Stars
《汇编语言(第四版)》 - 王爽 - 实验/检查点 | Assembly (4th Edition) - WangShuang - Labs
An open-source tool-augmented conversational language model from Fudan University
竞争性自适应重加权采样法(competitive adapative reweighted sampling, CARS)python代码
A sample of usage about Vivado MIG IP core, which is normally deployed to control ddr memory on FPGA board.
Skylar20011211 / zju-icicles
Forked from QSCTech/zju-icicles浙江大学课程攻略共享计划
This is the RV32I CPU with scoreboard and supports the expection and interrupt
These are Lab reports for Computer Architecture given by Xiaohong Jiang, Zhejiang University
This is a simple RV32IZ pipelines CPU supports forwarding and branch-not-taken.
a repo for computer architecture course code, at USTC, 2022 spring
Labs of Computer Architecture in 2021 Spring, USTC
some resources for CS courses of USTC
Repository for USTC-ComputerArchitecture 2021spring labs
Implementation of a simple RISCV architecture CPU using a 5-stage pipeline in Verilog.
RISC-V multi cycle CPU. Project of Computer Organization (THU 2020)