Repository for USTC-ComputerArchitecture 2021spring labs.
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Answer the questions and fix bugs in given graph.

1. Create normal CPU srcs based on given files.
2. Obtain harzard unit.
3. Add CSR instructions.
4. Add Lab Report.
   warning: you can definitely implement CSR in EX stage! So you don't need to implement too many forwardings like this one. Another way is to get another independent ALU specifically for CSR instructions.

1. Implement FIFO and LRU cache based on given cache.sv
2. Connect to CPU in LAB2 without CSR
3. Add Lab Report.

1. Implement BTB on Lab3 Cache CPU
2. Implement BHT based on step 1
3. Add counter (may not be the best way to count).

1. Finish Tomasulo simulator part
2. Finish Cache consistency simulator part.

Enjoy it!