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XiangShan
XiangShan PublicForked from OpenXiangShan/XiangShan
Open-source high-performance RISC-V processor
Scala
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openasip-RISCV
openasip-RISCV PublicForked from cpc/openasip
Open Application-Specific Instruction Set processor tools (OpenASIP)
C
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vrtlmod-FI
vrtlmod-FI PublicForked from tum-ei-eda/vrtlmod
vRTLmod modifies Verilator generated RTL simulation code for faul-injection purposes. It transforms source code with the help of LLVM/Clang-Tools and generates a fault injection API.
C++
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RV32ISC-Chisel
RV32ISC-Chisel PublicForked from github-3rr0r/RV32ISC
A RISC-V RV32I ISA Single Cycle CPU
Scala
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