Design-verification

UVM and Systemverilog based test benches for functional verification of a RAM module

I did this project to learn state of the art verification methodologies used in the industry.
The project is aimed at developing Systemverilog and UVM test benches for the functional verification of a RAM module.
ram.v is the verilog description of the ram module (UUT/DUT).
ram_tb.sv is the systemverilog based test bench for the ram module.
testbench.sv is the the UVM based test bench for the ram module.
interface.sv is the pin level interface of the ram module which is used across both the test benches.

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Name		Name	Last commit message	Last commit date
Latest commit History 6 Commits
README.md		README.md
interface.sv		interface.sv
ram.v		ram.v
ram_tb.sv		ram_tb.sv
testbench.sv		testbench.sv