Cutaia et al., 2015 - Google Patents

Vertical InAs-Si gate-all-around tunnel FETs integrated on Si using selective epitaxy in nanotube templates

Cutaia et al., 2015

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Document ID
9801523082716701038
Author
Cutaia D
Moselund K
Borg M
Schmid H
Gignac L
Breslin C
Karg S
Uccelli E
Riel H
Publication year
Publication venue
IEEE Journal of the Electron Devices Society

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In this paper, we introduce p-channel InAs-Si tunnel field-effect transistors (TFETs) fabricated using selective epitaxy in nanotube templates. We demonstrate the versatility of this approach, which enables III-V nanowire integration on Si substrates of any crystalline …
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