Mohan et al., 1994 - Google Patents

Ultrafast pipelined arithmetic using quantum electronic devices

Mohan et al., 1994

Document ID
7196795734992357371
Author
Mohan S
Mazumder P
Haddad G
Publication year
Publication venue
IEE Proceedings-Computers and Digital Techniques

External Links

Snippet

Negative differential resistance characteristics of several new quantum electronic devices have been used to design high-speed logic gates with the latching property. These latching gates form the basis of the ultrafast pipelined adder circuit described in this paper. The …
Continue reading at digital-library.theiet.org (other versions)

Classifications

    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making or -braking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making or -braking characterised by the components used
    • H03K17/92—Electronic switching or gating, i.e. not by contact-making or -braking characterised by the components used using superconductive devices
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application

Similar Documents

Publication Publication Date Title
Mohan et al. Ultrafast pipelined arithmetic using quantum electronic devices
US5903170A (en) Digital logic design using negative differential resistance diodes and field-effect transistors
Mazumder et al. Digital circuit applications of resonant tunneling devices
Balla et al. Low power dissipation MOS ternary logic family
Ng et al. Performance of CMOS differential circuits
Yuan et al. High-speed CMOS circuit technique
Iwamura et al. Single-electron majority logic circuits
Lu Implementation of iterative networks with CMOS differential logic
Cunha et al. Quaternary look-up tables using voltage-mode CMOS logic design
EP0626757A2 (en) Adiabatic dynamic logic
Shanbhag et al. Parallel implementation of a 4* 4-bit multiplier using a modified Booth's algorithm
González et al. CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differentiaI-resistance devices
Lu et al. Evaluation of two-summand adders implemented in ECDL CMOS differential logic
Sasipriya et al. Design of low power VLSI circuits using two phase adiabatic dynamic logic (2PADL)
Johnson et al. Design and analysis of asynchronous adders
Rjoub et al. Low-power/low-swing domino CMOS logic
Alioto et al. Performance evaluation of adiabatic gates
Nooshabadi et al. Fast feedthrough logic: A high performance logic family for GaAs
Current High density integrated computing circuitry with multiple valued logic
Pettenghi et al. Improved nanopipelined RTD adder using generalized threshold gates
Mazumder S. zyxwvutsrqponmlkjihgfedc
Thoidis et al. Multiple-valued logic voltage-mode storage circuits based on true-single-phase clocked logic
Haixia et al. Design of low-power quaternary flip-flop based on dynamic source-coupled logic
Gupta et al. An Algorithm for Nano-pipelining of Circuits and Architectures for a Nanotechnology
Mahmoodi-Meimand et al. Low-power, low-noise adder design with pass-transistor adiabatic logic