Gao et al., 2018 - Google Patents

Scaling package interconnects below 20µm pitch with hybrid bonding

Gao et al., 2018

Document ID
5411667383182098008
Author
Gao G
Mirkarimi L
Fountain G
Wang L
Uzoh C
Workman T
Guevara G
Mandalapu C
Lee B
Katkar R
Publication year
Publication venue
2018 IEEE 68th Electronic Components and Technology Conference (ECTC)

External Links

Snippet

The low-temperature direct bond interconnect commonly referred to as hybrid bonding technology is a promising solution for achieving an interconnect pitch smaller than 40μm. Wafer-to-wafer (W2W) direct bond interconnect technology has been in high volume …
Continue reading at ieeexplore.ieee.org (other versions)

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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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