Yamaoka et al., 2005 - Google Patents

A 300-MHz 25-/spl mu/A/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application …

Yamaoka et al., 2005

View PDF
Document ID
2930139554662548708
Author
Yamaoka M
Shinozaki Y
Maeda N
Shimazaki Y
Kato K
Shimada S
Yanagisawa K
Osada K
Publication year
Publication venue
IEEE journal of solid-state circuits

External Links

Snippet

An on-chip 1-Mb SRAM suitable for embedding in the application processor used in mobile cellular phones was developed. This SRAM supports three operating modes-high-speed active mode, low-leakage low-speed active mode, and standby mode-and uses a …
Continue reading at picture.iczhiku.com (PDF) (other versions)

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing, power reduction
    • G11C11/417Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing, power reduction for memory cells of the field-effect type
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power Management, i.e. event-based initiation of power-saving mode
    • G06F1/3234Action, measure or step performed to reduce power consumption
    • G06F1/3287Power saving by switching off individual functional units in a computer system, i.e. selective power distribution
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by G11C11/00
    • G11C5/14Power supply arrangements, e.g. Power down/chip (de)selection, layout of wiring/power grids, multiple supply levels
    • G11C5/147Voltage reference generators, voltage and current regulators ; Internally lowered supply level ; Compensation for voltage drops
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22Control and timing of internal memory operations
    • G11C2207/2227Standby or low power modes
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/10Decoders

Similar Documents

Publication Publication Date Title
Yamaoka et al. A 300-MHz 25-/spl mu/A/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor
Yamaoka et al. 90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique
Kanda et al. 90% write power-saving SRAM using sense-amplifying memory cell
US6798688B2 (en) Storage array such as a SRAM with reduced power requirements
US9361950B1 (en) Semiconductor device with reduced leakage current and method for manufacture of the same
US7936624B2 (en) Reduced power bitline precharge scheme for low power applications in memory devices
US7961499B2 (en) Low leakage high performance static random access memory cell using dual-technology transistors
US7379374B2 (en) Virtual ground circuit for reducing SRAM standby power
JP5791207B2 (en) Data processor having multiple low power modes
US7061820B2 (en) Voltage keeping scheme for low-leakage memory devices
CN108028057B (en) Single ended bit line current sense amplifier for SRAM applications
JP2004247026A (en) Semiconductor integrated circuit and ic card
JP2006040495A (en) Semiconductor integrated circuit device
Miyano et al. Highly energy-efficient SRAM with hierarchical bit line charge-sharing method using non-selected bit line charges
Kolar et al. A 32 nm high-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation
Itoh et al. Reviews and future prospects of low-voltage embedded RAMs
Yang et al. A low-power charge-recycling ROM architecture
US7505354B2 (en) Word line voltage control circuit for memory devices
US8743647B2 (en) Static read only memory device which consumes low stand-by leakage current
Yokoyama et al. 40-nm 64-kbit Buffer/Backup SRAM with 330 nW Standby Power at 65° C Using 3.3 V IO MOSs for PMIC less MCU in IoT Applications
Fukano et al. A 65nm 1Mb SRAM macro with dynamic voltage scaling in dual power supply scheme for low power SoCs
US7010706B2 (en) Apparatus having a first circuit supplying a power potential to a second circuit under a first operating mode otherwise decoupling the power potential
Goel et al. Area efficient diode and on transistor inter‐changeable power gating scheme with trim options for SRAM design in nano‐complementary metal oxide semiconductor technology
Narendra et al. Memory Leakage Reduction: SRAM and DRAM specific leakage reduction techniques
Tamba et al. A 1.5-ns 256-kb BiCMOS SRAM with 60-ps 11-k logic gates