이동윤, 2017 - Google Patents

Power Optimization Techniques Applicable in Pre/Post Placement Stages for Modern System-on-Chips

이동윤, 2017

View PDF
Document ID
155281925006281344
Author
이동윤
Publication year

External Links

Snippet

In this paper, we introduce two power optimization techniques applicable before and after placement stage. First, a new approach to the problem of allocating multi-bit flip-flops for data storage is presented. Previous approaches divide the allocation problem into two …
Continue reading at s-space.snu.ac.kr (PDF) (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081—Layout analysis, e.g. layout verification, design rule check
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5072—Floorplanning, e.g. partitioning, placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power Management, i.e. event-based initiation of power-saving mode
    • G06F1/3234—Action, measure or step performed to reduce power consumption
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78—Power analysis and optimization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/12—Design for manufacturability
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for programme control, e.g. control unit
    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled

Similar Documents

Publication Publication Date Title
Li et al. Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics
US7600208B1 (en) Automatic placement of decoupling capacitors
Singh et al. Power conscious CAD tools and methodologies: A perspective
US8595671B2 (en) Low-power FPGA circuits and methods
US7266797B2 (en) Automated and electrically robust method for placing power gating switches in voltage islands
US7840918B1 (en) Method and apparatus for physical implementation of a power optimized circuit design
US11003821B1 (en) Deterministic loop breaking in multi-mode multi-corner static timing analysis of integrated circuits
Frenkil The practical engineer [A multi-level approach to low-power IC design]
Lin et al. Pulsed-latch utilization for clock-tree power optimization
Guthaus et al. High-performance clock mesh optimization
US7092838B1 (en) Method and apparatus for the analysis and optimization of variability in nanometer technologies
Kapoor et al. Digital systems power management for high performance mixed signal platforms
US20140245251A1 (en) Design Optimization for Circuit Migration
TW201923823A (en) Integrated circuit design and methods of designing same and design system same
Seomun et al. Synthesis of active-mode power-gating circuits
US7480875B2 (en) Method of designing a semiconductor integrated circuit
Yi et al. Allocation of multi-bit flip-flops in logic synthesis for power optimization
Hsu et al. Crosstalk-aware power optimization with multi-bit flip-flops
US7260808B1 (en) Method and metric for low power standard cell logic synthesis
이동윤 Power Optimization Techniques Applicable in Pre/Post Placement Stages for Modern System-on-Chips
Mukheijee et al. Clock and power gating with timing closure
Ye et al. Power consumption in XOR-based circuits
Ahn et al. Design methodology for synthesizing resonant clock networks in the presence of dynamic voltage/frequency scaling
JPH1092942A (en) Apparatus and method for optimizing semiconductor integrated circuit
Posser et al. Electromigration Inside Logic Cells