Weerasekera, 2008 - Google Patents

System Interconnection Design Trade-offs in Three-Dimensional (3-D) Integrated Circuits

Weerasekera, 2008

View PDF
Document ID
14708171695425294462
Author
Weerasekera R
Publication year

External Links

Snippet

Continued technology scaling together with the integration of disparate technologies in a single chip means that device performance continues to outstrip interconnect and packaging capabilities, and hence there exist many difficult engineering challenges, most notably in …
Continue reading at www.diva-portal.org (PDF) (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5036Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78Power analysis and optimization
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation; Temperature sensing arrangements

Similar Documents

Publication Publication Date Title
Swaminathan et al. Power distribution networks for system-on-package: Status and challenges
Sylvester et al. Impact of small process geometries on microarchitectures in systems on a chip
Sriram et al. Physical Design for Multichip Modules
Ahn et al. A new framework of physics-based compact model predicts reliability of self-heated modern ICs: FinFET, NWFET, NSHFET comparison
Zhao et al. Field-based capacitance modeling for sub-65-nm on-chip interconnect
Tsai et al. Temperature-aware placement for SOCs
Sylvester et al. Rethinking deep-submicron circuit design
Salah et al. Arbitrary modeling of TSVs for 3D integrated circuits
Weerasekera et al. Two-dimensional and three-dimensional integration of heterogeneous electronic systems under cost, performance, and technological constraints
Ma et al. Formulae and applications of interconnect estimation considering shield insertion and net ordering
Zheng et al. Fast modeling of core switching noise on distributed LRC power grid in ULSI circuits
Weerasekera System Interconnection Design Trade-offs in Three-Dimensional (3-D) Integrated Circuits
Al Razi et al. Powersynth 2: Physical design automation for high-density 3-d multichip power modules
Evans et al. Electronic design automation (EDA) tools and considerations for electro-thermo-mechanical co-design of high voltage power modules
Khan et al. Designing TSVs for 3D integrated circuits
JP2005031850A (en) Power supply noise analysis method
Ihm et al. Comprehensive models for the investigation of on-chip switching noise generation and coupling
Eo et al. A compact multilayer IC package model for efficient simulation, analysis, and design of high-performance VLSI circuits
Vakanas et al. Effects of floating planes in three-dimensional packaging structures on simultaneous switching noise
Ma et al. 3D Interconnects with IC's Stack Global Electrical Context Consideration
Gopalakrishnan Energy Reduction for Asynchronous Circuits in SoC Applications
Ihm et al. Comprehensive model for on-chip power grid transient analysis and power grid-induced noise prediction
Daniel et al. Techniques for including dielectrics when extracting passive low-order models of high speed interconnect
Mao et al. Electromagnetic modelling of switching noise in on-chip power distribution networks
Chandrakar et al. Power and obstacle aware 3D clock tree synthesis