Ono et al., 1997 - Google Patents

Integrated and automated design-for-testability implementation for cell-based ICs

Ono et al., 1997

Document ID
13499847925949507106
Author
Ono T
Wakui K
Hikima H
Nakamura Y
Yoshida M
Publication year
Publication venue
Proceedings Sixth Asian Test Symposium (ATS'97)

External Links

Snippet

This paper presents several design-for-testability (DFT) techniques for cell-based ICs. In the design of cell-based ICs, embedded cores are often used along with the user defined random logic. The existence of embedded cores makes chip level testing more difficult and …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

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    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318572Input/Output interfaces
    • GPHYSICS
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    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
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    • G01R31/318555Control logic
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    • G01R31/318533Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558Addressing or selecting of subparts of the device under test
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    • G01R31/318533Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536Scan chain arrangements, e.g. connections, test bus, analog signals
    • GPHYSICS
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    • G01R31/318541Scan latches or cell details
    • GPHYSICS
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    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
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    • G01R31/318583Design for test
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    • G01R31/318594Timing aspects
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    • G01R31/319Tester hardware, i.e. output processing circuit
    • G01R31/31917Stimuli generation or application of test patterns to the device under test [DUT]
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    • G01R31/318505Test of Modular systems, e.g. Wafers, MCM's
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    • G01R31/31903Tester hardware, i.e. output processing circuit tester configuration
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    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
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    • G01R31/3177Testing of logic operation, e.g. by logic analysers
    • GPHYSICS
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    • G01R31/30Marginal testing, e.g. varying supply voltage
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    • G01R31/2851Testing of integrated circuits [IC]
    • GPHYSICS
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    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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    • GPHYSICS
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    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details

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