Nancollas, 2013 - Google Patents

Fully Automatic Standard Cell Creation in an Analog Generator Framework

Nancollas, 2013

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Document ID
11997141327777621036
Author
Nancollas R
Publication year
Publication venue
EECS Department, University of California, Berkeley

External Links

Snippet

Integrated circuit layout is a notoriously complicated and detail-oriented process. Thus, the growth of circuit complexity quickly led to the development of CAD tools to aid designers in keeping track of design rules and verifying their layout. Due to the repeatability of many …
Continue reading at eecs.berkeley.edu (PDF) (other versions)

Classifications

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    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081—Layout analysis, e.g. layout verification, design rule check
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
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    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • G—PHYSICS
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    • G06F17/5072—Floorplanning, e.g. partitioning, placement
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