Ogweno et al., 2015 - Google Patents
Power gating in asynchronous micropiplines for low power data driven computingOgweno et al., 2015
View PDF- Document ID
- 10115989535113757759
- Author
- Ogweno A
- Yakovlev A
- Degenaar P
- Publication year
- Publication venue
- 2015 11th Conference on Ph. D. Research in Microelectronics and Electronics (PRIME)
External Links
Snippet
In this work we explore the extent at which power gating in asynchronous micropipelines is beneficial at low operating voltages at different input data rates. In addition we present a further improvement to previous techniques by adding the delay blocks to the power gated …
- 238000000034 method 0 abstract description 9
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power Management, i.e. event-based initiation of power-saving mode
- G06F1/3234—Action, measure or step performed to reduce power consumption
- G06F1/3237—Power saving by disabling clock generation or distribution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power Management, i.e. event-based initiation of power-saving mode
- G06F1/3234—Action, measure or step performed to reduce power consumption
- G06F1/3287—Power saving by switching off individual functional units in a computer system, i.e. selective power distribution
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—INDEXING SCHEME RELATING TO CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. INCLUDING HOUSING AND APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B60/00—Information and communication technologies [ICT] aiming at the reduction of own energy use
- Y02B60/10—Energy efficient computing
- Y02B60/12—Reducing energy-consumption at the single machine level, e.g. processors, personal computers, peripherals, power supply
- Y02B60/1278—Power management
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—INDEXING SCHEME RELATING TO CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. INCLUDING HOUSING AND APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B60/00—Information and communication technologies [ICT] aiming at the reduction of own energy use
- Y02B60/10—Energy efficient computing
- Y02B60/12—Reducing energy-consumption at the single machine level, e.g. processors, personal computers, peripherals, power supply
- Y02B60/1207—Reducing energy-consumption at the single machine level, e.g. processors, personal computers, peripherals, power supply acting upon the main processing unit
- Y02B60/1217—Frequency modification
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—INDEXING SCHEME RELATING TO CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. INCLUDING HOUSING AND APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B60/00—Information and communication technologies [ICT] aiming at the reduction of own energy use
- Y02B60/10—Energy efficient computing
- Y02B60/12—Reducing energy-consumption at the single machine level, e.g. processors, personal computers, peripherals, power supply
- Y02B60/1232—Acting upon peripherals
- Y02B60/1235—Acting upon peripherals the peripheral being a bus
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/096—Synchronous circuits, i.e. using clock signals
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9450578B2 (en) | Integrated clock gater (ICG) using clock cascode complimentary switch logic | |
US8018247B2 (en) | Apparatus and method for reducing power consumption using selective power gating | |
Reddy | Low power-area Pass Transistor Logic based ALU design using low power full adder design | |
Ogweno et al. | Power gating in asynchronous micropiplines for low power data driven computing | |
US20190052254A1 (en) | Supply tracking delay element in multiple power domain designs | |
Shapiro et al. | Adaptive power gating of 32-bit Kogge Stone adder | |
Samanth et al. | Power reduction of a functional unit using rt-level clock-gating and operand isolation | |
Reynders et al. | Variation-resilient sub-threshold circuit solutions for ultra-low-power Digital Signal Processors with 10MHz clock frequency | |
Miyagi et al. | Low-powered self-timed pipeline with runtime fine-grain power supply | |
JP4698787B2 (en) | Performance-driven multi-variable variable supply voltage system for low power design of VLSI circuits and systems | |
Kawano et al. | Adjacent-state monitoring based fine-grained power-gating scheme for a low-power asynchronous pipelined system | |
Tamang et al. | A sub-threshold operation of XOR based energy efficient full adder | |
US9548735B1 (en) | System and method for adaptive power management | |
Tzartzanis et al. | Clock-powered CMOS VLSI graphics processor for embedded display controller application | |
Gupta et al. | Design and implementation of low power clock gated 64-bit ALU on ultra scale FPGA | |
Gupta et al. | Power efficient, clock gated multiplexer based full adder cell using 28 nm technology | |
Lee et al. | Comprehensive analysis and control of design parameters for power gated circuits | |
Singh et al. | Design and FPGA Synthesis of an Efficient Synchronous Counter with Clock-Gating Techniques | |
Nag et al. | An Autonomous Power and Clock Gating Technique in SRAM-Based FPGA | |
Nadella et al. | A dual threshold voltage modified dynamic power cutoff technique to consolidate leakage and speed in a VLSI subsystem | |
Khindria et al. | Low Power ALU using Wave Shaping Diode Adiabatic Logic | |
Mogheer | A new technology for reducing power consumption in synchronous digital design using tri-state buffer | |
Margala | Low-voltage adders for power-efficient arithmetic circuits | |
Dabholkar et al. | Optimised completion detection circuits for null convention logic pipelines | |
Kennedy et al. | Performance Analysis of a Low Power and High Speed Carry Select Adder |