WO2017185347A1 - 用于执行循环神经网络和lstm运算的装置和方法 - Google Patents

用于执行循环神经网络和lstm运算的装置和方法 Download PDF

Info

Publication number
WO2017185347A1
WO2017185347A1 PCT/CN2016/080744 CN2016080744W WO2017185347A1 WO 2017185347 A1 WO2017185347 A1 WO 2017185347A1 CN 2016080744 W CN2016080744 W CN 2016080744W WO 2017185347 A1 WO2017185347 A1 WO 2017185347A1
Authority
WO
WIPO (PCT)
Prior art keywords
unit
input
data
cell
neural network
Prior art date
Application number
PCT/CN2016/080744
Other languages
English (en)
French (fr)
Inventor
郭崎
陈峋宇
陈云霁
陈天石
Original Assignee
北京中科寒武纪科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 北京中科寒武纪科技有限公司 filed Critical 北京中科寒武纪科技有限公司
Priority to PCT/CN2016/080744 priority Critical patent/WO2017185347A1/zh
Priority to EP16899858.1A priority patent/EP3451239A4/en
Publication of WO2017185347A1 publication Critical patent/WO2017185347A1/zh
Priority to US16/174,193 priority patent/US11531860B2/en
Priority to US16/174,207 priority patent/US11727244B2/en

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/04Architecture, e.g. interconnection topology
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50Adding; Subtracting
    • G06F7/501Half or full adders, i.e. basic adder cells for one denomination
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52Multiplying; Dividing
    • G06F7/523Multiplying only
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30007Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001Arithmetic instructions
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/04Architecture, e.g. interconnection topology
    • G06N3/044Recurrent networks, e.g. Hopfield networks
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/04Architecture, e.g. interconnection topology
    • G06N3/048Activation functions
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/08Learning methods
    • G06N3/084Backpropagation, e.g. using gradient descent

Definitions

  • the invention relates to the field of artificial neural network technology, in particular to a cyclic neural network (RNN) and an LSTM, in particular to an apparatus and method for performing a cyclic neural network and an LSTM.
  • RNN cyclic neural network
  • LSTM LSTM
  • Cyclic neural networks and LSTM are widely used in speech recognition, language modeling, translation, picture description and other fields. In recent years, due to their high recognition accuracy and good parallelism, they have been increasingly influenced by academia and industry. Widespread concern.
  • One known method of supporting a cyclic neural network and LSTM is to use a general purpose processor.
  • the method supports the above algorithm by executing general purpose instructions using a general purpose register file and generic functions.
  • One of the disadvantages of this approach is that the performance of a single general purpose processor is low and does not meet the performance requirements of typical cyclic neural networks and LSTM operations.
  • communication between general-purpose processors becomes a performance bottleneck.
  • the general-purpose processor needs to decode the reverse operation of the cyclic neural network and LSTM into a sequence of long-column operations and fetch instructions, and the processor front-end decoding brings a large power consumption overhead.
  • Another known method of supporting cyclic neural networks and LSTM is to use a graphics processing unit (GPU).
  • the method supports the above algorithm by executing a generic SIMD instruction using a general purpose register file and a generic stream processing unit.
  • the GPU is a device dedicated to performing graphics and image operations and scientific calculations, without the special support for multi-layer artificial neural network operations, a large amount of front-end decoding work is still required to perform multi-layer artificial neural network operations, bringing a large number of Additional overhead.
  • the GPU has only a small on-chip cache, and the model data (weight) of the cyclic neural network and LSTM need to be repeatedly transferred from off-chip, and the off-chip bandwidth becomes the main performance bottleneck.
  • the GPU has only a small on-chip cache, and the cyclic neural network and LSTM model data (weight) need to be repeatedly transferred from off-chip. The off-chip bandwidth becomes the main performance bottleneck, and brings huge power consumption overhead.
  • An aspect of the present invention provides an apparatus for executing a cyclic neural network and an LSTM, comprising an instruction storage unit, a controller unit, a data access unit, an interconnection module, a main operation module, and a plurality of slave operation modules, wherein:
  • the instruction storage unit is configured to cache the instruction;
  • the controller unit is configured to read the instruction from the instruction storage unit, and decode the instruction into a micro instruction that controls the interconnection module, the main operation module, and the behavior of the operation module;
  • the data access unit Writing data from the memory to the main data processing unit and the corresponding data storage unit of each of the slave computing modules or reading data from the data storage unit to the memory;
  • the interconnecting module is used at the stage of starting the calculation of each layer of the neural network reverse training
  • the main arithmetic module transmits the input gradient vector of the layer to all the slave arithmetic modules through the interconnect module.
  • the interconnect module sequentially steps the output gradient vector portion of each slave computing module and the two pairs. Adding the output gradient vector of the layer; the arithmetic module is used to multiply and add the input data to obtain a partial sum and save, Until the neuron data is all input, the result is returned to the main operation module; the main operation module is used to perform interpolation activation on the sum returned from the operation module in the forward process, and the interpolation derivative is obtained in the reverse process and multiplied by the gradient.
  • the present invention also provides a method of performing a cyclic neural network and an LSTM operation using the above apparatus.
  • the device can be applied to the following (including but not limited to) scenarios: data processing, robots, computers, printers, scanners, phones, tablets, smart terminals, mobile phones, driving recorders, navigators, sensors, cameras, cloud servers , cameras, camcorders, projectors, watches, earphones, mobile storage, wearable devices and other electronic products; aircraft, ships, vehicles and other types of transportation; televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, Electric lights, gas stoves, range hoods and other household appliances; and including nuclear magnetic resonance instruments, B-ultrasound, electrocardiograph and other medical equipment.
  • FIG. 1 shows an example block diagram of an overall structure of an apparatus for executing a recurrent neural network and an LSTM according to an embodiment of the present invention
  • FIG. 2 is a view schematically showing the structure of an interconnection module in an apparatus for executing a cyclic neural network and an LSTM according to an embodiment of the present invention
  • FIG. 3 is a block diagram showing an example of a main operation module structure in an apparatus for executing a recurrent neural network and an LSTM according to an embodiment of the present invention
  • FIG. 4 is a block diagram showing an example of a slave operation module structure in an apparatus for executing a cyclic neural network and an LSTM according to an embodiment of the present invention
  • FIG. 5 illustrates an example block diagram of a cyclic neural network and an LSTM forward and reverse process in accordance with an embodiment of the present invention
  • Figure 6 shows a process of an operation of a device for performing a cyclic neural network and an LSTM using the present invention
  • Figure 7 is a structure of a cyclic neural network
  • Figure 8 is a block diagram of the LSTM algorithm
  • Figure 9 is a flow chart showing the cyclic neural network and LSTM single layer of the present invention.
  • Figure 10 is a flow chart showing the gradient back transfer of the single layer operation of the cyclic neural network and LSTM of the present invention.
  • FIG. 1 is a block diagram showing the overall structure of an apparatus for performing a cyclic neural network and an LSTM operation according to an embodiment of the present invention.
  • the apparatus includes an instruction storage unit 1, a controller unit 2, a data access unit 3, an interconnection module 4, a main operation module 5, and a plurality of slave operation modules 6.
  • the instruction storage unit 1, the controller unit 2, the data access unit 3, the interconnection module 4, the main operation module 5, and the slave operation module 6 can all pass hardware circuits (including but not limited to FPGA, CGRA, application specific integrated circuit ASIC, analog circuit). And memristor) implementation.
  • the instruction storage unit 1 reads in an instruction through the data access unit 3 and caches the read instruction.
  • the instruction memory unit 1 can be implemented by various memory devices (SRAM, DRAM, eDRAM, memristor, 3D-DRAM, and nonvolatile memory, etc.).
  • the controller unit 2 reads an instruction from the instruction storage unit 1, decodes the instruction into a microinstruction that controls the behavior of other units or modules, and sends it to the unit or module, such as the data access unit 3, the main operation module 5, and the slave.
  • the arithmetic module 6 and the like reads an instruction from the instruction storage unit 1, decodes the instruction into a microinstruction that controls the behavior of other units or modules, and sends it to the unit or module, such as the data access unit 3, the main operation module 5, and the slave.
  • the arithmetic module 6 and the like are examples of the instructions from the instruction storage unit 1, decodes the instruction into a microinstruction that controls the behavior of other units or modules, and sends it to the unit or module, such as the data access unit 3, the main operation module 5, and the slave.
  • the arithmetic module 6 and the like reads an instruction from the instruction storage unit 1, decodes the instruction into a microinstruction that controls the behavior of other units or modules, and sends it
  • the data access unit 3 is configured to access the external address space, directly read and write data to each storage unit inside the device, and complete loading and storage of the data.
  • the interconnection module is configured to distribute the input vector of the main operation module to the plurality of slave operation modules, and combine the calculation results of the slave operation modules and return to the main operation module.
  • Fig. 2 schematically shows a schematic structural view of an embodiment of the structure of an interconnection module.
  • the interconnection module 4 constitutes a data path between the main operation module 5 and the plurality of slave operation modules 6, and has an H-tree structure in this embodiment.
  • the H-tree is a binary tree path composed of multiple nodes. Each node sends the upstream data to the downstream two nodes in the same way, and the data returned by the two downstream nodes are combined and returned to the upstream node.
  • the neuron data in the main operation module 5 is sent to the respective slave operation modules 6 through the interconnection module 4; when the calculation process from the operation module 6 is completed Then, the value of each neuron data output from the arithmetic module is progressively formed into a complete vector of neuron data in the H-tree as an intermediate result vector. Assuming that there are N slave arithmetic modules in the device, the intermediate result vector is segmented by N, each segment has N elements, and the i-th slave arithmetic module calculates the i-th element in each segment.
  • the N elements are assembled into a vector of length N through the interconnect module and returned to the main arithmetic module. So if the network has only N output neurons, each slave unit only needs to output the value of a single neuron. If the network has m*N output neurons, each slave unit needs to output m neuron values.
  • the main arithmetic module performs interpolation activation on the sum returned from the arithmetic module in the forward direction, and the active derivative is obtained in the reverse interpolation and multiplied by the gradient.
  • the slave arithmetic module is configured to multiply and add the input data to obtain a partial sum and save until the neurons are all input to return the result to the main arithmetic module.
  • Fig. 3 shows an example block diagram of the structure of the main arithmetic module 5 in the apparatus for performing a cyclic neural network and LSTM operation according to the present invention.
  • the main operation module 5 includes an operation unit 51, a data dependency determination unit 52, and a neuron storage unit 53.
  • the neuron storage unit 53 is configured to buffer the input neuron data and the output neuron data used by the main operation module 5 in the calculation process.
  • the arithmetic unit 51 performs various arithmetic functions of the main arithmetic module.
  • the data dependency determining unit 52 is the arithmetic unit 51 reading and writing the neuron storage list.
  • the port of element 53 can also ensure that there is no consistency conflict between the reading and writing of data in the neuron storage unit 53.
  • the data dependency determining unit 52 determines whether there is a dependency relationship between the microinstruction that has not been executed and the data of the microinstruction that is being executed. If not, the microinstruction is allowed to be transmitted immediately, otherwise the microinstruction needs to wait until the micro The microinstruction is allowed to be transmitted after all the microinstructions on which the instruction depends are executed. For example, all microinstructions sent to the data dependency unit 52 are stored in an instruction queue internal to the data dependency unit 52, in which the read data of the read instruction ranges from the write command to the queue position. If the range of write data conflicts, the instruction must wait until the write instruction it depends on is executed.
  • the data dependency judging unit 52 is also responsible for reading the input gradient vector from the neuron storage unit 53 and transmitting it to the slave arithmetic module 6 through the interconnect module 4, and the output data from the arithmetic module 6 is directly sent to the operation through the interconnect module 4.
  • Unit 51 The command output from the controller unit 2 is sent to the arithmetic unit 51 and the dependency determining unit 52 to control its behavior.
  • each slave arithmetic module 6 includes an arithmetic unit 61, a data dependency determining unit 62, a neuron storage unit 63, a weight storage unit 64, and a weight gradient storage unit 65.
  • the arithmetic unit 61 receives the microinstructions issued by the controller unit 2 and performs an arithmetic logic operation.
  • the data dependency judging unit 62 is responsible for reading and writing operations on the storage unit in the calculation process.
  • the data dependency judging unit 62 ensures that there is no consistency conflict with the reading and writing of the storage unit.
  • the data dependency determining unit 62 determines whether there is a dependency relationship between the microinstruction that has not been executed and the data of the microinstruction that is being executed, and if not, allows the microinstruction to be immediately transmitted, otherwise it is necessary to wait until the micro The microinstruction is allowed to be transmitted after all the microinstructions on which the instruction depends are executed.
  • all microinstructions sent to the data dependency unit 62 are stored in an instruction queue inside the data dependency unit 62, in which the range of read data of the read instruction is a write command ahead of the queue position. If the range of write data conflicts, the instruction must wait until the write instruction it depends on is executed.
  • the neuron storage unit 63 buffers the scalar data corresponding to the slave arithmetic module 6 in the input vector data and the output vector partial sum calculated by the slave arithmetic module 6.
  • the weight buffer unit 64 buffers the weight data required by the slave computing module 6 in the calculation process. For each slave arithmetic module, only the columns in the weight matrix corresponding to the scalar data stored by the slave arithmetic module 6 are stored.
  • the weight gradient buffer unit 65 buffers the weight gradient data required by the corresponding slave module in updating the weights.
  • Each weight gradient data stored from the arithmetic module 6 corresponds to its stored weight gradient data.
  • the first half of the parallel and the update of the weights can be paralleled from the operation module 6 to implement the output gradient vector of the cyclic neural network and the LSTM.
  • the multiplication of the weight matrix w and the input gradient vector in_data can be divided into unrelated parallel computing subtasks, out and in_data are column vectors, and each slave computing module only computes the corresponding in_data
  • the product of the partial scalar element and the column corresponding to the weight matrix w, each output vector obtained is a sum of the sum of the final results, and these parts are summed in the H-tree step by step to obtain the final result. . So the computational process becomes a parallel computational part of the process and the subsequent accumulation process.
  • Each of the slave arithmetic modules 6 calculates a partial sum of the output vectors, and all of the sums are summed in the interconnect module 4 to obtain the final output vector.
  • Each slave arithmetic module 6 simultaneously multiplies the input vector and the output value of each layer in the forward operation to calculate a weight to update the weight stored by the slave arithmetic module 6.
  • Forward and reverse training are the two main processes of neural network algorithms. To train (update) the weights in the network, the neural network needs to calculate the forward output of the input vector in the network composed of the current weights. This is positive. To the process, the weight of each layer is trained (updated) layer by layer according to the difference between the output value and the label value of the input vector itself.
  • the output vector of each layer and the derivative value of the activation function are saved. These data are required for the reverse training process, so these data are guaranteed to exist at the beginning of the reverse training.
  • the output value of each layer in the forward operation is the data existing at the beginning of the reverse operation, and can be buffered in the main operation module by the data fetching unit and sent to the slave operation module through the H-tree.
  • the main operation module 5 performs subsequent calculation based on the output gradient vector, for example, multiplying the output gradient vector by the derivative of the activation function in the forward operation to obtain the input gradient value of the next layer.
  • Activation function in forward operation The derivative of the number is the data already existing at the beginning of the reverse operation, and can be cached in the main operation module by the data fetching unit.
  • an instruction set for performing an artificial neural network forward operation on the aforementioned apparatus includes the CONFIG instruction, the COMPUTE instruction, the IO instruction, the NOP instruction, the JUMP instruction, and the MOVE instruction, where:
  • the CONFIG command configures various constants required for current layer calculation before each layer of artificial neural network calculation begins;
  • the COMPUTE instruction completes the arithmetic logic calculation of each layer of artificial neural network
  • the IO instruction realizes reading input data required for calculation from the external address space and storing the data back to the external space after the calculation is completed;
  • the NOP instruction is responsible for clearing the microinstructions currently loaded into all internal microinstruction buffer queues, ensuring that all instructions preceding the NOP instruction are completed.
  • the NOP instruction itself does not contain any operations;
  • the JUMP instruction is responsible for the jump of the next instruction address that the controller will read from the instruction storage unit, and is used to implement the jump of the control flow;
  • the MOVE instruction is responsible for carrying data of an address in the internal address space of the device to another address in the internal address space of the device.
  • the process is independent of the operation unit and does not occupy the resources of the operation unit during execution.
  • FIG. 5 illustrates an example block diagram of a cyclic neural network and LSTM forward and reverse process in accordance with an embodiment of the present invention.
  • the input neuron vector is respectively subjected to a dot product operation with the weight vector of the slave operation module 6, to obtain a corresponding output neuron value, and all of the output neuron values constitute an intermediate result vector, and the intermediate result
  • the vector is subjected to the offset vector and the activation operation to obtain the final output neuron vector of the layer neural network.
  • the weight vector of each slave arithmetic module 6 is a column vector corresponding to the slave arithmetic module 6 in the weight matrix.
  • the interconnect module sends the input neuron vector [in0,...,inN] to all slave arithmetic units, temporarily stored in the neuron storage unit.
  • the dot product of its corresponding weight vector [w_i0, . . . , w_iN] and the input neuron vector is calculated.
  • the result output from the arithmetic unit is converted into a complete output vector through the interconnect module and returned to the main
  • the arithmetic unit performs an activation operation in the main operation unit to obtain a final output neuron vector [out0, out1, out2, ..., outN].
  • Figure 6 shows the process of implementing a cyclic neural network and LSTM operation using the apparatus and instruction set of the present invention.
  • step S1 an IO instruction is pre-stored at the first address of the instruction memory unit 1.
  • step S2 the operation starts, the controller unit 2 reads the IO instruction from the first address of the instruction storage unit 1, and according to the translated microinstruction, the data access unit 3 reads all the corresponding artificial neural network operations from the external address space.
  • the instruction is cached in the instruction storage unit 1.
  • step S3 the controller unit 2 then reads in the next IO instruction from the instruction storage unit, and according to the translated microinstruction, the data access unit 3 reads all data required by the main operation module 5 from the external address space (for example, including input).
  • the neuron vector, the interpolation table, the constant table, the offset, etc.) are supplied to the neuron storage unit 53 of the main operation module 5.
  • the controller unit 2 then reads the next IO instruction from the instruction storage unit, and based on the translated microinstruction, the data access unit 3 reads the weight matrix data required from the arithmetic module 6 from the external address space.
  • step S5 the controller unit 2 then reads the next CONFIG command from the instruction storage unit, and according to the translated microinstruction, the device configures various constants required for the calculation of the layer neural network.
  • the arithmetic unit 51, 61 configures the value of the unit internal register according to the parameters in the microinstruction, and the parameters include, for example, the accuracy setting of the layer calculation, the data of the activation function (for example, the precision bit of the layer calculation).
  • step S6 the controller unit 2 then reads the next COMPUTE instruction from the instruction storage unit.
  • the main operation module 5 first sends the input neuron vector to each slave operation module 6 through the interconnection module 4. It is saved to the neuron storage unit 63 of the slave arithmetic module 6.
  • step S7 according to the microinstruction decoded by the COMPUTE instruction, the weight vector is read from the weight storage unit 64 from the arithmetic unit 61 of the arithmetic module 6 (the weight matrix corresponds to the slave)
  • the column vector of the operation module 6 reads the input neuron vector from the neuron storage unit, completes the dot product operation of the weight vector and the input neuron vector, and returns the intermediate result through the interconnect module.
  • step S8 in the interconnect module 4, the intermediate results returned from each of the arithmetic modules 6 are progressively assembled into a complete intermediate result vector.
  • step S9 the main operation module 5 obtains the return value of the interconnection module 4, and reads the offset vector from the neuron storage unit 53 according to the micro-instruction decoded by the COMPUTE instruction, and adds it to the vector returned by the interconnection module 4, and then The addition result is then activated and the last output neuron vector is written back to the neuron storage unit 53.
  • step S10 the controller unit then reads the next IO instruction from the instruction storage unit.
  • the data access unit 3 stores the output neuron vector in the neuron storage unit 53 to the external address space designation address. The operation ends.
  • Figure 7 is the structure of a cyclic neural network.
  • the input of the cyclic neural network comes from the input of the current moment and the hidden layer output of the previous moment.
  • I is the number of inputs
  • H is the number of hidden layers
  • K is the number of outputs. among them Is the intermediate value of the hth output at time t, Is the hth output at time t after activation, Representing the residual pair Partial derivative, ⁇ represents the activation function.
  • Figure 8 shows the structure of a block of the LSTM algorithm.
  • LSTM introduces a cell to record information at the current point in time.
  • a block consists of three gates and one cell, input gate, output gate, and forget gate.
  • the main idea of the LSTM algorithm is to use the cell to record the current time state, and to pass the cell value to the previous time to achieve the function of directly transmitting information at different times.
  • the input gate and the forgotten gate are used to control the weight of the current time input and the last time cell in the output of the cell. Use the output gate to control the output of the cell. Under the control of the input gate and the forgotten gate, the appropriate information will be stored for a long time and recorded in the cell, thus solving the problem that the cyclic neural network decays with time.
  • Figure 9 is a flow chart showing the recurrent neural network and LSTM single layer of the present invention.
  • step A1 the product of the current moment input corresponding to the input gate and the weight is calculated and cached in the neuron buffer area, and then the product sum of the state of the previous time unit and the corresponding weight is calculated, and the hidden layer and the corresponding weight at the previous moment are calculated. The product sum exists in the buffer area. Finally add the three of them and activate to get the input threshold.
  • step A2 the product of the current moment input corresponding to the forgotten gate and the weight is calculated and cached in the neuron buffer area, and then the product sum of the state of the previous time unit and the corresponding weight is calculated, and the hidden layer and the corresponding weight at the previous moment are calculated. The product sum exists in the buffer area. Finally add the three of them and activate to get the forgotten threshold.
  • step A3 the product of the current moment input corresponding to the input gate and the weight value is calculated and buffered in the neuron buffer area, and then the memory area of the hidden layer and the corresponding weight value is calculated in the previous moment. Finally, add them two and activate to get the cell state intermediate value buffer to the neuron buffer. Then, the intermediate value is multiplied by the input gate, buffered in the buffer area of the arithmetic unit (51 in Fig. 7), and the cell state of the previous time is multiplied by the forgotten gate correspondingly, and the arithmetic unit is added to the previous cache correspondingly. , get the unit status value.
  • step A4 the product of the current time input corresponding to the output gate and the weight is calculated and buffered in the neuron buffer area, and then the product sum of the current time unit state and the corresponding weight is calculated, and the previous time hidden layer and the corresponding weight product are multiplied. And both have a buffer area. Finally add the three of them and activate to get the output threshold.
  • step A5 the unit state and the output gate are multiplied to obtain the output of the layer.
  • Figure 10 is a flow chart showing the gradient back transfer of the single layer operation of the cyclic neural network and LSTM of the present invention.
  • step B1 the weight of the hidden layer gradient and the corresponding position at the next moment is multiplied and the sum of the residual of the layer and the corresponding weight is multiplied to obtain the output gradient of the layer.
  • step B2 the output gradient and the cell activation value are multiplied and added, and the buffer is multiplied in the neuron buffer area by the activation function derivative to obtain an output gate gradient.
  • step B3 the state gradient of the cell is multiplied by the current output gradient and the derivative of the current output gate value and state activation into the neuron, and then the gradient of the cell at the next time and the gradient of the input gate and the forget gate and the output gate gradient at the current time are calculated. Multiplying the corresponding weights is stored in the neuron cache, and finally added to obtain the unit state gradient.
  • the gradient of the cell intermediate value is obtained by multiplying the current gate input activation value, the cell activation function derivative, and the cell state gradient.
  • step B4 the state gradients of all the cells at the current time are multiplied and multiplied by the cell state output at the previous time, and finally multiplied by the forgotten gate derivative to obtain a gradient of the forgotten gate.
  • step B5 the state gradients of all the cells at the current time are multiplied by the activation value of the median value of the current time, and the output is added and finally multiplied by the input gate derivative to obtain the gradient of the input gate.
  • the implementation process is similar to the above typical calculation. According to the formula, the corresponding weights and data are taken to perform weighted summation. For a long time, the next layer of operation instructions will be the main operation. The output neuron address of the upper layer stored in the unit is used as the input neuron address of this layer. Similarly, the weight address and offset address in the instruction are also changed to the address corresponding to this layer.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Software Systems (AREA)
  • Biophysics (AREA)
  • Biomedical Technology (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Computational Linguistics (AREA)
  • Data Mining & Analysis (AREA)
  • Molecular Biology (AREA)
  • Artificial Intelligence (AREA)
  • Mathematical Physics (AREA)
  • General Health & Medical Sciences (AREA)
  • Evolutionary Computation (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Neurology (AREA)
  • Image Analysis (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Mobile Radio Communication Systems (AREA)

Abstract

一种用于执行循环神经网络和LSTM的装置,包括指令存储单元(1)、控制器单元(2)、数据访问单元(3)、互连模块(4)、主运算模块(5)以及多个从运算模块(6)。从运算模块(6)用于将输入数据进行乘加得到部分和并保存,直到神经元数据全都输入将结果返回给主运算模块(5);主运算模块(5)用于在正向过程时对从运算模块(6)返回的和进行插值激活,在反向过程时插值得到激活导数并且与梯度相乘。该装置能够解决CPU和GPU运算性能不足、前端译码开销大的问题,有效提高了对多层人工神经网络正向运算的支持。

Description

用于执行循环神经网络和LSTM运算的装置和方法 技术领域
本发明人工神经网络技术领域,具体涉及循环神经网络(RNN)和LSTM,特别是一种用于执行循环神经网络和LSTM的装置和方法。
背景技术
循环神经网络和LSTM被广泛应用于语音识别,语言建模,翻译,图片描述等领域,近年来由于其较高的识别准确度和较好的可并行性,受到学术界和工业界越来越广泛的关注。
一种支持循环神经网络和LSTM的已知方法是使用通用处理器。该方法通过使用通用寄存器堆和通用功能部件执行通用指令来支持上述算法。该方法的缺点之一是单个通用处理器的运算性能较低,无法满足通常的循环神经网络和LSTM运算的性能需求。而多个通用处理器并行执行时,通用处理器之间相互通信又成为了性能瓶颈。另外,通用处理器需要把循环神经网络和LSTM的反向运算译码成一长列运算及访存指令序列,处理器前端译码带来了较大的功耗开销
另一种支持循环神经网络和LSTM的已知方法是使用图形处理器(GPU)。该方法通过使用通用寄存器堆和通用流处理单元执行通用SIMD指令来支持上述算法。由于GPU是专门用来执行图形图像运算以及科学计算的设备,没有对多层人工神经网络运算的专门支持,仍然需要大量的前端译码工作才能执行多层人工神经网络运算,带来了大量的额外开销。另外GPU只有较小的片上缓存,循环神经网络和LSTM的模型数据(权值)需要反复从片外搬运,片外带宽成为了主要性能瓶颈。另外,GPU只有较小的片上缓存,循环神经网络和LSTM的模型数据(权值)需要反复从片外搬运,片外带宽成为了主要性能瓶颈,同时带来了巨大的功耗开销。
发明内容
本发明的一个方面提供了一种用于执行循环神经网络和LSTM的装置,包括指令存储单元、控制器单元、数据访问单元、互连模块、主运算模块、以及多个从运算模块,其中:指令存储单元用于缓存指令;控制器单元用于从指令存储单元读取指令,并将该指令译码成控制互连模块、主运算模块、以及从运算模块行为的微指令;数据访问单元用于从内存向主运算模块和各从运算模块的相应数据存储单元中写数据或从所述数据存储单元向内存读数据;互连模块用于,在每层神经网络反向训练开始计算的阶段,主运算模块通过互连模块向所有的从运算模块传输本层的输入梯度向量,在从计算模块的计算过程完成后,互连模块逐级将各从计算模块的输出梯度向量部分和两两相加得到本层的输出梯度向量;从运算模块用于将输入数据进行乘加得到部分和并保存,直到神经元数据全都输入将结果返回给主运算模块;主运算模块用于在正向过程时对从运算模块返回的和进行插值激活,在反向过程时插值得到激活导数并且与梯度相乘。
本发明还提供了一种使用上述装置执行循环神经网络和LSTM运算的方法。
该装置可以应用于以下(包括但不限于)场景中:数据处理、机器人、电脑、打印机、扫描仪、电话、平板电脑、智能终端、手机、行车记录仪、导航仪、传感器、摄像头、云端服务器、相机、摄像机、投影仪、手表、耳机、移动存储、可穿戴设备等各类电子产品;飞机、轮船、车辆等各类交通工具;电视、空调、微波炉、冰箱、电饭煲、加湿器、洗衣机、电灯、燃气灶、油烟机等各类家用电器;以及包括核磁共振仪、B超、心电图仪等各类医疗设备。
附图说明
图1示出了根据本发明实施例的用于执行循环神经网络和LSTM的装置的整体结构的示例框图;
图2示意性示出了根据本发明实施例的用于执行循环神经网络和LSTM的装置中互连模块的结构;
图3示出了根据本发明实施例的用于执行循环神经网络和LSTM的装置中主运算模块结构的示例框图;
图4示出了根据本发明实施例的用于执行循环神经网络和LSTM的装置中从运算模块结构的示例框图;
图5示出了根据本发明实施例的循环神经网络和LSTM正反向过程的示例框图;
图6示出了利用本发明的执行循环神经网络和LSTM的装置的运算的过程;
图7是循环神经网络的结构;
图8是LSTM算法的一个block的结构;
图9示出了本发明的循环神经网络和LSTM单层的流程图;
图10示出了本发明的循环神经网络和LSTM的单层运算的梯度反向传递流程图。
具体实施方式
图1示出了本发明实施例的用于执行循环神经网络和LSTM运算的装置的整体结构示意图。如图1所示,该装置包括指令存储单元1、控制器单元2、数据访问单元3、互连模块4、主运算模块5和多个从运算模块6。指令存储单元1、控制器单元2、数据访问单元3、互连模块4、主运算模块5和从运算模块6均可以通过硬件电路(包括但不限于FPGA、CGRA、专用集成电路ASIC、模拟电路和忆阻器)实现。
指令存储单元1通过数据访问单元3读入指令并缓存读入的指令。指令存储单元1可以通过各种不同存储器件(SRAM、DRAM、eDRAM、忆阻器、3D-DRAM和非易失存储等)实现。
控制器单元2从指令存储单元1中读取指令,将指令译码成控制其他单元或模块行为的微指令,并发送给所述单元或模块,例如数据访问单元3、主运算模块5和从运算模块6等。
数据访问单元3用于访存外部地址空间,直接向装置内部的各个存储单元读写数据,完成数据的加载和存储。
述互连模块用于将所述主运算模块的输入向量分发给所述多个从运算模块,以及将各从运算模块的计算结果合并后返回给主运算模块。图2示意性示出了互连模块的结构的一种实施方式的结构示意图。互连模块4构成主运算模块5和多个从运算模块6之间的数据通路,在该实施例中具有H树型的结构。H树是由多个节点构成的二叉树通路,每个节点将上游的数据同样地发给下游的两个节点,将下游的两个节点返回的数据进行合并,并返回给上游的节点。
以典型的循环神经网络和LSTM的计算out=∑w×in_data为例,主运算模块5内的神经元数据通过互连模块4发送给各个从运算模块6;当从运算模块6的计算过程完成后,每个从运算模块输出的神经元数据的值会在H树中逐级拼成一个完整的由神经元数据组成的向量,作为中间结果向量。假设装置中共有N个从运算模块,则中间结果向量按N分段,每段有N个元素,第i个从运算模块计算每段中的第i个元素。N个元素经过互连模块拼成长度为N的向量并返回给主运算模块。所以如果网络只有N个输出神经元,则每个从运算单元只需输出单个神经元的值,若网络有m*N个输出神经元,则每个从运算单元需输出m个神经元值。
在本发明中,主运算模块在正向对从运算模块返回的和进行插值激活,在反向插值得到激活导数并且与梯度相乘。
在本发明中,从运算模块用于将输入数据进行乘加得到部分和并保存,直到神经元全都输入将结果返回给主运算模块。
图3示出了根据本发明用于执行循环神经网络和LSTM运算的装置中主运算模块5的结构的示例框图。如图3所示,主运算模块5包括运算单元51、数据依赖关系判断单元52和神经元存储单元53。
神经元存储单元53用于缓存主运算模块5在计算过程中用到的输入神经元数据和输出神经元数据。运算单元51完成主运算模块的各种运算功能。数据依赖关系判断单元52是运算单元51读写神经元存储单 元53的端口,同时能够保证对神经元存储单元53中数据的读写不存在一致性冲突。
具体地,数据依赖关系判断单元52判断尚未执行的微指令与正在执行过程中的微指令的数据之间是否存在依赖关系,如果不存在,允许该条微指令立即发射,否则需要等到该条微指令所依赖的所有微指令全部执行完成后该条微指令才允许被发射。例如,所有发往数据依赖关系单元52的微指令都会被存入数据依赖关系单元52内部的指令队列里,在该队列中,读指令的读取数据的范围如果与队列位置靠前的写指令写数据的范围发生冲突,则该指令必须等到所依赖的写指令被执行后才能够执行。同时,数据依赖关系判断单元52也负责从神经元存储单元53读取输入梯度向量通过互连模块4发送给从运算模块6,而从运算模块6的输出数据通过互连模块4直接发送给运算单元51。控制器单元2输出的指令发送给运算单元51和依赖关系判断单元52,来控制其行为。
图4示出了根据本发明的用于执行循环神经网络和LSTM的装置的从运算模块6的结构的示例框图。如图4所示,每个从运算模块6包括运算单元61、数据依赖关系判定单元62、神经元存储单元63、权值存储单元64和权值梯度存储单元65。
运算单元61接收控制器单元2发出的微指令并进行算数逻辑运算。
数据依赖关系判断单元62负责计算过程中对存储单元的读写操作。数据依赖关系判断单元62保证对存储单元的读写不存在一致性冲突。具体地,数据依赖关系判断单元62判断尚未执行的微指令与正在执行过程中的微指令的数据之间是否存在依赖关系,如果不存在,允许该条微指令立即发射,否则需要等到该条微指令所依赖的所有微指令全部执行完成后该条微指令才允许被发射。例如,所有发往数据依赖关系单元62的微指令都会被存入数据依赖关系单元62内部的指令队列里,在该队列中,读指令的读取数据的范围如果与队列位置靠前的写指令写数据的范围发生冲突,则该指令必须等到所依赖的写指令被执行后才能够执行。
神经元存储单元63缓存输入向量数据中与该从运算模块6相对应的标量数据以及该从运算模块6计算得到的输出向量部分和。
权值缓存单元64缓存该从运算模块6在计算过程中需要的权值数据。对于每一个从运算模块,都只会存储权值矩阵中与该从运算模块6所存储的标量数据相对应的列。
权值梯度缓存单元65缓存相应从运算模块在更新权值过程中需要的权值梯度数据。每一个从运算模块6存储的权值梯度数据与其存储的权值梯度数据相对应。
从运算模块6实现循环神经网络和LSTM的输出梯度向量的过程中可以并行的前半部分以及权值的更新。
以out=∑w×in_data为例,其中权值矩阵w和输入梯度向量in_data的乘法可以划分为不相关的并行计算子任务,out与in_data是列向量,每个从运算模块只计算in_data中相应的部分标量元素与权值矩阵w对应的列的乘积,得到的每个输出向量都是最终结果的一个待累加的部分和,这些部分和在H树中逐级两两相加得到最后的结果。所以计算过程变成了并行的计算部分和的过程和后面的累加的过程。每个从运算模块6计算出输出向量的部分和,所有的部分和在互连模块4中完成求和运算得到最后的输出向量。每个从运算模块6同时将输入向量和正向运算时每层的输出值相乘,计算出权值,以更新本从运算模块6存储的权值。正向运算和反向训练是神经网络算法的两个主要过程,神经网络要训练(更新)网络中的权值,首先需要计算输入向量在当前权值构成的网络中的正向输出,这是正向过程,然后根据输出值与输入向量本身的标注值之间的差值,反向逐层训练(更新)每层的权值。在正向计算过程中会保存每一层的输出向量以及激活函数的导数值,这些数据是反向训练过程所需要的,所以在反向训练开始时,这些数据已经保证存在。正向运算中每层的输出值是反向运算开始时已有的数据,可以通过数据访存单元缓存在主运算模块中并通过H树发送给从运算模块。主运算模块5基于输出梯度向量进行后续计算,例如将输出梯度向量乘以正向运算时的激活函数的导数得到下一层的输入梯度值。正向运算时的激活函 数的导数是在反向运算开始时已有的数据,可以通过数据访存单元缓存在主运算模块中。
根据本发明实施例,还提供了在前述装置上执行人工神经网络正向运算的指令集。指令集中包括CONFIG指令、COMPUTE指令、IO指令、NOP指令、JUMP指令和MOVE指令,其中:
CONFIG指令在每层人工神经网络计算开始前配置当前层计算需要的各种常数;
COMPUTE指令完成每层人工神经网络的算术逻辑计算;
IO指令实现从外部地址空间读入计算需要的输入数据以及在计算完成后将数据存回至外部空间;
NOP指令负责清空当前装至内部所有微指令缓存队列中的微指令,保证NOP指令之前的所有指令全部指令完毕。NOP指令本身不包含任何操作;
JUMP指令负责控制器将要从指令存储单元读取的下一条指令地址的跳转,用来实现控制流的跳转;
MOVE指令负责将装置内部地址空间某一地址的数据搬运至装置内部地址空间的另一地址,该过程独立于运算单元,在执行过程中不占用运算单元的资源。
图5示出了根据本发明实施例的循环神经网络和LSTM正反向过程的示例框图。在不同从运算模块6中,输入神经元向量分别与该从运算模块6的权值向量进行点积运算,得到对应的输出神经元值,所有这些输出神经元值组成中间结果向量,该中间结果向量经过加偏置向量以及激活运算得到该层神经网络的最终输出神经元向量,公式描述为out=∑w×in_data。每个从运算模块6的权值向量是权值矩阵中与该从运算模块6相对应的列向量。互连模块将输入神经元向量[in0,...,inN]发送给所有的从运算单元,暂存在神经元存储单元中。对于第i个从运算单元,计算其相应的权值向量[w_i0,...,w_iN]与输入神经元向量的点积。从运算单元输出的结果经过互连模块拼成完整的输出向量并返回给主 运算单元,在主运算单元中进行激活运算,得到最后的输出神经元向量[out0,out1,out2,...,outN]。
图6显示了利用本发明的装置和指令集实现循环神经网络和LSTM运算的过程。
在步骤S1,在指令存储单元1的首地址处预先存入一条IO指令。
在步骤S2,运算开始,控制器单元2从指令存储单元1的首地址读取该条IO指令,根据译出的微指令,数据访问单元3从外部地址空间读取相应的所有人工神经网络运算指令,并将其缓存在指令存储单元1中。
在步骤S3,控制器单元2接着从指令存储单元读入下一条IO指令,根据译出的微指令,数据访问单元3从外部地址空间读取主运算模块5需要的所有数据(例如,包括输入神经元向量、插值表、常数表和偏置等)至主运算模块5的神经元存储单元53。
在步骤S4,控制器单元2接着从指令存储单元读入下一条IO指令,根据译出的微指令,数据访问单元3从外部地址空间读取从运算模块6需要的权值矩阵数据。
在步骤S5,控制器单元2接着从指令存储单元读入下一条CONFIG指令,根据译出的微指令,装置配置该层神经网络计算需要的各种常数。例如,运算单元51、61根据微指令里的参数配置单元内部寄存器的值,所述参数例如包括本层计算的精度设置、激活函数的数据(例如本层计算的精度位)。
在步骤S6,控制器单元2接着从指令存储单元读入下一条COMPUTE指令,根据译出的微指令,主运算模块5首先通过互连模块4将输入神经元向量发给各从运算模块6,保存至从运算模块6的神经元存储单元63。
在步骤S7,根据COMPUTE指令译出的微指令,从运算模块6的运算单元61从权值存储单元64读取权值向量(权值矩阵中对应于该从 运算模块6的列向量),从神经元存储单元读取输入神经元向量,完成权值向量和输入神经元向量的点积运算,将中间结果通过互连模块返回。
在步骤S8,在互连模块4中,各从运算模块6返回的中间结果被逐级拼成完整的中间结果向量。
在步骤S9,主运算模块5得到互连模块4的返回值,根据COMPUTE指令译出的微指令,从神经元存储单元53读取偏置向量,与互连模块4返回的向量相加,然后再对相加结果做激活,并将最后的输出神经元向量写回至神经元存储单元53。
在步骤S10,控制器单元接着从指令存储单元读入下一条IO指令,根据译出的微指令,数据访问单元3将神经元存储单元53中的输出神经元向量存至外部地址空间指定地址,运算结束。
图7是循环神经网络的结构。为了解决传统神经网络在时间上对于以前的输入的依赖,正向运算的时候,循环神经网络的输入来自当前时刻的输入以及上一时刻的隐层输出。公式中I为输入数量,H为隐层数量,K为输出数量。其中
Figure PCTCN2016080744-appb-000001
是t时刻第h个输出的中间值,
Figure PCTCN2016080744-appb-000002
是激活后t时刻的第h个输出,
Figure PCTCN2016080744-appb-000003
表示残差对
Figure PCTCN2016080744-appb-000004
的偏导数,θ表示激活函数。
正向传播的公式表达为:
Figure PCTCN2016080744-appb-000005
Figure PCTCN2016080744-appb-000006
反向传播的公式表达:
Figure PCTCN2016080744-appb-000007
其中。通过对于上一时刻的隐层和本层输出的连接来达到综合时间序列的作用。但是这样的循环神经网络存在时间衰减的问题。
图8是LSTM算法的一个block的结构。相对于传统循环神经网络,LSTM引入了一个cell来记录当前时间点的信息。可以看出在LSTM算法里,一个block由三个门和一个cell组成,输入门、输出门、忘记门。 LSTM算法的主要思想是利用cell来记录当前时间的状态,对上一时刻传入cell值来达到在不同时间直接传递信息的功能。用输入门和忘记门来控制cell的输出里对于当前时间输入和上一时间cell的权重。用输出门来控制cell的输出。在输入门和忘记门的控制下,合适的信息将会被保存很长时间,一直记录在cell里面,这样就解决了循环神经网络随着时间衰减的问题。
图9示出了本发明的循环神经网络和LSTM单层的流程图。
在步骤A1,计算出输入门对应的当前时刻输入与权值的乘积和缓存在神经元缓存区,再计算上一时刻单元状态与对应权值的乘积和以及上一时刻隐层与对应权值乘积和都存在缓存区。最后将他们三个相加并且激活得到输入门值。
在步骤A2,计算出忘记门对应的当前时刻输入与权值的乘积和缓存在神经元缓存区,再计算上一时刻单元状态与对应权值的乘积和以及上一时刻隐层与对应权值乘积和都存在缓存区。最后将他们三个相加并且激活得到忘记门值。
在步骤A3,计算出输入门对应的当前时刻输入与权值的乘积和缓存在神经元缓存区,再计算上一时刻隐层与对应权值乘积和都存在缓存区。最后将他们两个个相加并且激活得到单元状态中间值缓存到神经元缓存区。然后让中间值和输入门对应相乘,缓存在运算单元(图7的51)缓存区内,再让上一时刻的单元状态和忘记门对应相乘,在运算单元与上一次缓存对应相加,得到单元状态值。
在步骤A4,计算出输出门对应的当前时刻输入与权值的乘积和缓存在神经元缓存区,再计算当前时刻单元状态与对应权值的乘积和以及上一时刻隐层与对应权值乘积和都存在缓存区。最后将他们三个相加并且激活,得到输出门值。
在步骤A5,单元状态和输出门对应相乘得到本层输出。
图10示出了本发明的循环神经网络和LSTM的单层运算的梯度反向传递流程图。
在步骤B1,计算出下一时刻隐层梯度和对应位置的权值相乘相加加上本层残差和对应权值相乘之和,得到本层输出梯度。
在步骤B2,让输出梯度和cell激活值对应乘加,缓存在神经元缓存区最后乘以激活函数导数得到输出门梯度。
在步骤B3将cell的状态梯度由当前输出梯度乘上当前输出门值和状态激活的导数存入神经元,再计算上下一时刻cell的梯度,输入门和忘记门的梯度以及本时刻输出门梯度乘以对应权值都存入神经元缓存,最后相加得到单元状态梯度。cell中间值的梯度由当前时刻输入门激活值,cell激活函数导数以及cell状态梯度相乘得到。
在步骤B4,将当前时刻所有cell的状态梯度对应乘以上一时刻cell状态输出相加最后与忘记门导数相乘得到忘记门的梯度。
在步骤B5,将当前时刻所有cell的状态梯度对应乘以本时刻cell中间值的激活值输出相加最后与输入门导数相乘得到输入门的梯度。
值得一提的是,传统循环神经网络算法应用在此装置上是极大简化了的LSTM算法,计算输出的时候只依赖当前时刻输入和上一时刻输出,正反向表达与LSTM的运行子过程类似,在此不做赘述。
对于一次完整的循环神经网络和LSTM算法,其实现过程与以上典型的计算类似,按照公式取出相应的权值和数据进行加权求和,长时间的时候,下一层的运算指令会将主运算单元中存储的上一层的输出神经元地址作为本层的输入神经元地址。同样地,指令中的权值地址和偏置地址也会变更至本层对应的地址。
通过采用用于执行循环神经网络和LSTM的装置和指令集,解决了CPU和GPU运算性能不足,前端译码开销大的问题。有效提高了对多层人工神经网络正向运算的支持。
通过采用针对循环神经网络和LSTM的专用片上缓存,充分挖掘了输入神经元和权值数据的重用性,避免了反复向内存读取这些数据,降低了内存访问带宽,避免了内存带宽成为多层人工神经网络正向运算性能瓶颈的问题。

Claims (8)

  1. 一种用于执行循环神经网络和LSTM运算的装置,包括指令存储单元、控制器单元、互连模块、主运算模块和多个从运算模块,其中,
    所述指令存储单元通过数据访问单元读入指令并缓存读入的指令;
    所述控制器单元从指令存储单元中读取指令,将指令译码成控制其他单元或模块行为的微指令,然后将各自的微指令分发至各个单元或模块;
    所述数据访问单元用于访问外部地址空间,完成数据的加载和存储;
    所述互连模块用于将所述主运算模块的输入向量分发给所述多个从运算模块,以及将各从运算模块的计算结果合并后返回给主运算模块;
    所述从运算模块用于将输入数据进行乘加得到部分和并保存,直到神经元数据全都输入将结果返回给主运算模块;
    所述主运算模块用于在正向过程时对从运算模块返回的和进行插值激活,在反向过程时插值得到激活导数并且与梯度相乘。
  2. 如权利要求1所述的用于执行循环神经网络和LSTM运算的装置,所述主运算模块包括运算单元、数据依赖关系判定单元、神经元缓存单元,其中,
    所述运算单元用于接收控制器单元发出的微指令并进行算数逻辑运算;
    所述数据依赖关系判断单元用于对神经元缓存单元进行读写操作,保证指令之间所用的数据不存在读写一致性冲突;
    所述神经元缓存单元用于缓存输入神经元数据和输出神经元数据。
  3. 如权利要求1所述的用于执行循环神经网络和LSTM运算的装置,所述从运算模块包括运算单元、数据依赖关系判定单元、神经元存储单元、权值存储单元和权值梯度存储单元,
    所述运算单元用于接收控制器单元发出的微指令并进行算数逻辑运算;
    所述数据依赖关系判断单元用于对神经元缓存单元进行读写操作,保证指令之间所用的数据不存在读写一致性冲突;
    所述神经元缓存单元用于缓存输入神经元数据和输出神经元数据。
    所述权值缓存单元用于缓存该从运算模块在计算过程中需要的权值数据;
    所述权值梯度缓存单元用于缓存相应从运算模块在更新权值过程中需要的权值梯度数据。
  4. 如权利要求1所述的用于执行循环神经网络和LSTM运算的装置,
    在循环神经网络和LSTM运算的正向过程进行以下计算过程:
    以下公式中表达参数的含义:
    wij表示从单位i到单位j的连接权值,
    Figure PCTCN2016080744-appb-100001
    表示t时刻j单位输入门的值,
    Figure PCTCN2016080744-appb-100002
    表示t时刻j单位输入门的激活值,下标l,
    Figure PCTCN2016080744-appb-100003
    ω,c分别表示输入门,输出门,忘记门和第c个cell。wcl
    Figure PCTCN2016080744-appb-100004
    w分别表示当前第c个cell到上一时刻的输入门,输出门,忘记门的连接权值,
    Figure PCTCN2016080744-appb-100005
    表达第c个cell在t时刻的状态,f、g、h都是激活函数,I表示输入大小,K表示输出大小,H表示隐层大小,h泛指cell和其他时刻的隐层连接,G表示所有对隐层的输入;
    为了简化表达,定义
    Figure PCTCN2016080744-appb-100006
    即残差对于第j个cell在t时刻的偏导数,下面的公式都是在一个时刻下的block完成的,其他时刻以此类推;
    以下是前向运算的公式表达,计算顺序按照给出公式顺序进行:
    输入门:
    Figure PCTCN2016080744-appb-100007
    忘记门:
    Figure PCTCN2016080744-appb-100008
    Cell:
    Figure PCTCN2016080744-appb-100009
    Cell状态:
    Figure PCTCN2016080744-appb-100010
    输出门:
    Figure PCTCN2016080744-appb-100011
    Cell输出:
    Figure PCTCN2016080744-appb-100012
  5. 如权利要求4所述的用于执行循环神经网络和LSTM运算的装置,
    在循环神经网络和LSTM运算的单层运算的梯度反向时进行以下计算过程:
    反向运算公式表达,计算顺序按照给出公式顺序进行:
    定义:
    Figure PCTCN2016080744-appb-100013
    Cell输出:
    Figure PCTCN2016080744-appb-100014
    输出门:
    Figure PCTCN2016080744-appb-100015
    Cell状态:
    Figure PCTCN2016080744-appb-100016
    Cell:
    Figure PCTCN2016080744-appb-100017
    忘记门:
    Figure PCTCN2016080744-appb-100018
    输入门:
    Figure PCTCN2016080744-appb-100019
  6. 一种用于执行循环神经网络和LSTM运算的方法,其中,
    利用多个从运算模块将输入数据进行乘加得到部分和并保存,直到神经元数据全都输入将结果返回给主运算模块;
    利用一个主运算模块在正向过程时对从运算模块返回的和进行插值激活,以及在反向过程时插值得到激活导数并且与梯度相乘。
  7. 如权利要求6所述的用于执行循环神经网络和LSTM运算的方法,
    在循环神经网络和LSTM运算的正向过程进行以下计算过程:
    以下公式中表达参数的含义:
    wij表示从单位i到单位j的连接权值,
    Figure PCTCN2016080744-appb-100020
    表示t时刻j单位输入门的值,
    Figure PCTCN2016080744-appb-100021
    表示t时刻j单位输入门的激活值,下标l,
    Figure PCTCN2016080744-appb-100022
    ω,c分别表示输入门,输出门,忘记门和第c个cell。wcl
    Figure PCTCN2016080744-appb-100023
    w分别表示当前第c个cell到上一时刻的输入门,输出门,忘记门的连接权值,
    Figure PCTCN2016080744-appb-100024
    表达第c个cell在t时刻的状态,f、g、h都是激活函数,I表示输入大小, K表示输出大小,H表示隐层大小,h泛指cell和其他时刻的隐层连接,G表示所有对隐层的输入;
    为了简化表达,定义
    Figure PCTCN2016080744-appb-100025
    即残差对于第j个cell在t时刻的偏导数,下面的公式都是在一个时刻下的block完成的,其他时刻以此类推;
    以下是前向运算的公式表达,计算顺序按照给出公式顺序进行:
    输入门:
    Figure PCTCN2016080744-appb-100026
    忘记门:
    Figure PCTCN2016080744-appb-100027
    Cell:
    Figure PCTCN2016080744-appb-100028
    Cell状态:
    Figure PCTCN2016080744-appb-100029
    输出门:
    Figure PCTCN2016080744-appb-100030
    Cell输出:
    Figure PCTCN2016080744-appb-100031
  8. 如权利要求7所述的用于执行循环神经网络和LSTM运算的装置,
    在循环神经网络和LSTM运算的单层运算的梯度反向时进行以下计算过程:
    反向运算公式表达,计算顺序按照给出公式顺序进行:
    定义:
    Figure PCTCN2016080744-appb-100032
    Cell输出:
    Figure PCTCN2016080744-appb-100033
    输出门:
    Figure PCTCN2016080744-appb-100034
    Cell状态:
    Figure PCTCN2016080744-appb-100035
    Cell:
    Figure PCTCN2016080744-appb-100036
    忘记门:
    Figure PCTCN2016080744-appb-100037
    输入门:
    Figure PCTCN2016080744-appb-100038
PCT/CN2016/080744 2016-04-29 2016-04-29 用于执行循环神经网络和lstm运算的装置和方法 WO2017185347A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/CN2016/080744 WO2017185347A1 (zh) 2016-04-29 2016-04-29 用于执行循环神经网络和lstm运算的装置和方法
EP16899858.1A EP3451239A4 (en) 2016-04-29 2016-04-29 APPARATUS AND METHOD FOR PERFORMING RECURRENT NEURONAL NETWORK AND LTSM CALCULATIONS
US16/174,193 US11531860B2 (en) 2016-04-29 2018-10-29 Apparatus and method for executing recurrent neural network and LSTM computations
US16/174,207 US11727244B2 (en) 2016-04-29 2018-10-29 Apparatus and method for executing recurrent neural network and LSTM computations

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/080744 WO2017185347A1 (zh) 2016-04-29 2016-04-29 用于执行循环神经网络和lstm运算的装置和方法

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US16/174,193 Continuation-In-Part US11531860B2 (en) 2016-04-29 2018-10-29 Apparatus and method for executing recurrent neural network and LSTM computations
US16/174,207 Continuation-In-Part US11727244B2 (en) 2016-04-29 2018-10-29 Apparatus and method for executing recurrent neural network and LSTM computations

Publications (1)

Publication Number Publication Date
WO2017185347A1 true WO2017185347A1 (zh) 2017-11-02

Family

ID=60160509

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/080744 WO2017185347A1 (zh) 2016-04-29 2016-04-29 用于执行循环神经网络和lstm运算的装置和方法

Country Status (3)

Country Link
US (2) US11531860B2 (zh)
EP (1) EP3451239A4 (zh)
WO (1) WO2017185347A1 (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108875601A (zh) * 2018-05-31 2018-11-23 郑州云海信息技术有限公司 动作识别方法和lstm神经网络训练方法和相关装置
US11042797B2 (en) 2019-01-08 2021-06-22 SimpleMachines Inc. Accelerating parallel processing of data in a recurrent neural network
WO2021212753A1 (zh) * 2020-04-23 2021-10-28 平安科技(深圳)有限公司 计算机性能数据确定方法、装置、计算机设备及存储介质
US11531860B2 (en) 2016-04-29 2022-12-20 Cambricon (Xi'an) Semiconductor Co., Ltd. Apparatus and method for executing recurrent neural network and LSTM computations

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110097179B (zh) * 2018-01-29 2020-03-10 上海寒武纪信息科技有限公司 计算机设备、数据处理方法及存储介质
US10657426B2 (en) * 2018-01-25 2020-05-19 Samsung Electronics Co., Ltd. Accelerating long short-term memory networks via selective pruning
CN109376853B (zh) * 2018-10-26 2021-09-24 电子科技大学 回声状态神经网络输出轴突电路
CN110288081A (zh) * 2019-06-03 2019-09-27 北京信息科技大学 一种基于fw机制及lstm的递归网络模型及学习方法
US11610125B2 (en) 2019-07-03 2023-03-21 Honda Motor Co., Ltd. Sensor fusion
US11580365B2 (en) * 2019-07-03 2023-02-14 Honda Motor Co., Ltd. Sensor fusion
CN112183715A (zh) * 2019-07-03 2021-01-05 本田技研工业株式会社 传感器融合
CA3116521A1 (en) * 2020-04-29 2021-10-29 Applied Brain Research Inc. Methods and systems for efficient processing of recurrent neural networks
CN111597819B (zh) * 2020-05-08 2021-01-26 河海大学 一种基于关键词的大坝缺陷图像描述文本生成方法
CN113051353B (zh) * 2021-03-05 2024-05-10 浙江工业大学 一种基于注意力机制的知识图谱路径可达性预测方法
CN118213207B (zh) * 2024-05-14 2024-08-06 深圳市金联信科技有限公司 一种电容器素子钉卷机智能控制方法及设备

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07311754A (ja) * 1994-05-19 1995-11-28 Ricoh Co Ltd 学習機械
CN102947818A (zh) * 2010-05-19 2013-02-27 加利福尼亚大学董事会 神经处理单元
CN103970512A (zh) * 2014-05-21 2014-08-06 龙芯中科技术有限公司 多核处理器及其并行重放方法
CN104145281A (zh) * 2012-02-03 2014-11-12 安秉益 神经网络计算装置和系统及其方法
CN104538028A (zh) * 2014-12-25 2015-04-22 清华大学 一种基于深度长短期记忆循环神经网络的连续语音识别方法
CN105488565A (zh) * 2015-11-17 2016-04-13 中国科学院计算技术研究所 加速深度神经网络算法的加速芯片的运算装置及方法
CN105512723A (zh) * 2016-01-20 2016-04-20 南京艾溪信息科技有限公司 一种用于稀疏连接的人工神经网络计算装置和方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6526167B1 (en) * 1998-05-26 2003-02-25 Sony Corporation Image processing apparatus and method and provision medium
US7512723B2 (en) * 2006-12-29 2009-03-31 Freescale Semiconductor, Inc. Queued interface devices, multi-core peripheral systems, and methods for sharing a peripheral in a multi-core system
US7647284B2 (en) * 2007-01-12 2010-01-12 Toyota Motor Engineering & Manufacturing North America, Inc. Fixed-weight recurrent neural network controller with fixed long-term and adaptive short-term memory
US8103803B2 (en) * 2008-11-21 2012-01-24 Nvidia Corporation Communication between a processor and a controller
US9978014B2 (en) * 2013-12-18 2018-05-22 Intel Corporation Reconfigurable processing unit
WO2015130928A1 (en) * 2014-02-26 2015-09-03 Nancy Packes, Inc. Real estate evaluating platform methods, apparatuses, and media
US20160034812A1 (en) 2014-07-31 2016-02-04 Qualcomm Incorporated Long short-term memory using a spiking neural network
US10783900B2 (en) * 2014-10-03 2020-09-22 Google Llc Convolutional, long short-term memory, fully connected deep neural networks
CN104615983B (zh) 2015-01-28 2018-07-31 中国科学院自动化研究所 基于递归神经网络和人体骨架运动序列的行为识别方法
CN105389772B (zh) 2015-12-02 2018-09-07 百度在线网络技术(北京)有限公司 基于图形处理器的数据处理方法和装置
CN111353589B (zh) * 2016-01-20 2024-03-01 中科寒武纪科技股份有限公司 用于执行人工神经网络正向运算的装置和方法
CN107315716B (zh) * 2016-04-26 2020-08-07 中科寒武纪科技股份有限公司 一种用于执行向量外积运算的装置和方法
WO2017185347A1 (zh) 2016-04-29 2017-11-02 北京中科寒武纪科技有限公司 用于执行循环神经网络和lstm运算的装置和方法
CN107341547B (zh) * 2016-04-29 2021-04-20 中科寒武纪科技股份有限公司 一种用于执行卷积神经网络训练的装置和方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07311754A (ja) * 1994-05-19 1995-11-28 Ricoh Co Ltd 学習機械
CN102947818A (zh) * 2010-05-19 2013-02-27 加利福尼亚大学董事会 神经处理单元
CN104145281A (zh) * 2012-02-03 2014-11-12 安秉益 神经网络计算装置和系统及其方法
CN103970512A (zh) * 2014-05-21 2014-08-06 龙芯中科技术有限公司 多核处理器及其并行重放方法
CN104538028A (zh) * 2014-12-25 2015-04-22 清华大学 一种基于深度长短期记忆循环神经网络的连续语音识别方法
CN105488565A (zh) * 2015-11-17 2016-04-13 中国科学院计算技术研究所 加速深度神经网络算法的加速芯片的运算装置及方法
CN105512723A (zh) * 2016-01-20 2016-04-20 南京艾溪信息科技有限公司 一种用于稀疏连接的人工神经网络计算装置和方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
CHEN, YUNJI ET AL.: "Artificial Neural Network Processor", SCIENCE CHINA: CHINESE BULLETIN OF LIFE SCIENCE = SCIENTIA SINICA VITAE, vol. 46, no. 2, 27 February 2016 (2016-02-27), pages 223 - 224, XP009512833, ISSN: 1674-7232, DOI: 10.1360/N052015-00297 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11531860B2 (en) 2016-04-29 2022-12-20 Cambricon (Xi'an) Semiconductor Co., Ltd. Apparatus and method for executing recurrent neural network and LSTM computations
US11727244B2 (en) 2016-04-29 2023-08-15 Cambricon Technologies Corporation Limited Apparatus and method for executing recurrent neural network and LSTM computations
CN108875601A (zh) * 2018-05-31 2018-11-23 郑州云海信息技术有限公司 动作识别方法和lstm神经网络训练方法和相关装置
US11042797B2 (en) 2019-01-08 2021-06-22 SimpleMachines Inc. Accelerating parallel processing of data in a recurrent neural network
WO2021212753A1 (zh) * 2020-04-23 2021-10-28 平安科技(深圳)有限公司 计算机性能数据确定方法、装置、计算机设备及存储介质

Also Published As

Publication number Publication date
US11531860B2 (en) 2022-12-20
US20190087709A1 (en) 2019-03-21
US11727244B2 (en) 2023-08-15
EP3451239A1 (en) 2019-03-06
EP3451239A4 (en) 2020-01-01
US20190087710A1 (en) 2019-03-21

Similar Documents

Publication Publication Date Title
WO2017185347A1 (zh) 用于执行循环神经网络和lstm运算的装置和方法
CN109284825B (zh) 用于执行lstm运算的装置和方法
CN111860812B (zh) 一种用于执行卷积神经网络训练的装置和方法
WO2017185387A1 (zh) 一种用于执行全连接层神经网络正向运算的装置和方法
WO2017124641A1 (zh) 用于执行人工神经网络反向训练的装置和方法
KR102470264B1 (ko) 완전연결층 신경망 역방향 트레이닝 실행용 장치와 방법
CN109117948B (zh) 画风转换方法及相关产品
CN107316078B (zh) 用于执行人工神经网络自学习运算的装置和方法
CN111353589B (zh) 用于执行人工神经网络正向运算的装置和方法
EP3451157B1 (en) Device and method for performing forward operation of convolutional neural network
CN111260025B (zh) 用于执行lstm神经网络运算的装置和运算方法
CN107886166B (zh) 一种执行人工神经网络运算的装置和方法
WO2017185248A1 (zh) 用于执行人工神经网络自学习运算的装置和方法
WO2018058452A1 (zh) 一种执行人工神经网络运算的装置和方法
WO2017185335A1 (zh) 一种用于执行batch normalization运算的装置和方法
WO2017177446A1 (zh) 支持离散数据表示的人工神经网络反向训练装置和方法
CN111860814B (zh) 一种用于执行batch normalization运算的装置和方法

Legal Events

Date Code Title Description
NENP Non-entry into the national phase

Ref country code: DE

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16899858

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2016899858

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2016899858

Country of ref document: EP

Effective date: 20181129