WO2017080340A1

WO2017080340A1 - Nanowire giant piezo-resistive property measurement device and manufacturing method therefor

Info

Publication number: WO2017080340A1
Application number: PCT/CN2016/102073
Authority: WO
Inventors: 张加宏; 赵阳; 李敏; 杨敏
Original assignee: 南京信息工程大学
Priority date: 2015-11-09
Filing date: 2016-10-14
Publication date: 2017-05-18
Also published as: CN105223421B; CN105223421A

Abstract

Provided are a nanowire giant piezo-resistive property measurement device and a manufacturing method therefor. The measurement device comprises: a nanowire (6); a platinum resistance temperature sensor (1); an electrothermal actuator (2); a capacitive measurement-based displacement sensor (3); an electrode (4); and a capacitive measurement-based load sensor (9). The platinum resistance temperature sensor (1), the electrothermal actuator (2), the displacement sensor (3), and the load sensor (9) are connected sequentially. There are four electrodes (4). The four electrodes (4) are disposed between the displacement sensor (3) and the load sensor (9). The nanowire (6) is disposed between two horizontally placed electrodes (4). The electrodes (4) are disposed at an upper side and a lower side of the nanowire (6). The measurement device and the manufacturing method therefor can realize concurrent measurement of a mechanical property and an electrical property of the nanowire (6), thereby completing characterization of a piezo-resistive coefficient. The invention is applicable to a variety of measurement samples.

Description

Nanowire giant piezoresistive characteristic measuring device and manufacturing method thereof

Technical field

The invention relates to a nanowire giant piezoresistive characteristic measuring device and a manufacturing method thereof, and belongs to the technical field of micro-nano electromechanical systems.

Background technique

As a typical one-dimensional semiconductor nanomaterial, nanowires have the characteristics of general nanomaterials, compatibility with modern large-scale integrated circuit technology, easy preparation in large quantities, and easy surface modification. Because the semiconductor properties of nanowires show unique electrical, mechanical, thermal, and chemical properties, their research and application areas cover a wide range of fields from chemical, physical, biological, environmental sensors, field effect transistors, and logic circuits. In addition, silicon nanowires also exhibit field emission, thermal conductivity, visible light luminescence and quantum confinement effects different from bulk silicon materials, and have great potential applications in nanoelectronic devices, optoelectronic devices and new energy sources. .

On the one hand, when exploring the performance and application of nanowires, the giant piezoresistive effect has become the most interesting feature due to its potential use in electromechanical sensors and strain engineering. Despite this, the preparation of nanowire giant piezoresistive structures is still difficult. The preparation methods are as follows: 1. Reducing the diameter of the nanowires by repeated thermal oxidation and etching processes to form a significant quantum confinement effect to enhance the nanometers. The piezoresistive characteristics of the wire; 2. Surface modification of the nanowire by a chemical process; 3. Preparation of a semiconductor-metal heterostructure.

On the other hand, the current characterization of nanostructured piezoresistive coefficients can be divided into two main categories: one is based on Atomic Force Microscope (AFM) or other probe technology loading methods, the main feature is the need for AFM/ Probe integrated nanomechanical sensor and nano The meter precision actuator requires nano-manipulation technology to assemble the nanostructure onto the needle tip and so on. However, such experimental test systems are very complicated and the experimental costs are also very expensive. Moreover, the size of the AFM tip structure is much larger than that of the nanostructure, and the control accuracy during mechanical loading is difficult to reach the nanometer scale. In addition, most AFM mechanical loading experiments are performed in Scanning Electron Microscopy (SEM), which affects the measurement of electrical characteristics. The other is to use the micro-electro-mechanical system micro-actuator to load the nano-structure. At present, there are mainly three kinds of MEMS driving devices: piezoelectric driving, electrostatic comb driving and thermal driving. The measurement of the resistance is measured by two points. The existence of factors such as resistance undoubtedly increases the measurement error of the piezoresistive coefficient of the nanowire.

It is worth noting that the temperature drift causes the sensitivity and stability of the semiconductor giant piezoresistive sensor to have a certain influence, and the measurement accuracy is lowered. Therefore, the semiconductor piezoresistive sensor applied to various temperature environments needs to consider the temperature drift effect. However, there are few studies on the temperature characteristics of the piezoresistive coefficient of nanowires, so relevant measurement and research methods are urgently needed.

Summary of the invention

OBJECTIVE: To overcome the deficiencies in the prior art, the present invention provides a nanowire giant piezoresistive characteristic measuring device and a manufacturing method thereof.

Technical Solution: In order to solve the above technical problems, the technical solution adopted by the present invention is:

A nanowire giant piezoresistive characteristic measuring device comprises: a nanowire, a platinum resistance temperature sensor, an electrothermal actuator, a displacement sensor based on capacitance measurement, an electrode, a load sensor based on capacitance measurement, the platinum resistance temperature sensor, and an electric heating An actuator, a displacement sensor based on capacitance measurement, and a load sensor based on capacitance measurement are sequentially connected, and the number of electrodes is set to four, the four The electrodes are disposed between the displacement sensor based on the capacitance measurement and the load sensor based on the capacitance measurement, and nanowires are disposed between the two horizontally placed electrodes, and electrodes are disposed on the lower sides of the nanowires.

Also included is a calibration probe that is coupled to a load sensor based on capacitance measurements.

The invention further comprises an electrical insulation module, characterized in that: between the electrothermal actuator and the displacement sensor based on the capacitance measurement, between the displacement sensor and the electrode based on the capacitance measurement, and between the electrode and the load sensor based on the capacitance measurement, based on the capacitance An electrical insulation module is provided between the measured load cell and the calibration probe.

The nanowires are made of externally grown silicon nanowires, and surface-modified by silver nanoparticles prepared on the nanowires to form a giant piezoresistive property.

The nanowires are chemical vapor deposition methods for synthesizing silicon germanium radial heterostructure nanowires having giant piezoresistive properties based on radial and axial growth control.

The nanowires are self-assembled by solution meteorological method to self-assemble silicon germanium longitudinal heterojunction nanowires having giant piezoresistive properties.

The nanowire adopts STM tip operation to prepare the nanowire with giant piezoresistive characteristics to position, align, and tighten the nanowires on the upper surface of the two suspension electrodes, and use the electron beam to induce deposition of the nanowires. The array is attached to the suspension electrode.

A method for manufacturing a nanowire giant piezoresistive characteristic measuring device, comprising: the following steps:

Step 1: Select 25 μm of top silicon, bury 2 μm of oxide layer, and 300 μm of SOI silicon wafer of bottom silicon. The silicon wafer is placed in a mixed solution of acetone, hydrogen peroxide and concentrated sulfuric acid for ultrasonic cleaning, and then repeatedly cleaned with deionized water. Then, the cleaned silicon wafer is placed in a diluted HF solution to remove the oxide layer on the surface of the silicon wafer;

Step 2: depositing a 1 μm SiO ₂ oxide layer on the top layer and the bottom layer of the SOI wafer by LPCVD technology;

Step Three: forming a platinum resistance region is etched by RIE technique SiO ₂ top oxide layer; etching by DRIE technique platinum resistance region;

Step 4: etching the top SiO ₂ oxide layer by RIE technique to form a boron doped resistance region; boron doping is performed in the resistance region by a diffusion process, and the resistivity of the resistive region is set to 1.7 to 1.9×10 ⁻⁵ Ω · m, forming a P-type doped silicon resistance region;

Step 5: etching the SiO ₂ oxide layer on the silicon surface by BOE using a buffer oxide;

Step 6: etching the underlying SiO ₂ oxide layer by an RIE technique to form an insulating module pattern;

Step 7: spin-coating a photoresist on the bottom layer of the SOI silicon wafer; forming a oxide layer etching mask pattern by using a mask;

Step 8: etching the underlying silicon by 100 μm by DRIE technology;

Step 9: etching the underlying SiO ₂ oxide layer not protected by the photoresist by an RIE technique;

Step 10: etching the underlying silicon not protected by the photoresist and the oxide layer by DRIE technology;

Step 11: forming a platinum resistive pattern using a positive photoresist, and using a stripping process to form a platinum unit of a temperature unit on the SiO ₂ buried layer;

Step 12: forming a pattern of electrodes and lead regions using a positive photoresist; sputtering aluminum, using a stripping process to form leads and an aluminum upper electrode;

Step 13: etching the SiO2 buried layer by RIE technology to expose the insulating module;

Step 14: stripping the residual photoresist, the underlying SiO 2 oxide layer;

Step 15: The device structure is completed by DRIE technology on the top layer silicon to form a complete structure and then annealed, and the aluminum lower electrode is formed on the measurement substrate by photolithography, etching, and stripping processes.

[Advantageous Effects] The nanowire giant piezoresistive characteristic measuring device and the manufacturing method thereof provided by the present invention use a combination of an external electric field and a chemical process surface modification to modify the surface state structure of the nanowire, or use self-grown silicon. The heterostructure is used to complete the preparation of nanowires with giant piezoresistive properties.

The nanowire giant piezoresistive characteristic measuring device is completed by using a standard CMOS process compatible MEMS technology suitable for mass production, and the MEMS measuring device can simultaneously measure the mechanical characteristics and electrical characteristics of the nanowire, thereby completing the characterization of the piezoresistive coefficient. And can be applied to a variety of different measurement samples.

The measuring device obtains the elongation and load data of the nanowire through the capacitance digital conversion chip which is externally connected to the displacement sensor and the load sensor, and thus does not depend on the scanning electron microscope imaging, thereby avoiding the measurement of the electrical characteristics by the electron beam irradiation. influences. At the same time, for the problem that the temperature of the sample to be tested affects the piezoresistive coefficient measurement, the measuring device also integrates a temperature sensor for temperature compensation of the piezoresistive coefficient, reducing the influence of the environmental system, thereby completing the high piezoresistive coefficient of various measurement samples. The purpose of precision measurement.

1. The present invention provides a method for preparing five kinds of nanowires having giant piezoresistive characteristics, and the MEMS measuring device with giant piezoresistive characteristics has the ability to apply a bias electric field, and can modulate the piezoresistive characteristics of the nanowires.

2. The invention integrates the MEMS temperature sensor with the measuring device for temperature compensation, ensures the consistency, and improves the accuracy of the giant piezoresistive coefficient.

3. The present invention combines the four-probe structure to eliminate the influence of contact resistance and thereby make the measurement result of the nanowire giant piezoresistive coefficient more accurate.

4. The present invention provides a higher sampling rate that can be captured in emergent events such as plastic deformation and corrupted data points.

5. The apparatus of the present invention can be characterized outside the vacuum chamber to make it easier to study the effects of environmental factors on the properties of the nanomaterial, such as gas, light or temperature.

6. All measurement data forces and displacements obtained by the present invention are not imaged by scanning electron microscopy, and the influence of electron beam irradiation on the measurement of electrical characteristics of the sample is avoided.

7. The measurement sample of the present invention may be a two-dimensional film, a one-dimensional nanostructure, and the nanostructure may be a single semiconductor nanowire structure, which may be a heterojunction nanowire or a nanowire array.

DRAWINGS

1 is a schematic structural view of a nanowire giant piezoresistive characteristic measuring device;

2 is a working flow chart of a nanowire giant piezoresistive characteristic measuring device;

3 is a flow chart of a preparation process of a nanowire giant piezoresistive characteristic measuring device;

4 is a schematic view showing the preparation of a silicon germanium radial heterojunction nanowire;

5 is a schematic view showing growth of a silicon germanium longitudinal heterojunction nanowire;

Figure 6 is a schematic view showing the operation of the STM probe to fix the nanowires on the electrodes;

7 is a schematic view of nanowires self-growth on an electrode;

8 is a flow chart of a MEMS process prepared by an integrated measurement structure of an electron beam lithography nanowire;

9 is a schematic structural view of four electrodes of a nanowire;

Figure 10 is a mechanical model of a mechanical characterization device for a nanowire sample;

Figure 11 is a flow chart of temperature compensation for wavelet neural network based on improved genetic algorithm.

detailed description

The present invention will be further described below in conjunction with the accompanying drawings.

As shown in FIG. 1 , a nanowire giant piezoresistive characteristic measuring device is a platinum resistance temperature sensor 1 for temperature compensation from left to right, and an electrothermal actuator 2 for driving a displacement sensor and a nanowire. And load sensor movement; displacement sensor 3 based on capacitance measurement for measuring the displacement of the thermal actuator while achieving the drive voltage decoupling function of the thermal actuator; four electrodes 4 for four-probe measurement; Nanowire 6 with giant piezoresistive characteristics; load sensor 9 based on capacitance measurement for measuring the displacement and tension of itself; calibration probe 10 for calibrating the force sensor. All of the above units are stabilized in the same plane by a set of beams anchored to the top silicon to ensure uniform distribution of the entire nanowire specimen.

The electrothermal actuator 2 and the displacement sensor 3, the displacement sensor 3 and the electrode 4, the electrode 4 and the load sensor 9, the load sensor 9 and the calibration probe 10 are respectively mechanically connected through the electrically insulating modules 11 of the four SOI buried layers, Independent electrical measurements are provided for nanowire samples; also used for mechanical connection of load sensor 9 to calibration probe 10 for efficient measurement. The two suspension electrodes 4 are mechanically connected to the nanowires 6.

As shown in FIG. 2, a measuring step of a nanowire giant piezoresistive characteristic measuring device: in the first step, the displacement sensor and the load sensor are calibrated under a microscope; and in the second step, the electrothermal actuator is driven as a driving device through an insulation module. The displacement sensor moves to the left, and the nanowire is moved to the left by the insulation module, and the nanowire is also moved to the left by the insulation module; the third step is the capacitance digital conversion by the load sensor and the displacement sensor based on the capacitance measurement The chip obtains the load and elongation data of the nanowire, and at the same time, the piezoresistive change is obtained by the measurement of the four probes; in the fourth step, the piezoresistive effect is characterized by the strain coefficient.

As shown in FIG. 3, a method for preparing a nanowire giant piezoresistive characteristic measuring device, the specific steps of the method:

1) Select 25μm of top silicon, bury 2μm of oxide layer, 300μm of SOI silicon wafer of bottom silicon, place the silicon wafer in ultrasonic solution of acetone, hydrogen peroxide and concentrated sulfuric acid, then wash it again with deionized water; then The cleaned silicon wafer is placed in a diluted HF solution to remove the oxide layer on the surface of the silicon wafer;

2) depositing a 1 μm SiO ₂ oxide layer on the top and bottom silicon of the SOI wafer by LPCVD technique;

3) etching a top SiO ₂ oxide layer by a RIE (Reactive Ion Etching) technique to form a platinum resistance region; etching the platinum resistance region by a DRIE (Deep Reactive Ion Etching) technique;

4) etching the top SiO ₂ oxide layer by RIE technique to form a boron doped resistance region; boron doping (resistivity: 1.7 to 1.9×10 ^-5 Ω·m) in the resistance region by a diffusion process to form a P-type Doped silicon resistance region;

5) using the SiO ₂ oxide layer is buffered oxide etch (BOE) peeling off the silicon surface;

6) etching the underlying SiO ₂ oxide layer by RIE technique to form an insulating module pattern;

7) spin-coating a photoresist on the bottom layer of the SOI wafer; forming a oxide layer etching mask pattern by using a mask;

8) etching the underlying silicon by 100 μm by DRIE technique;

9) etching the underlying SiO ₂ oxide layer not protected by the photoresist by an RIE technique;

10) etching the underlying silicon that is not protected by the photoresist and the oxide layer by DRIE technology;

11) forming a platinum resistance pattern using a positive photoresist, and using a stripping process to form a platinum unit of a temperature unit on the SiO ₂ buried layer;

12) forming a pattern of electrodes and lead regions using a positive photoresist; sputtering aluminum, forming a lead and an aluminum upper electrode by a lift-off process;

13) etching the SiO ₂ buried layer by RIE technology to expose the insulating module;

14) stripping the residual photoresist, the underlying SiO ₂ oxide layer;

15) The device structure is completed by DRIE technology on the top layer silicon to form a complete structure and then annealed, and the aluminum lower electrode is formed on the measurement substrate by photolithography, etching and stripping processes.

It is worth noting that the addition of a bias voltage between the suspension electrode of the MEMS measuring device and the substrate can deplete the pinch-off portion of the conductive channel forming portion in the nanowire to facilitate the nano-scale giant piezoresistive property.

Secondly, the calibration of the load sensor and the displacement sensor is completed. The data sampling rate for device calibration is 45 Hz. After the electric brake is powered on, the displacement sensor and the electrothermal actuator are moved to the left, and the displacement of the displacement sensor in the microscopic imaging and the displacement of the capacitance digital conversion chip circuit corresponding to the displacement are read out. The voltage is output, and the relationship between the displacement sensors and the corresponding voltage outputs is obtained. The probe device is used to push the calibration probe to move, and the displacement of the load sensor in the microscopic imaging and the output voltage of the capacitance digital conversion chip circuit corresponding to the displacement are read out, and the relationship between the load sensor and the corresponding voltage output is obtained. At the same time, the load cell is calibrated using a precision microbalance to obtain the relationship between displacement and load.

The invention provides five nanowire setting methods with giant piezoresistive characteristics, as follows:

Example 1: Silicon nanowires with silver

The experimental procedure for the preparation of Si nanowires is as follows: firstly, the Si wafer is cleaned with a 2% HF solution (HF: H ₂ O = 1:50) for 3 minutes to remove the natural oxide layer on the surface of the Si wafer; It is ultrasonically cleaned in a mixed solution of acetone, hydrogen peroxide and concentrated sulfuric acid, and then repeatedly cleaned with deionized water; then, a high-purity Au is evaporated by a vacuum evaporation coating machine to deposit a certain thickness of the metal catalyst on the surface of the Si substrate; The sample in which the metal catalyst was deposited was placed in a quartz tube of an automatic temperature control tube oxidizing furnace, and subjected to high temperature annealing to grow Si nanowires under a protective atmosphere at a temperature of 800-1100 ° C and a certain flow rate. The oxide film on the nanowire is treated with hydrofluoric acid, the surface of the nanowire of silicon is passivated by hydrogen, and the silicon nanoparticle whose surface is passivated by hydrogen is put into the silver nitrate solution, and the nanometer of silver is prepared on the silicon nanowire. particle.

Example 2: Silicon germanium radial heterojunction nanowires

Gold nanoclusters are deposited on oxidized silicon wafers and placed in a quartz tube furnace. At 450 ° C, silane was used as the lead gas, so that the silicon nanowire core was grown at an axial growth rate of about 2 μm/min, and then p-type silicon shell was deposited using silane and 100 ppm helium diborane as a lead gas. And at a radial growth rate of 10 nm/min. Then at 380 ° C, 锗 nanowire 10% The relevant argon gas was grown at an axial growth rate of 0.72 um/min, and the crucible was deposited in the furnace at a radial velocity of 10 nm/min by changing the positional environment of the growth substrate. Nanowires of various core-shell structures, such as Si/Ge, Ge/Si, or Si/Ge/Si, Ge/Si/Ge, etc., can be completed by repeating the above process. The process flow chart is shown in Figure 4.

Example 3: Silicon germanium longitudinal heterojunction nanowires

In the first step, a clean silicon wafer washed with an organic solvent is placed in a vacuum sputtering coating machine, and a layer of about 10 nm of tin is sputtered on the surface of the silicon wafer, heated to 600 ° C, and tin is agglomerated into nanoparticles; At 450-470 ° C, silane gas is obtained by thermal decomposition of stupid silane, and then silane gas is used as a lead gas to grow silicon nano-fragments on the surface of the tin nano-particle catalyst layer, and the reaction is completed and then (Ar + 5% H ₂ ) gas is introduced. The residual precursor gas is removed; in the third step, the triphenyl decane liquid is thermally decomposed at 420-440 ° C to obtain a decane gas, which is then used as a lead gas for growing the yttrium nano-segment on the silicon nano-fragment. The ruthenium nano-fragment was grown, and after completion of the reaction, an (Ar + 5% H ₂ ) gas was introduced to remove residual residual precursor gases. The silicon germanium heterojunction nanowires of the abrupt interface are formed by repeating the above two steps repeatedly, and the structure is until a suitable length of silicon germanium heterojunction nanowires (Si/Ge/Si/Ge) is grown. The process flow chart is shown in Figure 5.

For the above three implementation cases, the STM (sweep-to-tunnel microscope) tip operation was used to position, align, and tighten the nanowires on the upper surfaces of the two suspension electrodes, and the electron beam induced deposition. The nanowire array is fixed to the suspension electrode, and the effect is shown in Fig. 6.

Example 4: Self-grown surface-modified silicon nanowires

A thin oxide layer of 30-60 nm is formed on the model, and then lithographically positioned to remove oxidation of the sidewall of the trench The layer forms a window for growing silicon nanowires. Photolithography is used to assist in locating the growth region, and a high-density tin-nanoparticle catalyst is obtained in the growth region by electrodeposition, and the substrate is immersed in a microemulsion containing a tin salt solution, a hydrofluoric acid solution, and a surfactant during deposition. Particles having a radius of 10-20 nm. The silane (PS) is thermally decomposed at 450-470 ° C to obtain silane gas; then the silane gas is used as a lead gas to grow silicon nanowires on the surface of the tin nanoparticle catalyst layer, so that the suspended electrodes are connected through the nanowire array, and the nano The surface is subjected to surface modification treatment of Ba, Hf, and Zr doping to increase the surface state density and increase the surface effect and piezoresistive characteristics, as shown in FIG.

Example 5: Surface Modified Silicon Nanowires Based on MEMS Process

The calibration of the load cell and the displacement sensor was completed for the above structure, and the electron beam lithography nanowire was used to complete the preparation of the silicon nanowire giant piezoresistive characteristic measuring device, as shown in FIG. Specific steps are as follows:

2) 1um oxide layer of SiO ₂ is deposited on the top and bottom silicon SOI wafer by LPCVD technique;

5) stripping the SiO ₂ oxide layer on the silicon surface by buffer oxide etching (BOE);

8) etching the underlying silicon by 100 μm by DRIE technique;

11) is etched by RIE techniques the buried SiO ₂ layer to expose the insulation module, the peeling residual photoresist, the underlying oxide layer SiO _2;

12) forming a platinum resistance pattern using a positive photoresist, and using a stripping process to form a platinum unit of a temperature unit on the SiO ₂ buried layer;

13) depositing a layer of 1 μm silicon nitride on the top layer of the SOI silicon wafer by LPCVD method, and etching the nanowire region by RIE;

14) oxidize the upper layer of silicon in a 1100 degree pure oxygen environment, etch the silicon dioxide with a BOE solution, and then oxidize the same environment multiple times to etch the silicon dioxide until the nanowire thickness reaches 100 nm; doping the nanowire region with Hf , Ba or Zr;

15) The oxide film on the nanowire is treated with hydrofluoric acid, the surface of the nanowire of silicon is passivated by hydrogen, and the silicon nanoparticle whose surface is passivated by hydrogen is put into a silver nitrate solution, and silver is prepared on the silicon nanowire. Nanoparticles; RIE is used to etch away residual silicon nitride;

16) forming a pattern of electrodes and lead regions using a positive photoresist; sputtering aluminum, forming a lead and an aluminum electrode by a lift-off process;

17) The first step is to spin-coat the SOI wafer on the negative photoresist, and then soft-bake after coating the glue; the second step is to scan the surface of the photoresist to obtain the required nano-line pattern and device of various sizes. The third step is to develop the exposed pattern, and then remove the exposed portion to complete the device structure by the DRIE technique on the top silicon; finally, remove the unexposed portion of the photoresist. A lower electrode is formed on the measurement structure substrate by a photolithography, etching, and lift-off process.

Then, the initial resistance of the nanowire is obtained. 9, the horizontal direction is provided by two electrodes nanowires constant current source I, two vertical electrodes provide a voltage V ₀ nanowires, the nanowires to give the initial resistance

D1 The distance between the nanowires between the two electrodes in the vertical direction, and the distance between the nanowires between the two electrodes in the horizontal direction of d0; as previously emphasized, a bias voltage is applied between the suspension electrode of the nanowire and the substrate, and the depletion is performed. The pinch-off of the nanowire conductive channel forming portion can facilitate the full realization of the nanowire giant piezoresistive property.

Along with this, a voltage is supplied to the electrothermal actuator to operate the entire device. The electrothermal actuator acts as a driving device to push the displacement capacitance sensor to move to the left through the insulation module, and simultaneously pulls the nanowire to the left through the insulation module, and the nanowire moves the load sensor to the left through the insulation module. The nanowire tensile length d _s is nanometer as the displacement d _a of the displacement sensor minus the displacement d _{f of the} load cell, and the nanowire strain ε=d _s /d _{0 is obtained} . After the length of the nanowire is d _s , the voltage of the two electrodes in the vertical direction becomes V ₁ , and the resistance R ₁ after the change of the nanowire is

ΔR = R _{1 -} R ₀ . Piezoresistive coefficient

Characterize the piezoresistive effect.

As shown in Figure 10, since the sample of the nanowire becomes part of the mechanical system during the testing of the device, k _s d _s = k _f d _f; F _a = k _a d _a + k _s d _s , where k _s , k _a , k _f are the stiffness of the nanowire, load cell, and electrothermal actuator; d _s , d _a , d _f are the displacement of the nanowire, load cell, and electrothermal actuator, respectively; and the force F generated by the electrothermal actuator _a = _{2NEAαΔTsinθ,} where α is the thermal expansion coefficient of silicon, ΔT is the average temperature of the V-shaped beam, N being the number of V-shaped beam, a is the cross sectional area of the V-beam. The stiffness k _{s of the} nanowire can be obtained by the ratio of load sensor load to displacement corresponding to the output voltage. The nanowire stiffness k _s =F/d _s , the nanowire stress δ=F/S, F is the load sensor load, and S is the cross-sectional area of the nanowire. Thus, the nanowire Young's modulus E = δ / ε is obtained.

Through the above steps, the mechanical properties and electrical properties of the nanowires were measured, and the giant piezoresistive effect of the nanowires was characterized. During the measurement process, the temperature and resistivity of the sample to be tested have a direct relationship, which affects the measurement of the piezoresistive coefficient. Therefore, the temperature of the sample to be tested must be grasped before the measurement. If the temperature of the sample is not suitable for the measurement. , will affect the final piezoresistive coefficient, it must be modified based on the improved genetic algorithm wavelet neural network model, the specific process shown in Figure 11:

Step 1: Population initialization: randomly initialize the population, encode the link weight between the input layer and the hidden layer of the wavelet neural network, the link weight of the hidden layer to the output layer, the scaled silver and the translation factor, and generate an initial population of a certain scale. .

Step 2: According to the link weight, expansion and translation factor of the wavelet neural network obtained by the individual. The measured piezoresistive coefficient and temperature data are input as training data, and the error between the predicted output and the target value of the system is obtained as the fitness value F after training the wavelet neural network.

Step 3: Perform selection, crossover and mutation operations.

Step 4: Determine whether the evolution is over. Here are two end conditions: whether the fitness value satisfies the relationship, and the genetic algorithm reaches the set number of iterations. After satisfying these two conditions, the weight, scaling and translation factors of the search can be used. Wavelet neural network calculation.

The invention realizes the measurement of mechanical characteristics and electrical characteristics of various measurement samples through the nanowire giant piezoresistive characteristic measuring device and the MEMS measuring method thereof, and characterizes the piezoresistive coefficient. It can be extended to other types of nanowires, such as the measurement of mechanical, electrical and piezoresistive properties of metal-silicon heterojunction nanowires.

The above description is only a preferred embodiment of the present invention, and it should be noted that those skilled in the art can also make several improvements and retouchings without departing from the principles of the present invention. It should be considered as the scope of protection of the present invention.

Claims

A nanowire giant piezoresistive characteristic measuring device, comprising: a nanowire, a platinum resistance temperature sensor, an electrothermal actuator, a displacement sensor based on capacitance measurement, an electrode, a load sensor based on capacitance measurement, the platinum resistance A temperature sensor, an electrothermal actuator, a displacement sensor based on capacitance measurement, a load sensor based on capacitance measurement are sequentially connected, the number of electrodes is set to four, and the four electrodes are disposed on a displacement sensor based on capacitance measurement and based on capacitance measurement Between the load sensors, nanowires are disposed between the two horizontally placed electrodes, and electrodes are disposed on both sides of the nanowires.
The nanowire giant piezoresistive characteristic measuring apparatus according to claim 1, further comprising a calibration probe connected to the load sensor based on the capacitance measurement.
The nanowire giant piezoresistive characteristic measuring device and the method of manufacturing the same according to claim 2, further comprising an electrical insulation module, wherein the electrothermal actuator and the displacement sensor based on capacitance measurement are based on capacitance measurement An electrical insulation module is disposed between the displacement sensor and the electrode, between the electrode and the load sensor based on the capacitance measurement, and between the load sensor based on the capacitance measurement and the calibration probe.
The method for disposing nanowires in a nanowire giant piezoresistive characteristic measuring device according to claim 1, wherein the nanowires are grown by using externally grown silicon nanowires by preparing silver nanoparticles on the nanowires. The surface modification forms a giant piezoresistive property.
The method for setting nanowires in a nanowire giant piezoresistive characteristic measuring device according to claim 1, wherein the nanowires are chemical vapor deposition, and the composite pressure based on radial and axial growth has a giant piezoresistive resistance. Characteristics of silicon germanium radial heterostructure nanowires.
The method for setting a nanowire in a nanowire giant piezoresistive characteristic measuring device according to claim The method is characterized in that: the nanowire adopts a solution meteorological method to self-assemble and assemble a silicon germanium longitudinal heterojunction nanowire having a giant piezoresistive property.
The method for setting nanowires in a nanowire giant piezoresistive characteristic measuring device according to claim 1, wherein the nanowires are operated by an STM tip to prepare the nanowires having giant piezoresistive characteristics in two suspensions. The corresponding positions on the upper surface of the electrode are used for positioning, aligning, and tightening the nanowires, and the nanowire array is fixed on the suspension electrode by electron beam induced deposition.
A method for manufacturing a nanowire giant piezoresistive characteristic measuring device, comprising: the following steps:

Step 1: Select 25 μm of top silicon, bury 2 μm of oxide layer, and 300 μm of SOI silicon wafer of bottom silicon. The silicon wafer is placed in a mixed solution of acetone, hydrogen peroxide and concentrated sulfuric acid for ultrasonic cleaning, and then repeatedly cleaned with deionized water. Then, the cleaned silicon wafer is placed in a diluted HF solution to remove the oxide layer on the surface of the silicon wafer;

Step two: 1μm oxide layer of SiO 2 is deposited on the top and bottom silicon SOI wafer by LPCVD technique;

Step 3: etching a top SiO 2 oxide layer by a RIE technique to form a platinum resistance region; etching the platinum resistance region by a DRIE technique;

Step 4: etching the top SiO 2 oxide layer by RIE technique to form a boron doped resistance region; boron doping is performed in the resistance region by a diffusion process, and the resistivity of the resistive region is set to 1.7 to 1.9×10 −5 Ω · m, forming a P-type doped silicon resistance region;

Step 5: etching the SiO 2 oxide layer on the silicon surface by BOE using a buffer oxide;

Step 6: etching the underlying SiO 2 oxide layer by an RIE technique to form an insulating module pattern;

Step 7: spin-coating a photoresist on the bottom layer of the SOI silicon wafer; forming a oxide layer etching mask pattern by using a mask;

Step 8: etching the underlying silicon by 100 μm by DRIE technology;

Step 9: etching the underlying SiO 2 oxide layer not protected by the photoresist by an RIE technique;

Step 10: etching the underlying silicon not protected by the photoresist and the oxide layer by DRIE technology;

Step 11: forming a platinum resistive pattern using a positive photoresist, and using a stripping process to form a platinum unit of a temperature unit on the SiO 2 buried layer;

Step 12: forming a pattern of electrodes and lead regions using a positive photoresist; sputtering aluminum, using a stripping process to form leads and an aluminum upper electrode;

Step 13: etching the SiO2 buried layer by RIE technology to expose the insulating module;

Step 14: stripping the residual photoresist, the underlying SiO 2 oxide layer;

Step 15: The device structure is completed by DRIE technology on the top layer silicon to form a complete structure and then annealed, and the aluminum lower electrode is formed on the measurement substrate by photolithography, etching, and stripping processes.