WO2009040691A2

WO2009040691A2 - Electronic power switching device

Info

Publication number: WO2009040691A2
Application number: PCT/IB2008/053447
Authority: WO
Inventors: Toni Lopez; Reinhold Elferich
Original assignee: Nxp B.V.
Priority date: 2007-09-25
Filing date: 2008-08-27
Publication date: 2009-04-02
Also published as: WO2009040691A3

Abstract

The invention relates to an electronic power switching device including at least one control field effect transistor (control FET) characterised in that a switching node resonant oscillation between a half-bridge path parasitic inductances and an output capacitance of a further FET is exploited during the control FET turn-off.

Description

ELECTRONIC POWER SWITCHING DEVICE

FIELD OF THE INVENTION

The invention relates to an electronic power switching device including at least one control field effect transistor.

BACKGROUND OF THE INVENTION

High frequency power conversion is per se the most enticing solution to the demands for increasing high feedback control dynamics and reducing PCB space in low- voltage high-current applications, such as voltage regulator modules (VRM) or point of load (PoL). High switching frequency operation is however detrimental for the converter efficiency, which requires to be kept high especially in these applications. High efficiency is therefore a major obstacle for increasing the switching frequency operation. This in turn tremendously influences the design guidelines of the converter and particularly the switch devices, which have to feature both low conduction resistance and high switching performance.

The most common converter topology in voltage regulator modules and point of load applications is the synchronous buck converter. In this converter, several power loss mechanisms related to the power switches are identified and classified. Great effort has been put to mitigate power losses related to reverse recovery and gate bounce. Solutions to avoid such loss mechanisms enable the operation at higher switching frequency. However, even though reverse recovery and gate bounce related losses can be neglected, other switching loss mechanisms become predominant when increasing further the switching frequency operation.

These are loss mechanisms related to the gate drives and the turn-off of the Control FET

(Ctrl. FET). The latter appears to be of particular relevance in case of integrated solutions for high current applications. Typically more than 60% of the overall losses in the Control FET may occur at turn-off because of hard switching and avalanche breakdown.

US 6,356,059 Bl discloses a buck converter with normally off JFET.

US 6,166,528 discloses a method of lossless current sensing in buck converters. US 2005/0156579 Al discloses a multiphase converter with zero voltage switching.

OBJECT AND SUMMARY OF THE INVENTION

It is an object of the invention to mitigate the above mentioned Control FET turn off losses caused by turn-off hard switching and avalanche breakdown since they are main artefacts limiting the performance of the converter at high current, high switching frequency operation.

The above mentioned problems will be solved by an electronic power switching device and control scheme characterized in that the ringing caused by a switching action is exploited in the next commutation of the switching device.

According to the invention it is of advantage that an electronic power switching device includes at least one control field effect transistor (control FET) wherein a switching node resonant oscillation between a half-bridge path parasitic inductances and an output capacitance of a further FET is exploited during the control FET turn-off or turn-on.

Furthermore it is of advantage that the switching node oscillation is synchronised with the control FET turn-off or turn-on time. This allows a very fast and effective result. Accordingly it is additionally of advantage that the turn-off occurs at the valley of the resonant half-bridge current.

According to one embodiment of the invention a valley switching control block is integrated in a MOSFET driver. This allows a very easy setup to realise the inventive idea.

Additionally it is favourable if a valley switching control block is interconnected between a PWM generator and a driver control block.

Additionally it is of advantage that at least one positive ramp detector is provided to sense the charging phase of the output capacitance of the power switch.

Furthermore it is of advantage that a voltage controlled oscillator is employed to independently adjust the switching frequency of the power switch.

Further advantages are described according to the features of the dependent claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the invention will be apparent from the following description of an exemplary embodiment of the invention with reference to the accompanying drawings, in which:

Fig. Ia shows a block diagram of an electronic circuit;

Fig. Ib shows a block diagram of an electronic circuit;

Fig. 2 shows a diagram;

Fig. 3 shows a table;

Fig. 4 shows a diagram;

Fig. 5a shows a diagram;

Fig. 5b shows a diagram;

Fig. 6 shows a diagram;

Fig. 7 shows a diagram;

Fig. 8a shows a diagram;

Fig. 8b shows a diagram;

Fig. 9 shows three diagrams; Fig. 10 shows a block diagram of an electronic circuit;

Fig. 11 shows a diagram;

Fig. 12 shows a block diagram of an electronic circuit;

Fig. 13 shows a block diagram of an electronic circuit;

Fig. 14 shows a diagram;

Fig. 15 shows a block diagram of an electronic circuit;

Fig. 16 shows a block diagram of an electronic circuit;

Fig. 17 shows a diagram;

Fig. 18 shows a block diagram of an electronic circuit;

Fig. 19 shows a block diagram of an electronic circuit; and

Fig. 20 shows a block diagram of an electronic circuit.

DESCRIPTION OF EMBODIMENTS

Generally, a synchronous buck converter consists of input/output low-pass filters and a half-bridge with associated drivers and control circuitry. Fig. Ia shows the proposed simplified representation of the switched circuit 1. Input and output filter capacitors 2,3 are modelled just as ideal voltage sources. Therefore, all ac harmonics from the switching waveforms are assumed to be perfectly filtered out. Inductance ESLi, 4 is the only considered parasitic element of the input filter. It represents the equivalent series inductance of the input capacitance 2 and PCB tracks, which may significantly contribute to the switching behaviour of the MOSFET power switches 6,7. The output coil 5 is simply modelled with inductance Lo, which allows to cope with the output ripple current waveform. The output coil 5 current considerably influences both the switching and the conduction power losses in the switches. The power MOSFET switches 6,7 are accurately represented by means of a behavioural model for circuit simulators. As shown in Fig. Ib, the static behaviour of the semiconductor switch is electrically represented in combination with a network of parasitic impedances, which condition the switching dynamic operation. Resistances Rd and Rs model the substrate and package resistances. Inter-electrode capacitances Cgs, Cgd and Cds are voltage dependent and behave non-linearly. The required data of the model's parameters are extracted from finite element simulations of the particular device structure, or alternatively from measurements.

Fig. 2 shows simulated switching waveforms of the synchronous buck converter of Fig. 1. Circuit parameters correspond to values of the table of Fig. 3. Switching frequency Fs= 4.3MHz. Note that energy loss curves include driving losses.

Fig. 2 shows typical steady state switching waveforms of the output current io, switch node voltage and energy loss pattern of the power MOSFETs 6,7 resulting from

SPICE simulations of the circuit of Fig. 1. Table I of Fig. 3 lists the values used in the example, which are typical for a point-of-load integrated solution. Fig. 2 shows a transition at the falling edge, the so called falling edge transition 10.

The switching waveforms of Fig. 4 correspond to a more detailed description of the leading edge transition from the simulation of Fig. 2. In the example, the Ctrl. FET 6 suffers a sudden power loss in the defined voltage hard- switching time interval (VHS). This interval corresponds to the Miller plateau interval of the Ctrl. FET. At the falling edge transition, VHS starts when the Ctrl. FET 6 enters into the active region, i.e. when the drain voltage starts rising, whereas it ends as soon as the body diode of the Sync. FET 7 is forward biased or the Ctrl. FET 6 channel stops conducting.

During the falling edge VHS the output capacitance of the Ctrl. FET 6 charges up towards the input voltage, and so the drain current splits between the channel and output capacitance paths. Such current share usually corresponds to that of the output current io. Therefore the capacitance performs the common function of a turn-off snubber. Generally, the quicker the Ctrl. FET 6 is turned off, the higher the current through the output capacitance is, and thus the lower the channel loss gets. There exists a third current path of great importance during the falling edge VHS, which is the output capacitance of the sync. FET 7. The stored charge in this capacitance is delivered to the load during the falling edge interval. This process equals to that of a snubber capacitance, and thus helps the Ctrl. FET turn-off if it occurs during the VHS. In applications of large conversion ratios (i.e. low duty cycles), the output charge of the Sync. FET is large and thus can be greatly exploited as a turn-off snubber.

In cases like that shown in Fig. 4 though, the output capacitance of the Sync. FET might not help but worsen the turn-off. Namely, the Ctrl. FET is turned off when the switch node ringing generated at the leading edge transition is not yet vanished (see Fig. 2). When the VHS starts, the output capacitance of the Sync. FET is in the charging phase of the resonant oscillation, which adds up to the output current in the Ctrl. FET drain path. This is of course detrimental for the turn-off since the Ctrl. FET must undergo the hard-commutation of both the output load current and the capacitance current of the Sync. FET. Any attempt in switching the Ctrl. FET quicker causes the drain current to flow through the output capacitance and thus hard-switching is reduced. Yet, the existence of parasitic inductances in the half-bridge path forces the high current to keep flowing through the output capacitance of the Ctrl. FET (instead of the Sync. FET output capacitance), which eventually avalanches. Consequently, switching the Ctrl. FET faster might translate into an overall increase of the total power loss.

On the contrary, a more favourable situation occurs if, at the beginning of the VHS interval, the output capacitance of the Sync. FET is at the discharging phase of the resonant oscillation. It is then when the drain current through the Ctrl. FET is lower than the output current since the Sync. FET is taken over part of that current.

The invention proposes a method to reduce or eliminate the losses in the VHS by means of exploiting the switch node ringing existing during the Ctrl. FET turn-off. Reducing the Ctrl. FET Losses in the VHS is crucial for improving the overall efficiency and thus enabling higher switching frequency operation, particularly in high current applications.

In the given example, the Ctrl. FET loss corresponds to more than 77% of the total losses in the device, and about 50% the overall losses in the converter. According to the invention a reduction of power losses by more than 50% are achievable, which enables the possibility of multiplying by 4 the switching frequency operation of today's power integrated solutions.

The invention proposes a method to reduce or eliminate the power losses occurring in the VHS, i.e. hard switching and avalanche breakdown, by means of exploiting the switch node ringing.

This ringing is a resonant oscillation between the half-bridge path parasitic inductances and the output capacitance of the Sync. FET. Its excitation occurs at the leading edge transition, when the Ctrl. FET is turned on.

Upon certain circumstances the switch node ringing is maintained until the next switching event occurs, i.e. the falling edge transition. Properly arranged, this oscillation can be beneficial for minimising the Ctrl. FET turn-off losses, to such an extent that the device may even switch off under zero current conditions.

According to the invention it is of advantage to synchronise the switch node oscillation with the Ctrl. FET turn-off time, in such a way that the drain current through the Ctrl. FET is minimized during the VHS interval. In other words, the Ctrl. FET is turned off upon minimum current condition, thereby minimising its turn-off related losses. It is possible to observe that such condition is met when at the beginning of the VHS interval the output capacitance of the Sync. FET is at approximately the middle of its discharging phase of the resonant oscillation, that is, at the valley of the resonant current through the Ctrl. FET.

According to one embodiment of the invention the advantage is high when the half-bridge oscillating current is sufficiently large so that the Ctrl. FET drain current can reach zero at the falling edge VHS interval.

In order to achieve the previous condition, one may search for those circuit conditions that produce high current ringing, even though it may worsen the on conduction related losses due to an increase of the Root Mean Square (RMS) current. With regard to the above, circuit conditions to maximise the half-bridge oscillating current with minimum damping are a fast Ctrl. FET turn-on at the leading edge transition in order to excite the switch node oscillation and to achieve a low damping oscillation it is helpful to have a low half-bridge resistance. This includes the ESR of the input filter and the on resistance of the Ctrl. FET. Furthermore a low coupling to the gate drive circuits is of advantage. That is, low source inductance Ls and low capacitance Cgd. Additionally low Ctrl. FET turn-on related losses are of advantage. That is, low reverse recovery, gate bouncing, Sync. FET avalanche breakdown and hard switching. Furthermore a low half-bridge parasitic inductance, including the ESL of the input filter is of advantage.

Furthermore, it is desirable to have a low output coil current ripple to reduce the superimposed dc current of the resonant oscillation at the falling edge transition.

The invention is particularly relevant at high switching frequency operation and/or short Ctrl. FET on times, e.g. high conversion ratios, because of the importance of the switching losses. Moreover, upon such conditions, the damping requirements are less stringent due to the short Ctrl. FET on time, i.e. the sustained oscillation time.

Additionally the output capacitance of the Sync. FET may be alternatively in- creased. This improves the overall efficiency by adding this capacitance in case of predominant Ctrl. FET turn-off related losses. The increase of this output capacitance effectively amplifies the oscillating current.

The effect of the switch node ringing can be beneficial or detrimental for the converter efficiency depending on the turn-off time. One idea of the invention contains synchronising the Ctrl. FET turn-off time with the switch node ringing so that turn-off power losses are minimised. Therefore the control strategy is important to ensure at almost all times the system does not suffer much but benefits from the switch node ringing. Thus it is of advantage to keep the Ctrl. FET on time to profit from valley switching above 3/4 the period of the switch node resonant oscillation.

The fact that the Ctrl. FET turn-off favourably should occur at the valley of the resonant half-bridge current means that the Ctrl. FET on time cannot take any value. Instead, only a limited number of discrete times proportional to the resonant frequency of the switch node ringing are allowed. Consequently, measures should be applied to allow an effective regulation of any possible target output voltage value.

Fig. 5a shows the impact of varying the Ctrl. FET turn-on time ΔtoN on the converter power losses. Note that, in order to keep the output voltage constant, the switching frequency is corrected for each variation of ΔtoN, as shown in the right curve of Fig. 5b. Figure 5a shows power losses as a function of the increment of the Ctrl. FET turn-on time, ΔtoN- The Output voltage is kept constant. Fig. 5b shows the required switching frequency to keep the output voltage constant. Parameters of the simulations correspond to values of Table I of Fig. 3.

The power loss at Δt_ON=0 corresponds to the case of Fig. 2 and 4. In this case, about 80% of the total power loss in the Ctrl. FET including the losses in its driver is related to hard-switching and avalanche breakdown at turn-off. On the other hand, for the optimum case of ΔtoN=7ns, losses due to hard-switching and avalanche breakdown at turn-off can be neglected. Clearly, the strong overall power loss dependency on ΔtoN is mainly attributed to the Ctrl. FET turn-off losses.

Fig. 6 shows the simulated waveforms for an embodiment of ΔtoN=7ns. Unlike the case of ΔtoN=0ns, the Sync. FET losses are predominant since the switching losses of the

Ctrl. FET have been reduced. The resulting power loss profile at ΔtoN=7ns points the Sync.

FET gate driving to be the main loss mechanism remaining in the switched circuit (about

45% of the total power loss).

Fig. 7 gives insight into the Ctrl. FET turn-off behaviour at ΔtoN = 7ns. The turn-off timing is such that at the beginning of the VHS interval the channel current is at the valley of the half-bridge resonant oscillation. As shown, it corresponds to the discharging phase of the Sync. FET output capacitance, whose stored charge is being delivered to the output. Thus, the Ctrl. FET gets into the VHS interval when the output capacitance is carry- ing most of the output current, which implies lower hard-switching losses and voltage stress in the Ctrl. FET. From Fig. 5a one can deduce that the valleys of the resonant current are found at approximately ΔtoN = ± 7ns. The selection of one or the other influences the switching frequency and therefore the efficiency.

Fig. 8a shows the efficiency comparison between different operating scenarios. Note that the parameters of the circuit correspond to the values of Table I of Fig. 3. In one scenario, the converter is operated at the fixed switching frequency of IMHz without any turn-off valley switching control. The resulting efficiency curve is then compared to different cases of operation at higher switching frequencies. Considering the worst-case Ctrl. FET turn-off scenario, the mere increase of switching frequency from IMHz to a maximum of 4.5MHz produces a large drop in the efficiency curve.

The proposed solution of controlling the Ctrl. FET turn-off time produces though substantial improvement, approaching the efficiency curve of IMHz at full load, i.e. same losses at significantly higher switching frequency operation. As indicated previously the fact of turning off at an early valley, e.g. valley n-1, cause an efficiency drop, as the Fs is higher than in case of switching at a later valley, e.g. valley n. In the given example, the difference in switching frequency between two consecutive valleys is about 1.3MHz, as shown in Fig. 8b.

The efficiency curves reveal the benefit of the invention at high frequency, high current operation. At low load the benefit does not seem apparent, though. This is because the gate driving losses become predominant, as it can be indirectly seen in Fig. 9. The significant reduction of the Ctrl. FET turn-off losses lets the Sync. FET losses as main focus of heat dissipation, particularly at low and half- load and in case of turning off at an early valley, i.e. valley n-1. The benefit of the invention is further manifested in Fig. 9, which shows that the increase of switching frequency from 3.2MHz to 4.7MHz virtually does not worsen the losses in the Ctrl. FET, as the rise of the gate driver and other source of switching losses are compensated by a reduction of the Ctrl. FET turn-off losses. This is so because early cur- rent valleys are less damped and thus closer to zero. This gives clear evidence of the effectiveness of the invention at high switching frequency or short duty cycles.

Fig. 9 further reveals that the generated Ctrl. FET power loss at around 5MHz is above 30% lower compared to that of the conventional solution at IMHz switching fre- quency. Valley switching as described previously needs a means for controlling the Ctrl. FET on time toN in such a way that the Ctrl. FET switches off at the current valleys. This implies that only values of toN proportional to the period of the ringing at the switch node during the Ctrl. FET conduction are allowed. To implement the invention several embodiments are proposed.

The first embodiment is represented in the diagram of Fig. 10. A valley switching control block 20 is integrated in the MOSFETs driver 21 and interconnected be- tween the PWM generator 22 and the driver control 23 blocks. The valley switching control 20 varies the toN time of the PWM signal to get valley switching, as illustrated in the waveforms of Fig. 11. The value of ΔtoN can be both positive (+) and negative (-). The drain current at turn-off may be monitored to calculate the required ΔtoN for the next switching cycle. The current sensing may however be avoided if the resonant frequency of the drain current oscillation is known. In this case, the system can add the required ΔtoN to have an on time that is proportional to the period of the oscillation.

Adding ΔtoN to the PWM signal may disturb the load line regulation. In order to avoid or reduce such disturbance, the concept of valley hopping may be applied. It consists of alternating positive with negative ΔtoN so as to average the on time to the value of the PWM signal. Therefore, an inner loop within the valley switching control is implemented, which alternately adds positive and negative ΔtoN values to toN in order to cancel out their effect at the converter output.

Alternatively, the valley switching control may act on the toN control of the load line regulation. The PWM signal is therefore conditioned to the valley switching control action and connected directly to the driver control block, as shown in the proposed scheme of Fig. 12. The embodiment may allow for alternative means to the valley-hopping concept for regulating the load line. This is discussed in more detail in the following sections.

In the further description two embodiments are discussed. The embodiments mainly aim at dealing with the regulation of any output voltage level despite of a limited discrete values that the Ctrl. FET on time can take. One embodiment is based on both switching frequency and duty cycle control of the load line. The second embodiment considers the val- ley hopping, which performs the point of load regulation at a fixed switching frequency. A common task is the phase detection of the resonant current. In one embodiment the drain-to-source voltage across the Sync. FET, vdsds, can be used to detect the valleys of the Ctrl. FET drain current. If the parasitic resistances of the half-bridge path are low enough, then the current valley occurs when the drain-to-source voltage equals approximately to the input voltage Vi, see Fig. 1, during the discharge phase of the Sync. FET output capacitance. Note that getting valley switching at exactly that point is not critical for the converter losses, as shown in Fig. 5a. Let R_RB be the total half-bridge resistance, which include the drain-to-source resistance of the switches and the ESR of the input filter capacitances. Then, in order to consider R_RB to be low so as to applied the above valley detection method, the following inequality must be accomplished,

where LRB is the total half-bridge parasitic inductance, and Coss s AV is the average output capacitance of the Sync. FET, which is defined as follows,

^ OSS _S AV y y OS S S (v)dv (2)

' MAX ^~ ' MIN

where V_MAX and V_MIN are the maximum and minimum drain-to-source voltage of the ringing oscillation prior to the beginning of the falling edge transition, respectively. Function Coss s is the output capacitance of the Sync. FET, which is assumed to be dependent on the drain-to-source voltage across the device.

According to this detection principle, the circuit of Fig. 13 is proposed as embodiment. The circuit 30 makes use of positive ramp detectors 31 to sense the charging phase of the output capacitance 33 of the power switches. A digital circuit 32 controls a switch for sampling and holding the value of vdsds signal at the first ramping up of the Ctrl. FET drain-to-source voltage, vdsdc, during the falling edge transition. At this time the sign of the derivative of vdsds is also stored.

Fig. 14 illustrates the operation of circuit of Fig. 13. During the on time of the Ctrl. FET, i.e. signal vc equals to 1, the flip-flops are reset and the trig signal is set to 0. Signals dvC and dvS set to 1 whenever the time derivatives of vdsdc and vdsds, respectively, are positive. The falling edge transition starts when the duty cycle signal goes to 0. Signal vc goes to 0 as well, which sets the refresh signal to 1. The sampling period of vdsds starts. As soon as vdsdc starts rising signal trig goes to 1, which triggers the sampling of dvS. The refresh signal goes then to 0 and thus the sampling switch of vdsds switches off. The holding period therefore starts.

The circuit 30 requires to measure the drain-to-source voltages of the switches, i.e. vdsds and vdsdc, as well as the Ctrl. FET signal vc. The measurement points of vdsds and vdsdc should be if possible as close as possible to the die so as to reduce the effect of the parasitic inductances of the half-bridge path.

The valley detection circuit has three outputs: the sample and hold vdsds and dvS, i.e. vdsds(s&H) and dvS(s&H), respectively, and the output of the positive ramp detector for the vdsds signal, dvS.

In a point of load application, the output voltage is typically controlled by means of the on time toN of the PWM (Pulse Width Modulation) signal while keeping constant the switching frequency. Another embodiment considers the switching frequency as control variable while keeping constant toN-

The proposed embodiment 40 takes both switching frequency and toN time of the PWM signal as control variables for the output voltage regulation. A VCO (Voltage Controlled Oscillator) is employed to generate the PWM signal. The particularity of the VCO in the proposed embodiment is that two inputs are available to independently adjust the switching frequency Fs and the on time toN- Two conventional independent controllers are therefore connected at the output of the comparator of the reference and measured values, as shown in the scheme of Fig. 15.

The output of the duty cycle controller provides a toN⁵ signal. The toN value that the VCO sees though is a corrected version of toN⁵, i.e. toN'+ΔtoN- The added ΔtoN is to control that the Ctrl. FET turn-off occurs at the current valleys. Variations of toN⁵ lower than T_osc (see Fig. 14) will be corrected by ΔtoN so as to maintain valley operation. Therefore, the correction of toN⁵ bounds the Ctrl. FET on time upon steady state operation to discrete values corresponding to those providing valley switching. The generation of ΔtoN is carried out in the toN correction block. The output value depends on an error signal that is generated by the error estimation block. Fig. 16 shows the circuit diagram of the toN correction block. A dependent current source charges and discharges a capacitor whose voltage across Vr is proportional to ΔtoN- The sign of the error signal dictates the current direction. A constant positive error linearly charges up the capacitor, whereas a negative value discharges it, as shown in Fig. 17. Voltage Vr remains unchanged when error equals to zero. The relation between Vr and ΔtoN is given by the following expression,

At_^1 = _ * OSC

ON ~, Vr (3)

2Ka

The voltage range of Vr is 2Va, which corresponds to an on time variation of Tosc, that is, the time between two consecutive valleys,

Δt ON(MAX) ⁼ ^ OSC V V

When Vr exceeds Va a comparator activates a switch to discharge capacitor C to -Va. Likewise, the capacitor is charged up to Va whenever Vr is lower than -Va. Thus, the Ctrl. FET on time can be varied between -0.5Tosc and +0.5Tosc- Such range ensures that at least one current valley (e.g. the closest to the turn-off time) can be detected.

The current that charges capacitance C is directly proportional to the increment of Ctrl. FET on time that is required for valley switching, defined as ΔtoNr, and inversely proportional to the switching period Ts, as shown in the following expression,

r 2CKa _A / = error = — Vr = —— At_0Nr (5)

*s *s*osc

Thus, the injected current value is such that the charged voltage across capacitance C in the next falling edge transition effectively produces a Ctrl. FET on time correction of ΔtoNr- Both ΔtoNr and Tosc are calculated in the error estimation block. The period Tosc can be obtained by means of a period detector or by means of calculating the time period between two consecutive leading edge transitions of signal dvS. The estimation of ΔtoNr could be realised adaptively with a PI controller. A more precise alternative may be applied if the resonant oscillation is assumed to be sinusoidal. It is therefore straightforward to estimate ΔtoNr by means of the following expressions,

or,

T

At_^1,, _ = ^, OSC

¹ONr 1 sin -1 vdsd_S(S&H) - Vi if dvS_(S&H, < 0 (7) π K m_™ax - Vi

where V_max is the maximum voltage of vdsds and it can be sensed with a voltage peak detector. Note that the above expressions are valid when the output capacitance of the Sync. FET is approximately linear. This might be the case when adding parallel linear capacitors to the device.

Valley hopping regulates the output voltage by means of alternating valleys in the neighbourhood of a targeted duty cycle. The system has as unique control variable the Ctrl. FET on time and operates at constant switching frequency. A conventional load line controller 40 is used as shown in the diagram of Fig. 18. Such controller 40 generates a certain duty cycle to regulate the output voltage, i.e. signal t_ON'. Yet, only discrete values of Ctrl. FET on time toN corresponding to valley switching are input to the PWM generator 41. The valley hopping controller 42 alternates between valleys to generate an effective averaged on time that equals to toN⁵- The alternated valleys are those two being the closest to the targeted toN⁵, being T_Osc the time difference between them.

The toN correction block generates the required on time increment to track valley switching, as described in the previous section. In order to hop between the closest valleys to toN⁵, the tosc generation block adds a quantity to the output of the t_ON correction block according to the following algorithm, if reg > 0 & Δt_ON'< 0 then out = T_osc elseif reg < 0 & Δt_OΛ,'> 0 then out = -T_osc else out = 0

When signal reg from the valley hopping controller gets positive orders toN to be larger or equal than t_ON⁵ and therefore Δt_ON must get higher or equal to 0. Thus, the output tosc equals to Tosc in case ΔtoN' is negative. This causes the system to jump to the next valley and t_ON to be higher than t_ON'. The opposite occurs when reg is negative, as observed from the above algorithm. No value is added to ΔtoN' in case none of the above conditions are satisfied. The above algorithm might be implemented with the circuit of Fig. 19.

Signal reg is generated by the valley hopping controller, which may consist of a conventional PI controller. The control aims at reducing the average value of the ΔtoN to zero, thereby achieving an effective average t_ON equal to t_ON'.

Note that the bandwidth of the valley hopping control is significantly higher than that of the load line control so that to filter out the jittering effect that valley hopping may cause at the output of the converter.

The proposed valley- switching concept can be extended to other synchronous rectifier converter topologies, such as the boost converter. Furthermore, valley switching can be applied at the leading edge transition, particularly in applications where a high duty cycle is required.

Combining the concept of valley hoping in combination with frequency and duty cycle control it is possible to simultaneously allow for valley switching in both leading and falling edge transitions. The circuit to be design for such purpose corresponds to that of Fig. 20. Components Lr and Cr are no longer parasitic impedances but perform the task for zero-voltage-switching (ZVS) operation in both switches. Basically, the undamped series resonant circuit formed by inductance Lr and capacitance Cr provides ZVS in both leading and falling edge transitions. The output filter Lo and Co has the same functionality as in the conventional buck converter. The operation combines duty cycle and switching frequency control with valley hopping (as described above) in order to cope with ZVS in both leading and falling edge transitions as well as the output voltage regulation (valley hopping). The benefϊts of the converter are already described in the first sections, including the great benefit of getting ZVS at leading edge. The fundamental drawback is the high ripple current through the switches due to the resonant current, which must be proportional to the output load current.

In general the invention may advantageously be used in applications such as VRMs and PoL, e.g. power supplies for notebook PCs, graphic cards and semiconductor related products such as integrated power train modules and other discrete solutions for high current and low voltage applications. The invention may also target at other synchronous rectifier converter circuits that employ MOSFET devices driven at high frequency, hard switching operation, such as the boost converter.

References

1 switched circuit

2 capacitors

3 capacitors

4 inductance

5 output coil

6 power switch

7 power switch

20 control block

21 driver

22 PWM generator

23 driver control block

30 circuit

31 positive ramp detector

32 circuit

33 output capacitance

40 load line controller

41 PWM generator

42 valley hopping controller

Claims

CLAIMS:

1. Electronic power switching device and control scheme characterized in that the ringing caused by a switching action is exploited in the next commutation of the switching device.

2. Electronic power switch and control scheme according to claim 1 wherein the ringing caused by a switching action is synchronized with the electronic power switch turn- off time.

3. Electronic power switch and control scheme according to claim 1 wherein the ringing caused by a switching action is synchronized with the electronic power switch turn- on time.

4. Electronic power switch and control scheme according to claim 1 wherein the ringing caused by a switching action is synchronized with the electronic power switch turn- on and turn-off times.

5. Electronic power switch device and control scheme according to at least one of the claims 1 or 2 wherein the turn-off switching time occurs at the valley of the oscillating current through the switching device.

6. Electronic power switch device and control scheme according to at least one of the claims 1 or 3 wherein the turn-on switching time occurs at the valley of the oscillating current through the switching device.

7. Electronic power switch device and control scheme according to at least one of the claims 1 or 4, wherein the turn-on and turn-off switching times occur at the valley of the oscillating current through the switching device.

8. Electronic power switch device and control scheme according to at least one of the preceding claims, wherein the power switch device is a FET, bipolar, MOSFET or IGBT.

9. Electronic power switch device and control scheme according to at least one of the preceding claims implemented as control switch for buck converters, boost converters, synchronous rectifiers and/or other hard-switched power converters.

10. Electronic power switch device and control scheme according to at least one of the claims 1 to 9, wherein a valley switching control block (20) is integrated in a switch driver.

11. Electronic power switch device and control scheme according to at least one of the claims 1 to 10, wherein a valley switching control block (20) is interconnected between a PWM generator (22) and a driver control block (23).

12. Electronic power switch device and control scheme according to at least one of the claims 1 to 9, wherein a valley switching control block (20) is interconnected between the driver and the controller of the PWM generator (22) of the power converter.

13. Electronic power switch device and control scheme according to claim 12, wherein the controller of the PWM generator (22) of the power converter further acts as a function of the output signal from the valley switching control block (20).

14. Electronic power switch device and control scheme according to at least one of the claims 1 to 9, wherein both the duty cycle and the switching frequency variables are employed to independently control the output voltage of the power converter and the valley switching of the switch device.

15. Electronic power switch device and control scheme according to claim 14, wherein a voltage controller oscillator (VCO) with adjustable on time is employed to allow for duty cycle and switching frequency control variables.

16. Electronic power switch device and control scheme according to at least one of the preceding claims, wherein at least one positive ramp detector (31) is provided to sense the leading edge of the voltage oscillation at the switching node of the power converter.