WO2004023552A1

WO2004023552A1 - Multichp semiconductor device, test method, and system board

Info

Publication number: WO2004023552A1
Application number: PCT/JP2002/009052
Authority: WO
Inventors: Masayuki Sato; Isao Shimizu; Kenichi Tonomura
Original assignee: Renesas Technology Corp.
Priority date: 2002-09-05
Filing date: 2002-09-05
Publication date: 2004-03-18
Also published as: TW200408815A; JPWO2004023552A1

Abstract

A multichip semiconductor device comprising a package case (100) capable of holding semiconductor chips, semiconductor chips (200) held by the package case, and an insulating board (110) provided with wirings (112, 113) electrically connected to the semiconductor chips and a cross point switch circuit (114) provided at cross points of the wiring and serving as wiring route switching means capable of interconnecting given wirings and made of a low-dielectric constant material joined to the package case.

Description

Description Multichip semiconductor device, test method, and substrate for system

The present invention relates to a semiconductor device composed of a plurality of semiconductor chips and a test technique therefor, for example, a multi-chip module in which a plurality of semiconductor chips are mounted on a single substrate and sealed in a package, and a plurality of systems. The present invention relates to technology that is effective when used for a system substrate that can respond to problems. Background art

In recent years, the development of an LSI called a system LSI, in which a CPU (Central Processing Unit), a memory, and custom logic are mounted on a single semiconductor chip, has been actively performed. On the other hand, the miniaturization technology of semiconductors is evolving year by year, and in recent years, submicron technology such as 0.3 μm has been established. is there. System LSI is being developed with the support of such semiconductor miniaturization technology.

However, as the miniaturization of semiconductors advances, the importance of developing high-dielectric-constant insulating films increases from the viewpoint of speeding up MOS transistors.However, in order to suppress noise signal interference due to the coupling capacitance of wiring. It is effective to use a material with a low dielectric constant as the insulating film between wirings, and it is becoming clear that the development of an insulating film with a low dielectric constant is also important. However, it is difficult to form an insulating film with a high dielectric constant and an insulating film with a low dielectric constant on a single semiconductor chip. It has been found that there is a limit to naturalization.

By the way, epoxy resin and ceramic are known as low dielectric constant materials. Conventionally, a device called a multi-chip module in which a plurality of chips are mounted on a printed wiring board in which wiring is formed on an insulating substrate made of such a material. It has been known. In a multi-chip module, the global distribution connecting the chips Lines are formed on or inside the substrate with a low dielectric constant, and local wiring in the chip is formed on an insulating film with a high dielectric constant. This increases the speed of the MOS transistor and reduces noise and signal due to coupling capacitance between wirings. The two requirements of reducing interference. Therefore, it is considered that the development of a multi-chip device that constructs a system by encapsulating multiple semiconductor chips in a single package together with the system LSI is expected in the future.

However, in a system composed of a plurality of semiconductor chips, in addition to a test for checking whether each semiconductor chip operates normally, the system operates normally when assembled as a system. It became evident that a test to check whether or not it would work was indispensable, and that there was a problem that the time required for the test would increase and the cost would increase accordingly. On the other hand, as the size of the semiconductor integrated circuit increases, it becomes difficult to test circuits at the back of the chip, and on a chip with built-in analog circuits, if signal lines are provided for testing the analog circuits, the signal There is a problem that the characteristics of the circuit change depending on the line.

In addition to testing using a device called a tester, a semiconductor chip test technology uses a technology called DFT (design 'for' test aspirity) that provides a scan path inside the chip for testing, and an ALPG (algorithmic) A technique called BIST (Built-in 'Self' test) is known, in which a self-test is enabled by providing a test circuit consisting of a pattern and a generator. In recent years, a technology for providing a test circuit or wiring in a squeeze area of a wafer and performing a test on the wafer, and a technology for configuring and testing a test circuit on a board such as an aging board have been proposed.

In addition, there is an invention relating to a wiring board provided with a test structure in which a plurality of switch elements are arranged in a matrix on the wiring board so that wiring paths can be switched so that a system test can be performed. Japanese Patent Application Publication No. 2007-38).

SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-chip device capable of high-speed operation and having less noise and signal interference due to the coupling capacitance of wiring.

Another object of the present invention is to reduce the time required for testing. An object of the present invention is to provide a method for testing a multichip device.

Still another object of the present invention is to provide a substrate for an electronic system that can be used for configuring a plurality of multichip devices having different system configurations or for testing a semiconductor chip.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Disclosure of the invention

The following is a brief description of an outline of a typical invention disclosed in the present application.

That is, a package case capable of holding a plurality of semiconductor chips, a semiconductor chip held in the package case, a wiring electrically connected to the semiconductor chip, and an optional wiring provided at an intersection of the wiring. A cross-point switch circuit as a wiring path switching means capable of connecting the wirings is provided, and a multi-chip device is constituted by an insulating substrate made of a low dielectric material or the like joined to the package case. .

According to the above-described means, a semiconductor chip can be formed with a high dielectric constant material to form an insulating film that insulates between wirings, thereby enabling high-speed operation of a circuit. Since the connection can be made with the wiring formed on the substrate, a multi-chip device with less noise and signal interference due to the coupling capacitance of the wiring can be realized.

In addition, since the board is provided with wiring path switching means that can connect arbitrary wirings, it is necessary to provide regular wiring and other wiring that can configure a test circuit, for example, on the board. As a result, each semiconductor chip constituting the device can be tested independently, and the test as a system is also possible, thus facilitating the test and shortening the test time. . In addition, it is possible to configure a test circuit using semiconductor chips on a substrate, and to test other chips with the test circuit. This makes it possible to test without using a high-performance tester. Strikes.

Another aspect of the present invention is a substrate including: a plurality of wirings arranged to cross each other; and wiring path switching means provided at an intersection of the wirings and capable of connecting arbitrary wirings. A pair of lead-shaped wirings whose free ends are opposed to each other at a predetermined distance from each other, and a magnetic piece provided at the tip of the lead-shaped wiring or in the vicinity thereof; An element configured to be able to set the ON / OFF state of the switch depending on whether or not the magnetic piece has a magnetic pole is used.

According to the above-mentioned means, by mounting semiconductor chips of different functions or numbers on the substrate and setting the state of the switch element at the wiring intersection, a highly versatile substrate capable of constructing a different system is provided. Can be realized. It is also possible to configure a test circuit with semiconductor chips on a board before building a system, to test other semiconductor chips or to use it as a test board for any semiconductor chip. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a plan view showing an embodiment of a package case constituting a multichip module to which the present invention is applied.

FIG. 2 is a rear view showing an embodiment of a cap board which constitutes a multichip module to which the present invention is applied.

FIG. 3 is an explanatory diagram showing an example of the internal structure of the substrate of FIG.

FIG. 4 is a circuit diagram showing one embodiment of a cross point switch circuit provided on the substrate of FIG.

FIG. 5 is an enlarged cross-sectional view showing a state where the multichip module of the embodiment is assembled.

FIGS. 6A and 6B show specific examples of switch elements constituting a cross-point switch circuit suitable when the substrate is made of a low dielectric constant material. FIG. 6A is a front sectional view, and FIG. It is sectional drawing. FIGS. 7A and 7B show specific examples of switch elements constituting a cross point switch circuit suitable for a case where the substrate is made of a semiconductor crystal. FIG. It is sectional drawing.

FIG. 8 is a circuit diagram showing another configuration example of a cross-point switch circuit suitable when the substrate is made of a semiconductor crystal.

FIG. 9 is a sectional view showing a specific example of a nonvolatile memory element used as a switch element constituting the cross point switch circuit of FIG.

FIG. 10 is a circuit configuration diagram showing an example of a peripheral circuit for enabling connection information to be written to a nonvolatile memory element included in the cross point switch circuit of FIG.

FIG. 11 shows another specific example of a switch element constituting a cross-point switch circuit suitable when the substrate is made of a low-dielectric-constant material. FIG. 11 (A) is a front sectional view, and FIG. Is a plan sectional view. '

FIGS. 12A and 12B show another specific example of a switch element constituting a cross-point switch circuit suitable when the substrate is made of a semiconductor crystal. FIG. 12A is a front sectional view, and FIG. Is a plan sectional view.

Fig. 13 shows a magnetizing device that can be turned on and off when the magnetic switch element that composes the cross-point switch circuit in Fig. 3 is a switch element with a structure as shown in Figs. 11 and 12. It is a schematic structure figure showing an example.

FIG. 14 is a block diagram showing an application system having an analog circuit as an example of a system suitable for applying the multichip module of the present invention.

FIG. 15 is a flowchart showing a procedure of a test method of the multichip module of FIG. 1 to which the present invention is applied. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

1 and 2 show one embodiment of a multichip module to which the present invention is applied. Figures 1 and 2 show the state before assembly as a module. (With the case and cap open).

In FIG. 1, reference numeral 100 denotes a package case formed of an arbitrary material such as a synthetic resin and capable of holding a plurality of semiconductor chips. The package case 100 has a recess having substantially the same shape as the outer shape of the chip to be held. Are formed in a predetermined arrangement, and the semiconductor chip 200 is accommodated in each concave portion. At this time, each chip is recessed in the package case 100 with the connection parts provided for electrical connection to other chips and terminals such as bonding pads facing upward (see reference numeral 120 in FIG. 5). Is stored in.

Although not particularly limited, in this embodiment, as an example of the semiconductor chip 200 constituting the module, a CPU (central processing unit) 210 ゃ static RAM (random access memory) 2 2 0, dynamic RAM 230, custom logic chip 240 such as user logic circuit that configures the logic function required by the user, FPGA that allows the user to freely configure the logic (field 'programmable' gate · Array) 250 is shown. The semiconductor chip 200 constituting the module is not limited to these, and may be another chip such as a DSP (digital signal processor), a DMA controller, an A / D conversion circuit, or a D / A conversion circuit.

The static RAM 220 and the dynamic RAM 230 include memory peripheral circuits such as an address decoder that selects a corresponding memory cell when an address signal is applied. Further, the dynamic RAM 230 includes a refresh control circuit that performs pseudo-selection periodically so that information charge of the memory cell is not lost even when the non-access time becomes long. Also, although not particularly limited, the dynamic RAM 230 includes, when a defective bit is present in the memory array, a memory row or a memory column including the defective bit in a spare memory row or a spare memory row. A so-called redundant circuit that replaces the memory column is provided.

FIG. 2 shows the back surface of the substrate 110 also serving as a cap bonded to the package case 100, that is, the surface bonded to the package case 100 of FIG. This is a low dielectric constant material such as epoxy resin or ceramic or silicon. And the like. On the back of the board i10, the package case

A surface wiring 112 connecting the bus 111 and the chip electrically connected to the semiconductor chip 200 held at 100 is formed.

Also, inside the substrate 110, that is, between any layers of the substrate having a laminated structure of a plurality of insulator layers, each of the internal wirings 113 arranged in a lattice pattern and each of the internal wirings 113 is formed. There is provided a contact point switch circuit 114 which is provided at a point and which can connect arbitrary wirings in the up, down, left, right, or diagonal directions in the figure.

Further, on the back surface of the substrate 110, any one of the internal wirings 113 is brought into contact with a pad or a wiring of the semiconductor chip 200 held in the package case 100 for electrical connection. Contact points 1 15 are provided. The contact point 115 may be an electrode pad such as a bonding pad or a contact hole formed in an insulating film so as to expose a signal line on a chip through which a signal to be taken out is transmitted.

As described above, in this embodiment, the wiring connecting between the semiconductor chips is provided on the substrate 110 made of a low dielectric constant material such as epoxy resin or ceramic. Since the coupling capacitance is small, noise can be transmitted from one wiring to another wiring due to crosstalk, and distortion due to interference between signals can be suppressed. In addition, since the substrate 110 has a grid-like internal wiring 113 and a cross-point switch circuit 114 provided at each intersection of the internal wiring 113, any one or a plurality of chips are provided. Can be used to construct a test circuit that tests other chips, thereby allowing the chip that constitutes the module to be tested without using a sophisticated tester.

In addition, since there is no need to provide a test circuit such as a BIST on the chip itself, the size of the chip that constitutes the module can be reduced, and the module can be downsized. Furthermore, in the module of the embodiment, it is possible to reconfigure the same hardware composed of the same semiconductor chip as a system having different functions by resetting the cross point switch circuit 114. is there. Two

8 Although not shown in FIG. 2, pads or lead terminals (pins) connected to the path 111 and connected to an external device other than the module are provided on the front side of the substrate 110. Is provided. In addition to the pads or lead terminals connected to the bus 111, pads or lead terminals for directly connecting the external terminals of any semiconductor chip and the external device should be provided on the front side of the substrate 110. May be.

FIG. 3 is an enlarged view of the internal wiring 113 of the substrate 110, and FIG. 4 shows a specific example of the cross point switch circuit 114 provided at each intersection. In the embodiment of FIG. 3, the cross point switch circuits 114 are provided at all the intersections of the internal wirings 113, but it is also possible to provide every other or every several points. It is. Further, the internal wiring 113 is constituted by a plurality of conductive layers by a multilayer wiring technique. In FIG. 3, wirings 113 'shown by broken lines are wirings of different conductive layers.

As shown in FIG. 4, the cross point switch circuit 114 is provided at the intersection of the vertical signal lines Ly 1, Ly 2 and the horizontal signal lines LX 1, Lx 2, Switch SW1 that can connect and disconnect between the signal lines Ly1 and Ly2 in the opposite direction, switch SW2 that can connect and disconnect between the horizontal signal lines LX1 and LX2, and the signal line in the vertical direction A switch SW3 that can connect and disconnect between Ly1 and the horizontal signal line LX1, and a switch SW4 that can connect and disconnect between the vertical signal line Ly1 and the horizontal signal line LX2 Between the vertical signal line Ly2 and the horizontal signal line LX2 and the switch SW5, which can be separated, between the vertical signal line Ly2 and the horizontal signal line Lx1 And a switch SW6 that can be connected and disconnected.

In FIG. 4, the signal lines indicated by the symbols SX 1, SX 2, SX 3... And SY 1, SY 2, SY 3. A control line for setting the off state and a signal line RRL meandering around each switch are release lines for releasing the on / off state of the switches SW1 to SW6. If all of the cross point switch circuits 114 shown in FIG. 3 are constituted by a circuit composed of six switches SW1 to SW6 as shown in FIG. Instead, a circuit having only the switches SW1 and SW2 among the switches SW1 to SW6 may be arranged at a certain intersection, and a circuit having the switches SW3 to SW6 among the switches SW1 to SW6 may be arranged at the adjacent intersection. . Similarly, a cross-point switch circuit composed of other combinations of the switches SW1 to SW6 is also conceivable.

FIG. 5 shows a cross-sectional structure of the multichip module of the embodiment. In FIG. 5, the same reference numerals as in FIG. 2 denote the same members or parts.

Although not particularly limited, in FIG. 5, the substrate 110 is provided with four layers of internal wiring 113. Of these wirings, Lxl, Lx2 and SXI, SX2, SX3 ... are on the same wiring layer, and Lyl, Ly2 and SY1, SY2, SY3 ... are on the other. The same wiring layer is used, and the wiring connecting the release line RRL and the chip is formed by another wiring layer.

In FIG. 5, reference numeral 120 denotes a recess provided in the package case 100 for storing the semiconductor chip 200, 130 denotes a pad provided on the semiconductor chip 200, and 116 denotes a pad. An insulating layer made of a low dielectric constant material such as epoxy resin constituting the substrate 110, and 117 is a conductive layer connecting the internal wiring 113 provided on the substrate and the pad 130 of the semiconductor chip 200. It is a via consisting of a body. The node 130 and the via 116 are connected with a low melting point metal such as a solder ball or a conductive adhesive. In recent years, research has been conducted on a room-temperature bonding technology in which a surface to be bonded is mirror-finished and bonded by using an adhesive without using an adhesive, and the connection is performed using such a technology. Is also good.

FIG. 6 shows a specific example of the switches SW1 to SW6 constituting the cross-point switch circuit 114 suitable when the substrate 110 is made of a low dielectric constant material such as an epoxy resin. 6A is the same front sectional view as FIG. 5, and FIG. 6B is a plan sectional view.

In this embodiment, as shown in FIG. 6, a void 1 18 is formed in an insulator layer 1 16 a to 1 16 c constituting a substrate, and a pair of internal portions are formed in the void 1 18. The wirings 114a and 114b protrude from the left and right, and are opposed to each other so that their tips are slightly apart. So Then, ferromagnetic layers] VIG 1 and MG 2 are formed on the opposing surfaces of the tips of the internal wirings 114 a and 114 b, respectively. The structure shown in FIG. 6 is a structure suitable for forming a substrate by laminating an insulator layer and a conductor layer by a known substrate processing technique. Specifically, the internal wirings 114a and 114b are formed by lamination with different conductor layers, respectively. The ferromagnetic layers MG1 and MG2 can be formed by the lamination technique like the internal wirings 114a and 114b, but they can also be formed by applying a magnetic material.

FIG. 7 shows a specific example of the switches SW1 to SW6 constituting the cross-point switch circuit 114 suitable when the substrate 110 is made of a semiconductor crystal. 7A is a front sectional view same as FIG. 5, and FIG. 7B is a plan sectional view.

In this embodiment, as shown in FIG. 7, a void 1 18 is formed in the insulator layers 1 16 a and 1 16 b, and a pair of internal wirings 1 1 4 are formed in the void 1 18. a, 114b protrude from the left and right, and are opposed to each other with their tips slightly apart. Ferromagnetic layers MG 1 and MG 2 are formed on the opposing surfaces of the internal wirings 114 a and 114 b, respectively. The structure shown in FIG. 7 is a structure suitable for being formed by combining deposition and etching of an insulator layer or a conductor layer on a crystal substrate by a known semiconductor manufacturing technique.

Specifically, the insulator layers 116a and 116b are deposited on a substrate made of a semiconductor crystal by a known CVD method (chemical vapor deposition method), a plasma CVD method, or the like. 4a and 114b are formed by removing excess portions of the conductor layer deposited by a CVD method, a sputtering method, or the like by a known plasma etching method, reactive ion etching, or the like. The ferromagnetic layers MG 1 and MG 2 can be formed by deposition and etching in the same manner as the internal wirings 114 a and 114 b, but strong at the tips of the internal wirings 114 a and 114 b. A magnetic material may be applied to form the MG 1 and MG 2 layers. The semiconductor crystal may be a single crystal or a polycrystal. When switches having the structure shown in FIG. 6 or FIG. 7 are used as the switches SW1 to SW6 constituting the cross point switch circuit of FIG. 4, one of the control lines SX1, SX2 and SX3 is used. One of the SY 1, SY 2, SY 3 By selecting one of them and passing a current in a predetermined direction, the ferromagnetic layer MG 1 at the tip of the internal wiring 1 1 4a, 1 1 4b located at the intersection of the selected control line is selected. , MG 2 can be magnetized.

That is, one of the control lines SX1, SX2, SX3... And SY1, SY2, SY3... Shown in FIG. The magnetic field generated when a current in a predetermined direction is passed through both control lines is strengthened mutually near the ferromagnetic layers MG 1 ′ MG 2 so that they pass near the switch. , MG 2 can be magnetized in a predetermined direction, and the ferromagnetic layers MG 1, MG 2 are arranged so as not to be magnetized even if a current flows only in one of the control lines passing near the MG 2.

Thereby, the ferromagnetic layers MG 1 and MG 2 at the tips of the internal wirings 114 a and 114 b located at the intersections of the selected control lines can be magnetized. When the ferromagnetic layers MG1 and MG2 are magnetized, the switches are magnetized and the ferromagnetic layers MG1 and MG2 are attracted to each other, and the internal wirings 114a and 114b are turned on and turned on. Set. In addition, an alternating magnetic field can be generated by passing an alternating current through the release line RRL to demagnetize the ferromagnetic layers MG 1 and MG 2 of all the magnetic switches. As a result, the switch in which the ferromagnetic layers MG1 and MG2 are demagnetized returns to the original state by returning the internal wirings 114a and 114b to elasticity and returns to the off state.

As described above, since the cross point switch circuit of the present embodiment can connect or disconnect desired signal lines, in the circuit of FIG. 3, a test is performed by connecting terminals of arbitrary chips. After that, it is possible to easily change the system such that the connection is changed and the system is reconfigured to a desired system.

FIG. 8 shows another example of a cross point switch circuit 114 suitable for the case where the substrate 110 is made of a semiconductor crystal such as silicon. This embodiment uses a nonvolatile storage element composed of a MOS FET having a floating gate used in flash memory or the like as a switch element constituting a cross point switch circuit 114, as shown in FIG. Switches SW1 to SW6 are replaced with two non-volatile memory elements in series. Have.

Specifically, non-volatile memory elements F 11 and F 12 in series form are provided between the vertical signal lines Ly 1 and Ly 2, and the horizontal signal lines LX 1 and LX 2 The non-volatile memory elements F 21 and F 22 in the serial form are interposed between them, and the non-volatile memory elements F in the serial form are interposed between the vertical signal line Ly 1 and the horizontal signal line LX 1. 3 1, F 32, series-connected nonvolatile storage elements F 41, F 42, vertical signal line L between vertical signal line Ly 1 and horizontal signal line L x 2 The non-volatile memory elements F51, F52 in a serial form are connected between the y2 and the horizontal signal line Lx2, and the vertical signal line Ly2 and the horizontal signal line Lx1 are connected. Between them, series-connected nonvolatile memory elements F 61 and F 62 are provided.

In FIG. 8, SX1 to SX4 and SY1 to SY4 are the non-volatile memory elements Fll, F12; F21, F22;..., F61, F62 on and off. This is a control line for controlling the status. Control lines SX1 to SX4 are arranged in parallel with wiring LX1 and LX2, and control lines SY1 to SY4 are arranged in parallel with wiring Ly1 and Ly2. ing. One of the control gate terminals of the pair of series-type nonvolatile memory elements is connected to one of the horizontal control lines SX1 to SX4, and the other control gate terminal is connected to the vertical control line. Connected to any one of control lines SY1 to SY4.

In the embodiment shown in FIG. 8, two non-volatile memory elements are provided in series between each signal line. However, in principle, one element may be provided between each signal line. The two non-volatile memory elements in the series configuration can be selected by setting only one of the control lines SX 1 to SX 4 and SY 1 to SY 4 that are orthogonal to each other to the selected level. Or one set of non-volatile storage elements. If only one non-volatile storage element is provided between each signal line and one of the non-volatile storage elements is selected, another control is performed for each non-volatile storage element at each intersection. It becomes necessary to provide wires, and the number of control wires becomes very large.

On the other hand, when two non-volatile memory elements in a series form are used as in the embodiment, In this case, if only one of the control lines SX 1 to SX4 and SY 1 to SY4 is set to the selection level, only one set of nonvolatile memory elements can be selected at each intersection. (4) A common control line can be provided for the cross point switch circuit at the intersection of the same row, and the total number of control lines can be greatly reduced. Note that, as described above, only one set of nonvolatile storage elements is selected at each intersection and writing (for example, operation of lowering the threshold voltage) is performed, and in the normal state, all the control lines LX and Ly are connected. When set to the selection level (high level), only the storage element to which writing has been performed in advance is turned on, and the corresponding signal lines can be connected so that signals can be transmitted.

By the way, as described above, the connection switching means between the signal lines is constituted by using the two nonvolatile storage elements in series, and any one of the storage elements is provided by the orthogonal control lines SX1 to SX4 and SY1 to SY4. In the case where the configuration is selected, the writing (injection of charges into the floating gate) of the storage information, that is, the writing of the connection information to the plurality of storage elements in the same row or column is not performed. There is a need to. For example, assuming that the memory elements F32 and F41 whose gates are connected to the control line SX1 in FIG. 8 are formed in the same pail region. In this case, the control lines SX1 and P41 are connected to each other. If a write voltage is applied during that time, writing will be performed simultaneously on F32 and F41. The following method can be considered as a method for writing data to all storage elements one by one while avoiding such simultaneous writing. First, as shown in FIG. 8, the cell regions WL 1 and WL 2 are formed in two rows on the substrate surface so as to be parallel to the vertical control lines SY 1 and SY 2. The storage elements (eg, F32 and F41) whose gate terminals are connected to the direction control line SX are formed on the above-mentioned separate roll-up areas WL1 and WL2 formed vertically. . However, storage elements in the same column connected to different horizontal control lines are formed on the same cell region formed in the vertical direction. Specifically, for example, F32, F22, and F61 are formed on the well WL1, and F41, F11, and F52 are formed on the well WL2.

Then, they intersect via one of the control lines SX and the well region WL. A high voltage is applied between the gate and the well of the storage element F ij at the position where the threshold voltage is to be written, and writing is performed by the tunnel phenomenon to lower the threshold voltage, for example. In this way, by selectively applying a write voltage to any one of the horizontal control lines SX and any one of the vertical well regions WL, only one of the storage elements located at the intersection thereof is Writing can be performed.

Next, the storage element whose threshold voltage has been lowered as described above is used, and a high-level voltage is applied to the gate terminal of the storage element using a control line (SX system), and the storage element is used. Is turned on, a write voltage is applied to the control line (SY system) to which the gate of the storage element that is paired is connected, and a potential difference is applied between the signal lines to be connected, and a drain current flows. As a result, the threshold voltage is lowered by injecting hot carriers generated in the channel into the floating gate. As a result, the threshold voltage of the storage element forming the pair can be reduced similarly to the other storage element.

According to the above-described method, writing by drain current cannot be performed on a storage element paired with a storage element having a high threshold voltage because no voltage is applied between the gate and the well, but it is desired to connect the storage element. In the method according to the present embodiment in which a pair of nonvolatile storage elements are provided between signal lines and only one set is made conductive by orthogonal control lines, the storage elements forming a pair have the same state, that is, one pair has a low threshold voltage. If so, the other has a low threshold voltage, and if one has a high threshold voltage, the other has a high threshold voltage. Therefore, there is no problem even if the above-described writing method is employed. Further, in the above embodiment, the case where the threshold voltage of one of the six nonvolatile memory elements is selectively reduced has been described. It is also possible to increase the threshold voltage of the semiconductor device so that only the increased device is turned on in the normal operation state. Furthermore, by selectively changing the threshold voltage of six sets of two or three sets of non-volatile memory elements, one signal can be branched to a plurality of signal lines, or conversely, a wired logic of a plurality of signals can be used. It is also possible to adopt a configuration in which the signal is transmitted as a sum signal.

FIG. 9 shows a nonvolatile memory constituting the cross point switch circuit 114. An example of the structure of the elements F11 to F62 is shown.

In FIG. 9, reference symbol S UB denotes a substrate made of a semiconductor crystal such as silicon, WL denotes a cell region having a different conductivity type or impurity concentration from the substrate formed on the substrate surface, and FL denotes an insulating film on the substrate S UB (shown in FIG. A floating gate consisting of a conductive layer formed through the) and CG are control gates connected to the control lines SX and SY. The floating gate FG and the control gate CG are also separated by an insulating film (not shown). Although not particularly limited, in this embodiment, the conductivity type of the substrate SUB is N-type, and the conductivity type of the cell region WL is P-type. S RC and DRN are self-aligned technologies. The source and drain of the MOS FET are composed of a high concentration diffusion layer formed on the surface of the substrate S UB on both sides of the floating gate FG. Area.

FIG. 10 shows an example of a peripheral circuit for enabling connection information to be written to the nonvolatile storage elements F 11 to F 62 that constitute the cross point switch circuit 114.

As shown in FIG. 10, in this embodiment, the selection line SX 1 to which the gates of the nonvolatile storage elements F 12, F 21,... Of the plurality of connection switching means arranged in the horizontal direction are connected. , SX 2, SX 3, SX 4... Are connected to an X-switch decoder XS-DEC. One end of the selection lines SY1, SY2, SY3, SY4,... Connected to the gates of the nonvolatile storage elements F11, F42,. Y switch decoder YS—Connected to DEC.

The decoder XS—DEC decodes the address signal XAD input from the outside of the chip and sets one of the select lines SX 1, SX 2, SX 3, SX 4,. I do. The decoder YS-DEC decodes an address signal YAD input from outside the chip and selects one of the selection lines SY1, SY2, SY3, SY4,. Is set to the selection level. The decoders XS-DEC and YS-DEC operate normally after the setting of the connection switching means is completed by writing to each nonvolatile element. During operation, it is configured so that all the select lines SX1, SX2, SX3, SX4 ... and SY1, SY2, SY3, SY4 ... can be set to high level (or low level). ing.

Incidentally, FIG. 1 0 Select line SX i, shows a peripheral circuit relating SY j _c signal line L xi, with respect to the feed system of L yj Oyopi Ueru WL j, or provided the same decoders, This can be dealt with by a method such as providing a pad to which a direct voltage is applied. The nonvolatile memory elements at the intersections of the signal lines constituting the cross point switch circuit are all erased, that is, turned off before writing is started. Then, in that case, the signal lines of the variable wiring circuit are separated from each other, and it is difficult to immediately write to the nonvolatile memory element at the center of the chip. Therefore, writing to each nonvolatile memory element on the chip may be performed in order from the one at the corner of the chip.

FIG. 11 shows another embodiment of the switches SW1 to SW6 constituting the cross-point switch circuit 114 suitable when the substrate 110 is made of a low dielectric constant material such as epoxy resin ceramic. FIG. 12 shows another embodiment of the switches SW1 to SW6 suitable when the substrate 110 is made of a semiconductor crystal such as silicon. In FIGS. 11 and 12, (A) is a front sectional view, and (B) is a plan sectional view.

In these embodiments, the control lines SX1, SX2, SX3 ... and SY1, SY2, SY3 ... shown in Fig. 4 and the release line RRL need not be provided. It is. The surrounding insulating films 116 are shown as an integral part regardless of the difference in the forming process. The fact that they are integrally shown does not mean that they are formed at the same time, but they are actually a laminated structure as in FIGS. 6 and 7. If the substrate is made of ceramic, a micro-relay sealed between glass can be assembled before sintering and sintered at low temperature to produce a substrate containing the relay.

As is apparent from a comparison of FIGS. 11 and 12 with FIGS. 6 and 7, the magnetic switch of the embodiment of FIG. 6 is the magnetic switch of FIG. 6, and the magnetic switch of FIG. It has a similar configuration to the magnetic switch of FIG.

The difference between the magnetic switches shown in FIGS. 11 and 12 and the magnetic switches shown in FIGS. 6 and 7 is that in FIGS. 11 and 12, the internal wirings 114a and 114b Instead of not providing the ferromagnetic pieces MG 1 and MG 2 at the tip, a ferromagnetic piece MGP is provided on the upper wall or side wall of the void 1 1 18 inside the insulator layer 1 16 where the magnetic switch is formed, The on / off state of the switch is set depending on whether or not the ferromagnetic piece MGP has a magnetic pole.

In this embodiment, at least one of the internal wirings 114a and 114b (on the side far from the ferromagnetic piece MGP) is formed of a conductive magnetic material. In such a configuration, when the ferromagnetic piece MGP is provided with a magnetic pole, the internal wirings 114a and 114b are drawn to the ferromagnetic piece MGP and come into contact with the ferromagnetic piece MGP by the same principle as that of the reed switch. As a result, the conductive state is established. A ferromagnetic piece MGP is provided on the upper wall or side wall of the empty space 1 18, and the internal wirings 1 14 a and 1 14 b are formed of a non-magnetic material, and a magnetic material layer is formed at one of the tips. May be provided.

When the magnetic switch of the embodiment shown in FIG. 11 or FIG. 12 is used as the cross point switch circuit 114 provided on the substrate 110 shown in FIG. 3, any one of the switches SW1 to SW6 is turned on. As a method of setting the state, for example, there is a method using a device having a magnetic head as shown in FIG. In addition, as a method of returning the switches SW1 to SW6 to the off state, there are a method of heating the substrate 110 to one or more curies of the material of the ferromagnetic material piece MGP to erase the magnetic pole of the ferromagnetic material piece MGP, and a method of removing the magnetic pole of the ferromagnetic piece MGP. There is a method of erasing by applying an alternating magnetic field to the whole. When the ferromagnetic piece MGP is demagnetized, the magnetic switch returns to its original state by returning to its original state due to the elasticity of the internal wirings 114a and 114b.

The device shown in FIG. 13 includes a magnetic head MH and a control device CPC for controlling the magnetic head MH. The magnetic head MH is brought close to one of the magnetic switches on the substrate 110 which is to be turned on. Then, a current is passed through the head to generate lines of magnetic force to magnetize the ferromagnetic piece MGP.

At this time, the positioning of the head is performed for the positioning provided on the substrate 110. If the mark MK is used to determine the position of the head by using it as the base point, accurate positioning can be easily performed. Further, the head may be moved by controlling a motor for moving the arm holding the head in the X direction and a motor for moving the head in the Y direction (both not shown). An XY stage that can move in the X and Y directions may be used as the table to be placed. In this way, the on / off state of the magnetic switch is set.

FIG. 14 shows an application system having an analog circuit as an example of a system suitable for applying the multichip module of the present invention. This application system, along with the CPU, SRAM, and MMU, processes read signals from the medium and generates write signals in a PRML (partial, response, maximum, like-like) format in magnetic storage such as a hard disk. A / D conversion circuits A / C and D / A conversion circuits D AC and a digital / signal / processor DSP for performing operations for processing analog signals are implemented as separate semiconductor integrated circuits on separate semiconductor chips. Each chip was housed in one package case, and a substrate as shown in Fig. 2 or Fig. 3 having a grid-like wiring 113 and a cross-point switch circuit 114 was joined to form a module. Things.

As shown in Fig. 14, the PRML circuit uses an automatic gain control amplifier 321 to amplify the read signal from the read magnetic head 311 and a noise frequency from the amplified signal. A filter circuit 3 2 2 for removing components, an AD conversion circuit 3 2 3 (AD C) for AD-converting a read signal, and decrypting read data that has been encrypted and stored or encrypting write data Cryptographic processing circuit 3 2 4 (DEQ), Encoder & decoder 3 25 that encodes write data and decodes read data, and signal processing that performs signal processing such as converting write data to analog signals Necessary for the operation of the circuit 3 2 6, the write amplifier 3 2 7 that drives the magnetic head 3 12 for writing, the AD conversion circuit 3 2 3 (AD C) and the encryption processing circuit 3 2 4 (DEQ) PLL that generates the clock signal Locked loop) The circuit consists of 3 2 8 etc.

In the system shown in Fig. 14, the circuit block of the PRML type circuit, the cryptographic processing circuit 324 (DEQ), and the DA conversion of the encoder & decoder 325 and the signal processing circuit 326 The functions of the circuit except for the circuit can be realized by a digital signal processor DSP.

Furthermore, in the system of this application example, a DA converter circuit 411 and an AD converter circuit 4 12 for testing the filter circuit 3 2 and an analog signal for testing the AD converter circuit 3 2 3 are generated. DA converter circuit 4 13, signal processing circuit 3 2 6 Test AD converter circuit 4 14 for measuring analog output voltage, FFT (fast Fourier transform) circuit 4 15 for frequency analysis, etc. Is provided. In recent years, PRML circuits are often configured as a system LSI on one semiconductor chip. In that case, to test whether analog circuits such as the DA conversion circuit 411 and the AD conversion circuit 412 have the desired characteristics, it is necessary to provide signal lines and pads for extracting output signals outside the chip. However, if a signal line is provided for testing an analog circuit, there is a problem that the characteristics of the circuit are changed by the signal line. On the other hand, as described above, by applying the present invention to configure a multi-chip module, a device that conventionally could only test the entire PRML circuit, The test can be performed with a smaller unit of circuit as a target. Moreover, when the present invention is applied, if the ON / OFF state of each of the switches SW1 to SW6 of the cross point switch circuit 114 provided on the substrate 110 is reset, the connection between the chips can be changed. For example, if the AD converter circuit 3 23 is tested and found to have desired characteristics, the AD converter circuit 3 23 is used to test the filter 3 22 and the signal processing circuit 3 26. There is an advantage that it becomes possible.

When testing such an analog circuit, it is desirable to use a read-type magnetic switch as shown in FIGS. 6 and 7, FIGS. 11 and 12. FIG. In a switch circuit using MOSFET as shown in Fig. 8, the signal level This is because logic down does not cause a problem in a logic test that determines "1" or "0", but is not suitable for transmitting analog signals.

Next, an example of a test method of the multi-chip module of FIG. 1 to which the present invention is applied will be described with reference to FIG.

In the test of the multi-chip module of FIG. 1, first, it is checked whether the FPGA 250 operates normally, and it is determined whether or not there is a defect. If there is a defect, the defect is avoided (step S). 1 to S 3). Next, a test circuit (AL PG) for testing the SRAM 250 is constructed in the portion of the FPGA 250 excluding the above-mentioned defective part, and the FPGA 250 is connected to the SRAM 220 After the setting of the cross point switch circuit 114 is performed, the tests of the SRAM 220 are sequentially executed (steps S4 and S5).

If no defect is found in the SRAM 220, a test circuit for testing the custom logic circuit 240 and the CPU 210 in the portion of the FPGA 250 excluding the defect described above ( Logic tester) is constructed, and the cross-point switch circuit 114 is set to connect the FPGA 250 to the custom logic circuit 240 and the CPU 210, and then the custom logic circuit 240 is set. Then, the CPU 210 test is executed (steps S6 to S8). At this time, a test pattern or a test pattern generation program is stored using the SRAM 220 that has already been inspected.

If no defect is found, a test circuit (AL PG) for testing the DRAM 230 is constructed in the portion of the FPGA 250 excluding the above-mentioned defective portion, and the FPGA 250 and the After setting the cross point switch circuit 114 so as to connect the DRAM 230, the DRAM 230 test is executed sequentially (steps S9, S10). When a defective portion is found, the defective address is stored in the SRAM 220 or an external storage device, and then the defective bit is determined by using a redundant circuit provided in the DRAM 230. A rescue program for rescue is read into the CPU 210, and the crosspoint switch circuit 114 is set so as to connect the CPU 210 and the DRAM 230. After that, the program is executed by the CPU 210 to perform bit relief (steps S11 and S12).

After that, for non-defective products, a part of the custom logic such as user logic is configured in the portion excluding the defective part in the FPGA 250 (step S13), and the crossover is performed so as to configure the original system. The point switch circuit 114 is reset, and the chips are connected so as to form a legitimate system to complete a multichip module (step S14). After constructing the normal system of the multichip module, a test is performed to determine whether or not the system operates normally, and those that are determined to be normal are shipped as non-defective products (steps S15 and S16). In step S13, the data that constitutes the user logic so as to avoid the defect using the information indicating the defect obtained in step S1 is stored in the FPGA 250. The desired logic is formed by writing to the connection information storage memory cell.

Through the above procedure, each chip constituting the multi-chip module is tested and a multi-chip module having a desired function is constructed. According to this embodiment, the test of other chips such as RAM 220, DRAM 230, and CPU 210 is executed by a test circuit configured to avoid a defective portion in the FPGA 250. Therefore, highly reliable test results can be obtained without using a sophisticated external tester.

Further, when a chip having an irreparable defect is detected, the chip may be replaced with another equivalent chip, thereby improving the yield. And F

After completing the self-test by the test circuit configured in the PGA250, the custom logic is configured in the FPGA250, eliminating unnecessary chips and installing a test circuit. Large size can be suppressed.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and it is needless to say that various modifications can be made without departing from the gist of the invention. Nor.

For example, in the above embodiment, the intersections of the grid-like wiring 1 13 and each wiring A cross-point switch circuit 114 is provided in the circuit board to configure a system that can be configured as desired.However, a test circuit can be configured by connecting the chips housed in the package case 100 or a module. The circuit may be configured as a board dedicated to each module provided with only the wiring that can be switched to one of the original systems and the cross point switch circuit 114.

By using the substrate as described in the above embodiment, although unnecessary wiring and elements are generated, a versatile substrate that can be used for a plurality of multi-chip modules having different system configurations can be obtained. There is an advantage that the cost can be reduced and the substrate can be provided to the market as an independent product. On the other hand, when the board is configured as a board for a specific module as described above, it is possible to design the module in accordance with the size of the module, to reduce the size of the module, and to use unnecessary wiring and Since the number of elements is significantly reduced, the cost can be lower than that of the above-mentioned general-purpose substrate depending on the number of manufactured elements.

Further, the substrate having the cross-point switch circuit provided at the intersection of the lattice-shaped wiring and the wiring in the above-described embodiment can be used as an aging board for mounting a semiconductor chip to be tested in a test device such as aging. In addition, by mounting a semiconductor chip that constitutes the test circuit in addition to the semiconductor chip under test, the test can be executed simultaneously with the aging test, reducing the burden on the tester. In addition to the reduction, testing with a simple tester becomes possible. In addition, when the semiconductor chip to be tested is a memory by using the above substrate, a method already proposed by the present inventors (International Publication WO01-37285), etc. This makes it possible to configure a test circuit with any memory on the substrate and test another memory with the test circuit.

Also, instead of configuring a test circuit with any of the memories on the board and testing other memories with the test circuit, the terminals of any of the chips can be connected to the wiring and cross point switch circuit on the board. It is also possible to pull out the module through the module and perform a test for each chip with an external tester. Test the entire system In order to increase the failure detection rate, a huge number of test patterns are required. However, if the test is performed for each chip, the number of test patterns is much smaller and the test time is reduced. Industrial applicability

In the above description, the case where the present invention is applied to a multi-chip module of a type accommodated in a package case and a substrate as a cap, which is a field of application, which is the background of the invention made by the present inventors, has been described. However, the present invention can also be used for electronic devices configured on a printed wiring board such as a memory module.

Claims

The scope of the claims

1. Wiring electrically connected to a plurality of semiconductor chips, an insulating substrate provided with a wiring path switching means provided at an intersection of the wiring and capable of connecting arbitrary wiring, and mounted on the insulating substrate And a plurality of semiconductor chips connected to each other by the wiring and the wiring connection switching means.

2. A package case capable of holding a plurality of semiconductor chips, wherein the package case and the insulating substrate are joined while the semiconductor chip is held in the package case. Multi-chip half described in

3. The wiring includes a regular wiring that connects the plurality of semiconductor chips to form a desired system and a test wiring that transmits a signal for testing any one of the semiconductor chips. 3. The multi-chip semiconductor device according to claim 1, wherein

4. The multi-chip semiconductor device according to claim 3, wherein the wirings are arranged in a grid pattern on or inside the insulating substrate.

5. The insulating substrate is formed of a low dielectric constant material, and the wiring path switching means includes: a pair of lead-shaped wirings whose free ends are opposed to each other at a predetermined interval; Alternatively, the element is composed of a magnetic piece provided in the vicinity of the element and configured to be able to set a signal conduction or cutoff state depending on whether the magnetic piece has a magnetic pole. Item 5. The multi-chip semiconductor device according to any one of Items 1 to 4.

6. The insulating substrate is formed of a semiconductor crystal, and the wiring path switching means is a semiconductor. 5. The multi-chip semiconductor device according to claim 1, wherein the non-volatile memory element has a control gate and a floating gate formed in a body crystal.

7. The wiring path switching means is composed of two nonvolatile memory elements connected in series, and one of the two nonvolatile memory elements is arranged such that its control terminals cross each other. The first selection line and the second selection line are connected to the first selection line, and the control terminals of the other nonvolatile memory elements are connected to the second selection line. 7. The multi-chip semiconductor device according to claim 6, wherein:

8. Wiring to be electrically connected to the semiconductor chip. A desired system can be configured on an insulating substrate provided with wiring path switching means provided at the intersection of the wiring and connecting arbitrary wirings. After mounting a plurality of semiconductor chips and testing the semiconductor chips by setting the wiring path switching means so that any one of the semiconductor chips can be tested, the other semiconductor chips can be tested. The wiring path switching means is switched to test the other semiconductor chip, and after the test for each semiconductor chip is completed, the wiring path switching means is switched again to set a wiring path so as to configure the desired system. A method for testing a multi-chip semiconductor device.

9. One of the plurality of semiconductor chips is a semiconductor chip for outputting an analog signal, and the analog signal output from the semiconductor chip is transmitted to the test circuit via the wiring and the wiring path switching means. 9. The test method for a multi-chip semiconductor device according to claim 8, wherein the test is performed by supplying the test data to a semiconductor device.

10. One of the plurality of semiconductor chips is a first semiconductor chip that outputs an analog signal, and one of the other semiconductor chips is a second semiconductor chip that can input an analog signal. A second semiconductor chip or the second semiconductor chip and the second semiconductor chip A test circuit is configured with a semiconductor chip other than the first semiconductor chip, and the wiring path switching means is set so that the analog signal output from the first semiconductor chip is input to the second semiconductor chip. 10. The method for testing a multi-chip semiconductor device according to claim 9, wherein the evaluation is performed by the test circuit.

11. A plurality of semiconductor chips electrically connectable to a terminal portion, a plurality of wires including wires arranged to intersect with each other and connected to the terminal portion, and an arbitrary portion provided at an intersection of the wires. What is claimed is: 1. A system substrate, comprising: wiring route switching means for connecting wirings.

12. The wiring path switching means includes: a pair of lead-shaped wirings whose free ends are opposed to each other at a predetermined interval; and a magnetic piece provided at or near the tip of the lead-shaped wiring. 21. The system substrate according to claim 11, wherein the element is a device configured to be able to set an on / off state of a switch depending on whether or not the magnetic piece has a magnetic pole.

13. The leading end of the lead-shaped wiring is projected into a space formed in the insulating layer, and is arranged so as to face the leading end of another lead-shaped wiring in the space. 13. The system substrate according to claim 12, wherein:

14. The system substrate according to any one of claims 11 to 13, wherein the wirings are arranged in a grid.

15. An insulating film for insulating the wiring is made of a material having a lower dielectric constant than an insulating film formed on a surface of the semiconductor chip to be mounted. 4. The system substrate according to any one of 4.