WO1999059206A3 - Semiconductor device and method for making the device - Google Patents

Semiconductor device and method for making the device Download PDF

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Publication number
WO1999059206A3
WO1999059206A3 PCT/IB1999/000818 IB9900818W WO9959206A3 WO 1999059206 A3 WO1999059206 A3 WO 1999059206A3 IB 9900818 W IB9900818 W IB 9900818W WO 9959206 A3 WO9959206 A3 WO 9959206A3
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
making
semiconductor device
interconnected
top surface
Prior art date
Application number
PCT/IB1999/000818
Other languages
French (fr)
Other versions
WO1999059206A2 (en
Inventor
Veen Nicolaas J A Van
Antonius J M Nellissen
Samber Marc A De
Original Assignee
Koninkl Philips Electronics Nv
Philips Svenska Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Philips Svenska Ab filed Critical Koninkl Philips Electronics Nv
Priority to JP2000548921A priority Critical patent/JP2002515651A/en
Priority to KR1020007000345A priority patent/KR20010021782A/en
Publication of WO1999059206A2 publication Critical patent/WO1999059206A2/en
Publication of WO1999059206A3 publication Critical patent/WO1999059206A3/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A semiconductor device comprises a first substrate (10) whose top surface is provided with interconnected conductor patterns (31, 32 and 33), side faces and bottom surface. A second substrate (40) having an electric circuit (41) and connection pads (43) at a connection side (47) is mounted on the first substrate (10) with the connection side (47) facing the top surface (11) of the first substrate (10). The connection pads (43) and the first conductor pattern (31) are interconnected by means of solder bumps (45) which are located between the substrate (40) and the substrate (10).
PCT/IB1999/000818 1998-05-13 1999-05-06 Semiconductor device and method for making the device WO1999059206A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2000548921A JP2002515651A (en) 1998-05-13 1999-05-06 Semiconductor device and method of manufacturing semiconductor device
KR1020007000345A KR20010021782A (en) 1998-05-13 1999-05-06 Semiconductor device and method for making the device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP98201564.6 1998-05-13
EP98201564 1998-05-13

Publications (2)

Publication Number Publication Date
WO1999059206A2 WO1999059206A2 (en) 1999-11-18
WO1999059206A3 true WO1999059206A3 (en) 2000-02-24

Family

ID=8233715

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB1999/000818 WO1999059206A2 (en) 1998-05-13 1999-05-06 Semiconductor device and method for making the device

Country Status (3)

Country Link
JP (1) JP2002515651A (en)
KR (1) KR20010021782A (en)
WO (1) WO1999059206A2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2794570B1 (en) * 1999-06-04 2003-07-18 Gemplus Card Int METHOD FOR MANUFACTURING PORTABLE DEVICE WITH INTEGRATED CIRCUIT WITH ELECTRICAL CONDUCTION PATHS
US6507099B1 (en) * 2000-10-20 2003-01-14 Silverbrook Research Pty Ltd Multi-chip integrated circuit carrier
US6710457B1 (en) 2000-10-20 2004-03-23 Silverbrook Research Pty Ltd Integrated circuit carrier
US6775906B1 (en) 2000-10-20 2004-08-17 Silverbrook Research Pty Ltd Method of manufacturing an integrated circuit carrier
US6876008B2 (en) 2003-07-31 2005-04-05 Lumileds Lighting U.S., Llc Mount for semiconductor light emitting device
US6995402B2 (en) 2003-10-03 2006-02-07 Lumileds Lighting, U.S., Llc Integrated reflector cup for a light emitting device mount

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0343720A2 (en) * 1988-05-23 1989-11-29 Koninklijke Philips Electronics N.V. Semiconductor wafer and method of dividing it
EP0465196A2 (en) * 1990-07-02 1992-01-08 General Electric Company Compact high density interconnect structure
US5285571A (en) * 1992-10-13 1994-02-15 General Electric Company Method for extending an electrical conductor over an edge of an HDI substrate
US5466634A (en) * 1994-12-20 1995-11-14 International Business Machines Corporation Electronic modules with interconnected surface metallization layers and fabrication methods therefore
US5471090A (en) * 1993-03-08 1995-11-28 International Business Machines Corporation Electronic structures having a joining geometry providing reduced capacitive loading
US5648684A (en) * 1995-07-26 1997-07-15 International Business Machines Corporation Endcap chip with conductive, monolithic L-connect for multichip stack
US5657537A (en) * 1995-05-30 1997-08-19 General Electric Company Method for fabricating a stack of two dimensional circuit modules

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0343720A2 (en) * 1988-05-23 1989-11-29 Koninklijke Philips Electronics N.V. Semiconductor wafer and method of dividing it
EP0465196A2 (en) * 1990-07-02 1992-01-08 General Electric Company Compact high density interconnect structure
US5285571A (en) * 1992-10-13 1994-02-15 General Electric Company Method for extending an electrical conductor over an edge of an HDI substrate
US5471090A (en) * 1993-03-08 1995-11-28 International Business Machines Corporation Electronic structures having a joining geometry providing reduced capacitive loading
US5466634A (en) * 1994-12-20 1995-11-14 International Business Machines Corporation Electronic modules with interconnected surface metallization layers and fabrication methods therefore
US5657537A (en) * 1995-05-30 1997-08-19 General Electric Company Method for fabricating a stack of two dimensional circuit modules
US5648684A (en) * 1995-07-26 1997-07-15 International Business Machines Corporation Endcap chip with conductive, monolithic L-connect for multichip stack

Also Published As

Publication number Publication date
KR20010021782A (en) 2001-03-15
JP2002515651A (en) 2002-05-28
WO1999059206A2 (en) 1999-11-18

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