US8117494B2 - DMI redundancy in multiple processor computer systems - Google Patents
DMI redundancy in multiple processor computer systems Download PDFInfo
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- US8117494B2 US8117494B2 US12/644,540 US64454009A US8117494B2 US 8117494 B2 US8117494 B2 US 8117494B2 US 64454009 A US64454009 A US 64454009A US 8117494 B2 US8117494 B2 US 8117494B2
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- instability
- management interface
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1417—Boot up procedures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
- G06F11/2023—Failover techniques
- G06F11/2025—Failover techniques using centralised failover control functionality
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
- G06F11/2023—Failover techniques
- G06F11/2028—Failover techniques eliminating a faulty processor or activating a spare
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
- G06F11/2038—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant with a single idle spare processing component
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
- G06F11/2043—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant where the redundant components share a common memory address space
Definitions
- This disclosure relates generally to the field of multiple processor computer platforms, and more particularly to an apparatus, system and method for desktop management interface (DMI) redundancy in a multiple processor computer system.
- DMI desktop management interface
- Computer systems can have a single (unitary) processor (UP) or multiple processor configuration.
- One type of multiple processor configuration is a dual processor (DP) configuration.
- DP dual processor
- a multiple processor configuration typically one of the processor is designated a boot processor, whereby when the computer system is booted, the boot processor is the only processor involved in the boot process. If the boot processor fails to boot the computer system, the computer is typically non-function unless other measures are taken. What is needed is multiple processor computer system that is enabled to determine if the boot processor is functioning properly, and if not, designating another processor to be the boot processor.
- FIG. 1 shows an example related processor topology.
- FIG. 2 shows an example of a multiple processor platform having a dual processor (DP) topology in accordance with various aspects of the present disclosure.
- FIG. 3 shows another example of a multiple processor platform having quad processor topology in accordance with various aspects of the present disclosure.
- FIG. 4 shows an example flowchart for switching from a DP to DP architecture in accordance with various aspects of the present disclosure.
- FIG. 5 shows an example flowchart for switching from a DP to a unitary processor (UP) architecture in accordance with various aspects of the present disclosure.
- a method comprises aspects of monitoring a first processor of a computer by a monitoring module for a first processor instability; determining if the first processor is stable based on the monitored first processor instability; routing operational priority to a second processor of the computer through a multiplexer module if the first processor is determined not to be stable, wherein a first desktop management interface of the first processor and a second desktop management interface of the second processor are in communication with the multiplexer module and wherein the first processor and the second processor are in communication by a processor interconnect; and operating the computer using the second processor.
- an apparatus comprises aspects of a first processor; a second processor configured to be in communication with the first processor through an interconnect; and a multiplexer configured to multiplex a first desktop management interface of the first processor and a second desktop management interface of the second processor into a platform controller hub.
- an apparatus comprises aspects of a computer including a board, the board including a first processor; a second processor configured to be in communication with the first processor through an interconnect; and a multiplexer configured to multiplex a first desktop management interface of the first processor and a second desktop management interface of the second processor connected to a platform controller hub.
- FIG. 1 shows an example related processor topology.
- Two processors, 105 and 110 are connected through an interconnect, such as a point-to-point processor interconnect like QuickPath Interconnect (QPI) by Intel.
- a Desktop Management Interface (DMI) of processor 105 is connected to a Platform Control HUB (PCH) 115 , while a DMI of processor 110 is unused.
- PCH Platform Control HUB
- a PCH also known as an I/O Controller Hub (ICH) or Southbridge, is a chip that implements the “slower” capabilities of the motherboard (not shown) in a northbridge/southbridge chipset computer architecture.
- ICH I/O Controller Hub
- Southbridge is a chip that implements the “slower” capabilities of the motherboard (not shown) in a northbridge/southbridge chipset computer architecture.
- the southbridge can be distinguished from the northbridge by not being directly connected to the CPU. Rather, the northbridge ties the southbridge to the CPU. Through the use of controller
- the processors can be route-through enabled processors. Route-through is a packet routing mechanism within the uncore of certain processors.
- the term “uncore” refers to components of a multi-core chip other than the cores (e.g., the interconnect for the cores, the bus interfaces, etc.). Changes in the internal blocks (CSI home logic, Source Address Decode Blocks, Global Queue, etc) are used to determine the destination of the packets. Instead of processing the packet at each node, the destination node is determined and either ‘route through’ or process based on the destination address.
- FIG. 2 shows an example of a multiple processor platform having a dual processor (DP) topology in accordance with various aspects of the present disclosure.
- two processors, 205 and 210 can be connected through an interconnect, such as a point-to-point processor interconnect.
- the point-to-point interconnect can be a QPI; however, other suitable processor interconnects may be used.
- processors 205 and 210 are both route-through enabled processors; however, this is merely an example platform configuration. The processors need not be route-through enabled.
- one of the two processor 205 or 210 can be selected to be a boot processor.
- a DMI of processor 205 and a DMI of processor 210 can be connected to inputs of multiplexer MUX 215 .
- a monitor 220 can be in communication with MUX 215 and can be configured to monitor a condition of the boot processor.
- a controller 230 can in communication with the monitor 220 , MUX 215 or both and be configured to instruct the MUX 215 to designate the non-boot processor to be the boot processor based on the conditioned monitored by the monitor 220 .
- the output of MUX 215 can be in communication with a PCH 225 .
- FIG. 3 shows another example of a multiple processor platform having quad processor topology in accordance with various aspects of the present disclosure.
- four processors, 305 , 310 , 315 and 320 can be connected through an interconnect, such as a point-to-point processor interconnect.
- the point-to-point interconnect can be a QPI; however, other suitable processor interconnects may be used.
- processors 305 , 310 , 315 and 320 are route-through enabled processors; however, this is merely an example platform configuration. The processors need not be route-through enabled.
- one of the four processor 205 or 210 can be selected to be a boot processor.
- DMI of processors 305 , 310 , 315 and 320 can be connected to inputs of multiplexer MUX 325 .
- a monitor 320 can be in communication with MUX 315 and can be configured to monitor a condition of the boot processor.
- a controller 340 can in communication with the monitor 320 , MUX 315 or both and be configured to instruct the MUX 315 to designate a non-boot processor to be the boot processor based on the conditioned monitored by the monitor 320 .
- Output of MUX 325 can be in communication with a PCH 335 .
- the monitor 220 , 320 can be a timer, a watchdog timer or a baseboard management controller, or a discrete state machine.
- a watchdog timer can be a computer hardware timing device that is configured to trigger a system reset if the boot processor, due to some fault condition, such as a hang or freeze, neglects to regularly service the watchdog.
- a hang or freeze occurs when either the boot processor, a computer program or the whole system becomes unresponsive to user input.
- Hardware can cause a computer to hang, either because it is intermittent or because it is mismatched with other hardware in the computer. Also, hardware can also become defective over time due to dirt or heat damage.
- the watchdog can be tied directly to the MUX 215 , 315 or to the controller 230 , 340 or both.
- the monitor 220 , 320 can be a baseboard management controller (BMC).
- BMC is a specialized microcontroller embedded on the motherboard of a computer.
- the BMC is the intelligence in the Intelligent Platform Management Interface (IPMI) architecture.
- IPMI Intelligent Platform Management Interface
- the BMC manages the interface between system management software and platform hardware. Different types of sensors built into the computer system report to the BMC on parameters such as temperature, cooling fan speeds, power mode, operating system (OS) status, etc.
- the BMC monitors the sensors and can send alerts to the MUX 215 , 315 or to the controller 230 , 340 or both if any of the parameters do not stay within preset limits, including a potential failure of the system.
- a user of the computer can also communicate with the BMC to take some corrective action such as resetting or power cycling the system to get a hung OS running again.
- Physical interfaces to the BMC can include SMBus busses, an RS-232 serial console, address and data lines and an Intelligent Platform Bus (IPMB), that enables the BMC to accept IPMI request messages from other management controllers in the system.
- IPMB Intelligent Platform Bus
- the monitor 220 , 320 can be configured to monitor and determine whether the system is stable by monitoring for various system instabilities.
- a system instability can include whether or not the designated boot processor is able to boot properly.
- Other system instabilities can include whether the system is able to remain stable for a specific duration of time, such as on the order of minutes, days or weeks.
- the determination can be performed in a variety of manners. For example, system instability can be determined manually by a user/operation by observation of the system, using hardware and/or software implemented watchdog timers, or managed through system level logging of performance data.
- Other parameters can include a determination that the system is running slower as compared to a desired state, electrical instability, too memory errors for the boot processor, or too many errors on DMI or other platform interfaces local to one or more processors.
- the boot processor configuration can be accomplished on an architecture by architecture basis. For example, various strapping options, such as combinations of inputs on the processor set in a pre-determined fashion used to provide directives to the processor to configure itself when it comes out of reset. The strapping options could be controlled by a PLD, FPGA, a manual switch, or from another logic device on the platform. In some aspects, the boot processor can be disabled on an architecture specific basis.
- the MUX can be configured in several ways.
- the MUX can be configured by PCH integrated Manageability Engine, onboard BMC, manually through a user interface on the front panel or through field-programmable gate array (FPGA) or a complex programmable logic device (CPLD).
- PCH integrated Manageability Engine onboard BMC
- FPGA field-programmable gate array
- CPLD complex programmable logic device
- FIG. 4 shows an example flowchart for switching from a DP to DP architecture in accordance with various aspects of the present disclosure.
- the process begins at 405 where the monitor 220 , 330 is configured to detect a condition, such as instabilities in the operational status of the processors. If no instability is detected, the process loop back to 405 , where a detected instability leads to 410 .
- the platform is powered down and the MUX reroutes DMI from socket 0 to socket 1 .
- the processor in socket 1 is then configured to be the boot processor.
- the system is reboot in DP mode, where the platform is booted using the rerouted processor in socket 1 .
- FIG. 5 shows an example flowchart for switching from a DP to a unitary processor (UP) architecture in accordance with various aspects of the present disclosure.
- the process begins at 505 where the monitor 220 , 330 is configured to detect a condition, such as instabilities in the operational status of the processors. If no instability is detected, the process loop back to 505 , where a detected instability leads to 510 .
- the platform is powered down and the MUX reroutes DMI from socket 0 to socket 1 .
- the processor in socket 1 is then configured to be the boot or legacy processor and the processor in socket 0 is disabled.
- the system is reboot in UP mode, where the platform is booted using the rerouted processor in socket 1 .
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Abstract
Description
Claims (20)
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
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US12/644,540 US8117494B2 (en) | 2009-12-22 | 2009-12-22 | DMI redundancy in multiple processor computer systems |
TW099139986A TWI526822B (en) | 2009-12-22 | 2010-11-19 | Method and apparatus for dmi redundancy in multiple processor computer systems |
JP2010262354A JP5296036B2 (en) | 2009-12-22 | 2010-11-25 | DMI redundancy in multiprocessor computer systems |
PCT/US2010/058243 WO2011087594A2 (en) | 2009-12-22 | 2010-11-29 | Dmi redundancy in multiple processor computer systems |
EP10252158A EP2348414A3 (en) | 2009-12-22 | 2010-12-17 | Desktop Management Interface redundancy in multiple processor computer systems |
CN201010620079.XA CN102110035B (en) | 2009-12-22 | 2010-12-21 | DMI redundancy in multiple processor computer systems |
US13/356,054 US8527808B2 (en) | 2009-12-22 | 2012-01-23 | DMI redundancy in multiple processor computer systems |
US13/954,266 US8943360B2 (en) | 2009-12-22 | 2013-07-30 | DMI redundancy in multiple processor computer systems |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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US12/644,540 US8117494B2 (en) | 2009-12-22 | 2009-12-22 | DMI redundancy in multiple processor computer systems |
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US13/356,054 Continuation US8527808B2 (en) | 2009-12-22 | 2012-01-23 | DMI redundancy in multiple processor computer systems |
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US20110154106A1 US20110154106A1 (en) | 2011-06-23 |
US8117494B2 true US8117494B2 (en) | 2012-02-14 |
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US12/644,540 Expired - Fee Related US8117494B2 (en) | 2009-12-22 | 2009-12-22 | DMI redundancy in multiple processor computer systems |
US13/356,054 Active US8527808B2 (en) | 2009-12-22 | 2012-01-23 | DMI redundancy in multiple processor computer systems |
US13/954,266 Active US8943360B2 (en) | 2009-12-22 | 2013-07-30 | DMI redundancy in multiple processor computer systems |
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US13/356,054 Active US8527808B2 (en) | 2009-12-22 | 2012-01-23 | DMI redundancy in multiple processor computer systems |
US13/954,266 Active US8943360B2 (en) | 2009-12-22 | 2013-07-30 | DMI redundancy in multiple processor computer systems |
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US (3) | US8117494B2 (en) |
EP (1) | EP2348414A3 (en) |
JP (1) | JP5296036B2 (en) |
CN (1) | CN102110035B (en) |
TW (1) | TWI526822B (en) |
WO (1) | WO2011087594A2 (en) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201218075A (en) * | 2010-10-20 | 2012-05-01 | Hon Hai Prec Ind Co Ltd | Dual processor startup system |
CN102955136A (en) * | 2011-08-18 | 2013-03-06 | 鸿富锦精密工业(深圳)有限公司 | Assistant detection circuit and assistant detection method for redundant power sources |
JP5561622B2 (en) | 2011-09-27 | 2014-07-30 | 日本電気株式会社 | Multiplexing system, data communication card, state abnormality detection method, and program |
TW201321943A (en) * | 2011-11-17 | 2013-06-01 | Hon Hai Prec Ind Co Ltd | Fan control system and method |
CN103164234A (en) * | 2011-12-13 | 2013-06-19 | 鸿富锦精密工业(深圳)有限公司 | Dual processor shifting device |
TW201405303A (en) * | 2012-07-30 | 2014-02-01 | Hon Hai Prec Ind Co Ltd | System and method for monitoring baseboard management controller |
WO2015042925A1 (en) * | 2013-09-29 | 2015-04-02 | 华为技术有限公司 | Server control method and server control device |
US9811491B2 (en) | 2015-04-07 | 2017-11-07 | Lenovo Enterprise Solutions (Singapore) Pte. Ltd. | Minimizing thermal impacts of local-access PCI devices |
WO2018076351A1 (en) * | 2016-10-31 | 2018-05-03 | 华为技术有限公司 | Method and enabling device for starting physical device |
CN109670319B (en) * | 2018-12-25 | 2022-04-15 | 广东浪潮大数据研究有限公司 | Server flash safety management method and system thereof |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5574929A (en) * | 1993-06-23 | 1996-11-12 | Koninklijke Ptt Nederland N.V. | Processor circuit comprising a first processor, a memory and a peripheral circuit, and system comprising the processor circuit and a second processor |
US20060106958A1 (en) | 2004-11-13 | 2006-05-18 | Motorola, Inc. | Efficient multiprocessor system and methods thereof |
US20060136915A1 (en) | 2004-12-17 | 2006-06-22 | Sun Microsystems, Inc. | Method and apparatus for scheduling multiple threads for execution in a shared microprocessor pipeline |
US20090254698A1 (en) * | 2008-02-27 | 2009-10-08 | Samsung Electronics Co., Ltd. | Multi port memory device with shared memory area using latch type memory cells and driving method |
US20090259884A1 (en) * | 2008-04-11 | 2009-10-15 | International Business Machines Corporation | Cost-reduced redundant service processor configuration |
US20110026411A1 (en) * | 2009-07-29 | 2011-02-03 | Lijing Hao | Methods and systems for fail-safe communication |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02130666A (en) * | 1988-11-11 | 1990-05-18 | Pfu Ltd | System reconstituting system for multiprocessor system |
US5491788A (en) * | 1993-09-10 | 1996-02-13 | Compaq Computer Corp. | Method of booting a multiprocessor computer where execution is transferring from a first processor to a second processor based on the first processor having had a critical error |
KR100518478B1 (en) * | 1997-06-23 | 2005-10-05 | 코닌클리케 필립스 일렉트로닉스 엔.브이. | Slave DSP reboots stalled master CPU |
US6687818B1 (en) * | 1999-07-28 | 2004-02-03 | Unisys Corporation | Method and apparatus for initiating execution of an application processor in a clustered multiprocessor system |
US20020178262A1 (en) * | 2001-05-22 | 2002-11-28 | David Bonnell | System and method for dynamic load balancing |
US7251723B2 (en) * | 2001-06-19 | 2007-07-31 | Intel Corporation | Fault resilient booting for multiprocessor system using appliance server management |
US20050066218A1 (en) * | 2003-09-24 | 2005-03-24 | Stachura Thomas L. | Method and apparatus for alert failover |
US7366948B2 (en) * | 2004-10-25 | 2008-04-29 | Hewlett-Packard Development Company, L.P. | System and method for maintaining in a multi-processor system a spare processor that is in lockstep for use in recovering from loss of lockstep for another processor |
US7376816B2 (en) | 2004-11-12 | 2008-05-20 | International Business Machines Corporation | Method and systems for executing load instructions that achieve sequential load consistency |
US7965736B2 (en) * | 2005-08-24 | 2011-06-21 | Qualcomm Incorporated | Transmission of multiplex protocol data units in physical layer packets |
JP4701929B2 (en) * | 2005-09-02 | 2011-06-15 | 株式会社日立製作所 | Boot configuration change method, management server, and computer system |
JP4853620B2 (en) * | 2005-12-08 | 2012-01-11 | 日本電気株式会社 | Multiprocessor system and initial startup method and program |
JP2008276320A (en) * | 2007-04-25 | 2008-11-13 | Nec Corp | Virtual system control method and computer system |
US7971098B2 (en) * | 2008-03-24 | 2011-06-28 | Globalfoundries Inc. | Bootstrap device and methods thereof |
-
2009
- 2009-12-22 US US12/644,540 patent/US8117494B2/en not_active Expired - Fee Related
-
2010
- 2010-11-19 TW TW099139986A patent/TWI526822B/en active
- 2010-11-25 JP JP2010262354A patent/JP5296036B2/en not_active Expired - Fee Related
- 2010-11-29 WO PCT/US2010/058243 patent/WO2011087594A2/en active Application Filing
- 2010-12-17 EP EP10252158A patent/EP2348414A3/en not_active Withdrawn
- 2010-12-21 CN CN201010620079.XA patent/CN102110035B/en active Active
-
2012
- 2012-01-23 US US13/356,054 patent/US8527808B2/en active Active
-
2013
- 2013-07-30 US US13/954,266 patent/US8943360B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5574929A (en) * | 1993-06-23 | 1996-11-12 | Koninklijke Ptt Nederland N.V. | Processor circuit comprising a first processor, a memory and a peripheral circuit, and system comprising the processor circuit and a second processor |
US20060106958A1 (en) | 2004-11-13 | 2006-05-18 | Motorola, Inc. | Efficient multiprocessor system and methods thereof |
US20060136915A1 (en) | 2004-12-17 | 2006-06-22 | Sun Microsystems, Inc. | Method and apparatus for scheduling multiple threads for execution in a shared microprocessor pipeline |
US20090254698A1 (en) * | 2008-02-27 | 2009-10-08 | Samsung Electronics Co., Ltd. | Multi port memory device with shared memory area using latch type memory cells and driving method |
US20090259884A1 (en) * | 2008-04-11 | 2009-10-15 | International Business Machines Corporation | Cost-reduced redundant service processor configuration |
US20110026411A1 (en) * | 2009-07-29 | 2011-02-03 | Lijing Hao | Methods and systems for fail-safe communication |
Non-Patent Citations (1)
Title |
---|
International Search Report and Written Opinion mailed Aug. 30, 2011 for PCT/US2010/058243. |
Also Published As
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JP2011134314A (en) | 2011-07-07 |
CN102110035A (en) | 2011-06-29 |
TW201137601A (en) | 2011-11-01 |
WO2011087594A3 (en) | 2011-10-27 |
CN102110035B (en) | 2015-04-08 |
JP5296036B2 (en) | 2013-09-25 |
EP2348414A2 (en) | 2011-07-27 |
US8527808B2 (en) | 2013-09-03 |
TWI526822B (en) | 2016-03-21 |
US8943360B2 (en) | 2015-01-27 |
WO2011087594A2 (en) | 2011-07-21 |
US20110154106A1 (en) | 2011-06-23 |
US20130318337A1 (en) | 2013-11-28 |
EP2348414A3 (en) | 2013-01-16 |
US20120124416A1 (en) | 2012-05-17 |
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