US7361528B2 - Germanium infrared sensor for CMOS imagers - Google Patents

Germanium infrared sensor for CMOS imagers Download PDF

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US7361528B2
US7361528B2 US11/069,422 US6942205A US7361528B2 US 7361528 B2 US7361528 B2 US 7361528B2 US 6942205 A US6942205 A US 6942205A US 7361528 B2 US7361528 B2 US 7361528B2
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germanium
silicon
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Jong-Jan Lee
Jer-shen Maa
Sheng Teng Hsu
Douglas J. Tweet
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Sharp Corp
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    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14634—Assemblies, i.e. Hybrid structures
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    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H01L27/14649—Infrared imagers
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
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    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
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    • H01L27/144—Devices controlled by radiation
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264—Inorganic materials
    • H01L31/028—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
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    • H01L31/103—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PN homojunction type
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    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
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    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • This invention relates to IR sensors, and specifically to fabrication of an IR sensor wherein a germanium thin film is grown on a silicon donor wafer, followed by a bonding and layer transfer process which transfers the germanium layer to another structure.
  • Photo detecting in the near-infrared regime e.g., wavelengths of between about 0.7 ⁇ m to 2 ⁇ m
  • Silicon photodiodes are widely used as photodetectors for the visible light regime because of their low dark current and compatibility with silicon integrated circuit technologies.
  • Attempts have been made to deposit Si 1-x Ge x (SiGe) alloys, or germanium thin films, in silicon to fabricate an IR detector, however, the lattice mismatch in a SiGe-to-silicon boundary limits the maximum SiGe thickness which may be formed while still maintaining a defect free structure.
  • SiGe thin films having a germanium concentration of less than 50% have a relatively low IR absorption coefficient. Hence, it is difficult to fabricate an IR detector on SiGe film which has high sensitivity and low dark current.
  • Germanium has a high IR absorption coefficient, however, a 4% lattice mismatch to silicon results in a high dark current when a germanium photodetector is fabricated by direct deposition of germanium on silicon.
  • a germanium photodetector having a simple PN diode structure exhibiting a very high dark current, e.g., about 30 mA/cm 2 has been fabricated, Colace et al., Efficient high - speed near - infrared Ge photodetectors integrated on Si substrates , Applied Physics Letters, Vol. 76, No. 10, pp 1231-1233 (2000).
  • a germanium thin film bonded to silicon or silicon dioxide has been disclosed, wherein the IR sensor and the driving CMOS circuit are both fabricated on a germanium thin film.
  • High temperature processes are required for germanium IC processes, i.e., ion implantation activation processes are usually performed following an annealing at about 800° C. Such high temperature processes degrade the quality of germanium thin films because the thermal expansion coefficient of silicon, germanium and silicon dioxide are different.
  • a high temperature process performed on a germanium thin film which is bonded to a silicon wafer usually results in defects in the germanium layer(s), as described in U.S. Pat. No. 6,645,831, for Thermally stable crystalline defect - free germanium bonded to silicon and silicon dioxide , granted Nov. 11, 2003 to Shaheen et al. Additionally, germanium IC processes are not as well established in the semiconductor industry as are silicon IC processes.
  • a graded SiGe growth has been demonstrated to form a thick SiGe buffer layer prior to germanium growth, Lee et al., Optimized Strained Si/Strained Ge Dual - channel Heterostructures for High Mobility P ⁇ and N - MOSFETs , IEDM 2003, pp 429-432.
  • Germanium p-MOSFET fabricated on bulk germanium and on epi-germanium has been disclosed by Ritenour et al., Epitaxial Strained Germanium p - MOSFETs with HfO 2 Gate Dielectric and TaN Gate Electrode , IEDM 2003, pp 433-436.
  • a method of fabricating a germanium infrared sensor for a CMOS imager includes preparation of a donor wafer, including; preparation of a silicon wafer; ion implantation into the silicon wafer to form a P+ silicon layer; growing an epitaxial germanium layer on the P+ silicon layer, cyclic annealing the wafer to from a layer of high density of defects on the germanium side of the silicon-germanium interface and to diffuse ions from the P+ silicon layer into the high defect density region of the germanium layer forming a P+ germanium layer; implanting hydrogen ions to a depth at least as deep as the P+ silicon layer to form a defect layer; preparing a handling wafer, including: fabricating a CMOS integrated circuit on the silicon substrate; completing multiple metal interconnects; preparing a silicon substrate; depositing a layer of passivation oxide on the CMOS integrated circuit; planarizing the structure by CMP; forming contact or via holes; removing surface metal by CMP to form metal plugs, smoothing
  • FIG. 1 is a block diagram of the method of the invention.
  • FIGS. 2-5 depicts steps in the method of the invention.
  • the germanium wafer is bonded onto a silicon CMOS wafer, and in this disclosure, a germanium thin film is grown onto a silicon donor wafer, followed by a bonding process.
  • the initial steps in the method of the invention 10 include preparation of what is referred to herein as a donor wafer 12 , including preparation of a conventional silicon wafer 14 .
  • Ion implantation 16 of boron ions into the silicon wafer converts the surface layer of the donor silicon wafer to a P+ material 18 .
  • the doping density is in the order of 1 ⁇ 10 19 cm ⁇ 3 to 1 ⁇ 10 20 cm ⁇ 3 .
  • the next step is epitaxial growth 20 of between about 0.5 ⁇ m to 4.0 ⁇ m of germanium 22 onto the P+ wafer material, followed by cyclic annealing 24 .
  • the range of temperature for the high temperature portion of the cyclic annealing is between about 800° C. to 900° C.
  • the range of temperature in the low temperature portion of the cyclic annealing is between about 700° C. to 850° C.
  • the time interval for each annealing is between about one to ten minutes, and the number of cycles is between about 5 to 50 cycles.
  • a layer 26 of high density of defects is created on the germanium side of the silicon-germanium interface, while the boron simultaneously diffuses from the P+ silicon layer into the high defect density region of the germanium layer, forming a P+ germanium layer 28 .
  • the donor wafer may be smoothed by an optional CMP step 30 to smooth the surface of the germanium layer, if required.
  • the top surface of the germanium may be implanted 32 to form a shallow N+ layer to reduce the leakage current of the IR detector, which process, is, however, an optional step.
  • Hydrogen, argon or helium ions are implanted 34 into silicon wafer 14 to form a defect layer 36 , which subsequently will be used to allow exfoliation of the surface layer of silicon donor wafer 14 along defect layer 36 .
  • the hydrogen ion implantation projected depth is into, or slightly deeper than, the P+ silicon layer.
  • the final donor wafer is depicted in FIG. 2 .
  • preparation 40 of a handling wafer 42 includes a conventional silicon substrate 44 , which has a CMOS integrated circuit 46 fabricated 48 thereon, including a metallization step, and, if required, multi-layer metal interconnects.
  • a layer of passivation oxide 50 is deposited 52 , and the wafer planarized by a CMP process 54 .
  • Contact holes are formed through conventional photolithographic processes, after which, metal is deposited, followed by CMP of the metal to form a detector connected to the CMOS interconnect metal plugs 56 .
  • a refractory metal such as Al, Au, Ag, Ir, Ni, Pd or Pt, is deposited 58 . Photoresist is applied and patterned to define the refractory metal to form a bottom electrode of the detectors. The refractory metal is etched, and the photoresist is stripped.
  • an optional layer of thin oxide may be deposited and smoothed by CMP 60 , stopping at the level of the refractory metal, in order further to planarize the handling wafer surface, which provides for better bonding to the germanium layer.
  • CMP 60 As depicted in FIG. 3 , only the pass transistor is shown. For the sake of simplicity other devices in the detector cell are not shown.
  • An optional layer, having a thickness of between about 5 nm to 10 nm of polysilicon or polygermanium may be deposited 62 to promote the adhesion between the germanium and the handling wafer.
  • the handling wafer and the donor wafer are bonded together.
  • Proper surface treatment 64 , 66 is necessary to create a good bond.
  • the germanium surface of the donor wafer may be treated as hydrophilic or hydrophobic, and a similar treatment may be applied to the handling wafer. Additionally, a plasma treatment may be applied to the wafer surfaces to improve the bonding strength.
  • Bonding 68 may be perform in the temperature range of between about 200° C. to 600° C., in either a vacuum or in another suitable ambient atmosphere.
  • the wafers are then split 70 , leaving the germanium thin film on the handling wafer, with a thin layer of P+ silicon on the germanium thin film.
  • This layer may be selectively etched 72 , or removed by a CMP process if desired, however, this is considered to be an optional process, as the P+ silicon layer has no effect on the electrical or optical properties of the completed detector.
  • a thin layer of indium tin oxide (ITO) 74 is deposited 76 to the top of the wafer, as depicted in FIG. 4 , which ITO layers serves as the ground plate of the detector.
  • ITO indium tin oxide
  • each cell detector may also desirable to isolate 78 each cell detector from one another to minimize cross talk between adjacent cells. This easily may be done by using a photoresist mask to etch the germanium layer, and subsequently filling the etched gap with silicon oxide 80 , smoothing by CMP, and stopping at the surface of the germanium layer, before the deposition of the ITO transparent metal electrode, as shown in FIG. 5 . It is noted that the P+ silicon on the top of P+ germanium and the optional N+ layer on the bottom of germanium layer are not shown in FIGS. 4 and 5 . Because the detector is driven by an N-MOST, the top P+ germanium junction and the bottom N+ germanium junction are reverse biased when the NMOS pass transistor is turned on. The IR sensor is then completed 82 according to state-of-the-art processes.

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Abstract

A method of fabricating a germanium infrared sensor for a CMOS imager includes preparation of a donor wafer, including: ion implantation into a silicon wafer to form a P+ silicon layer; growing an epitaxial germanium layer on the P+silicon layer, forming a silicon-germanium interface; cyclic annealing; and implanting hydrogen ions to a depth at least as deep as the P+ silicon layer to form a defect layer; preparing a handling wafer, including: fabricating a CMOS integrated circuit on a silicon substrate; depositing a layer of refractory metal; treating the surfaces of the donor wafer and the handling wafer for bonding; bonding the handling wafer and the donor wafer to form a bonded structure; splitting the bonded structure along the defect layer; depositing a layer of indium tin oxide on the germanium layer; completing the IR sensor.

Description

FIELD OF THE INVENTION
This invention relates to IR sensors, and specifically to fabrication of an IR sensor wherein a germanium thin film is grown on a silicon donor wafer, followed by a bonding and layer transfer process which transfers the germanium layer to another structure.
BACKGROUND OF THE INVENTION
Photo detecting in the near-infrared regime, e.g., wavelengths of between about 0.7 μm to 2 μm, has many applications, such as fiber-optical communication, security applications and thermal imaging. Silicon photodiodes are widely used as photodetectors for the visible light regime because of their low dark current and compatibility with silicon integrated circuit technologies. Attempts have been made to deposit Si1-xGex (SiGe) alloys, or germanium thin films, in silicon to fabricate an IR detector, however, the lattice mismatch in a SiGe-to-silicon boundary limits the maximum SiGe thickness which may be formed while still maintaining a defect free structure. Additionally, SiGe thin films having a germanium concentration of less than 50% have a relatively low IR absorption coefficient. Hence, it is difficult to fabricate an IR detector on SiGe film which has high sensitivity and low dark current.
Germanium has a high IR absorption coefficient, however, a 4% lattice mismatch to silicon results in a high dark current when a germanium photodetector is fabricated by direct deposition of germanium on silicon. A germanium photodetector having a simple PN diode structure exhibiting a very high dark current, e.g., about 30 mA/cm2, has been fabricated, Colace et al., Efficient high-speed near-infrared Ge photodetectors integrated on Si substrates, Applied Physics Letters, Vol. 76, No. 10, pp 1231-1233 (2000).
A germanium thin film bonded to silicon or silicon dioxide has been disclosed, wherein the IR sensor and the driving CMOS circuit are both fabricated on a germanium thin film. High temperature processes are required for germanium IC processes, i.e., ion implantation activation processes are usually performed following an annealing at about 800° C. Such high temperature processes degrade the quality of germanium thin films because the thermal expansion coefficient of silicon, germanium and silicon dioxide are different. A high temperature process performed on a germanium thin film which is bonded to a silicon wafer usually results in defects in the germanium layer(s), as described in U.S. Pat. No. 6,645,831, for Thermally stable crystalline defect-free germanium bonded to silicon and silicon dioxide, granted Nov. 11, 2003 to Shaheen et al. Additionally, germanium IC processes are not as well established in the semiconductor industry as are silicon IC processes.
A graded SiGe growth has been demonstrated to form a thick SiGe buffer layer prior to germanium growth, Lee et al., Optimized Strained Si/Strained Ge Dual-channel Heterostructures for High Mobility P− and N-MOSFETs, IEDM 2003, pp 429-432.
A Germanium p-MOSFET fabricated on bulk germanium and on epi-germanium has been disclosed by Ritenour et al., Epitaxial Strained Germanium p-MOSFETs with HfO 2 Gate Dielectric and TaN Gate Electrode, IEDM 2003, pp 433-436.
In U.S. patent application Ser. No. 10/993,533, filed Nov. 19, 2004, for Fabrication of Thin Film Germanium Infrared Sensor by Bonding to Silicon Wafer, a germanium IR detector is described, which detector may be fabricated on a silicon CMOS circuit by a bonding process in which a germanium donor wafer is required. The size of commercial germanium wafers is smaller than that of silicon wafers, and the process is therefore unable to take advantages of larger silicon wafers.
SUMMARY OF THE INVENTION
A method of fabricating a germanium infrared sensor for a CMOS imager includes preparation of a donor wafer, including; preparation of a silicon wafer; ion implantation into the silicon wafer to form a P+ silicon layer; growing an epitaxial germanium layer on the P+ silicon layer, cyclic annealing the wafer to from a layer of high density of defects on the germanium side of the silicon-germanium interface and to diffuse ions from the P+ silicon layer into the high defect density region of the germanium layer forming a P+ germanium layer; implanting hydrogen ions to a depth at least as deep as the P+ silicon layer to form a defect layer; preparing a handling wafer, including: fabricating a CMOS integrated circuit on the silicon substrate; completing multiple metal interconnects; preparing a silicon substrate; depositing a layer of passivation oxide on the CMOS integrated circuit; planarizing the structure by CMP; forming contact or via holes; removing surface metal by CMP to form metal plugs, smoothing the metal plugs by CMP; depositing a layer of refractory metals; photomaskinig and etching to define the refractory metal to form a bottom electrode for the sensor; depositing a thin layer of dielectric, smoothing the dielectric by CMP; stopping at the level of the refractory metal; treating the surfaces of the donor wafer and the handling wafer for bonding; bonding the handling wafer and the donor wafer to form a bonded structure; splitting the bonded structure along the defect layer; depositing a layer of indium tin oxide on the germanium layer; completing the IR sensor.
It is an object of the invention to provide a method of using a silicon wafer, which has a germanium epitaxial layer thereon, as a donor wafer for bonding a germanium layer onto a silicon CMOS for use as an IR detector.
This summary and objectives of the invention are provided to enable quick comprehension of the nature of the invention. A more thorough understanding of the invention may be obtained by reference to the following detailed description of the preferred embodiment of the invention in connection with the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of the method of the invention.
FIGS. 2-5 depicts steps in the method of the invention.
 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
This disclosure differs from the above-cited U.S. Patent Application in that in the previous disclosure, the germanium wafer is bonded onto a silicon CMOS wafer, and in this disclosure, a germanium thin film is grown onto a silicon donor wafer, followed by a bonding process.
Preparation of Donor Wafers
Referring now to FIGS. 1 and 2, the initial steps in the method of the invention 10 include preparation of what is referred to herein as a donor wafer 12, including preparation of a conventional silicon wafer 14. Ion implantation 16 of boron ions into the silicon wafer converts the surface layer of the donor silicon wafer to a P+ material 18. The doping density is in the order of 1×1019cm−3 to 1×1020 cm−3.
The next step is epitaxial growth 20 of between about 0.5 μm to 4.0 μm of germanium 22 onto the P+ wafer material, followed by cyclic annealing 24. The range of temperature for the high temperature portion of the cyclic annealing is between about 800° C. to 900° C. The range of temperature in the low temperature portion of the cyclic annealing is between about 700° C. to 850° C. The time interval for each annealing is between about one to ten minutes, and the number of cycles is between about 5 to 50 cycles. During cyclic annealing, a layer 26 of high density of defects is created on the germanium side of the silicon-germanium interface, while the boron simultaneously diffuses from the P+ silicon layer into the high defect density region of the germanium layer, forming a P+ germanium layer 28. The donor wafer may be smoothed by an optional CMP step 30 to smooth the surface of the germanium layer, if required.
The top surface of the germanium may be implanted 32 to form a shallow N+ layer to reduce the leakage current of the IR detector, which process, is, however, an optional step. Hydrogen, argon or helium ions are implanted 34 into silicon wafer 14 to form a defect layer 36, which subsequently will be used to allow exfoliation of the surface layer of silicon donor wafer 14 along defect layer 36. The hydrogen ion implantation projected depth is into, or slightly deeper than, the P+ silicon layer. The final donor wafer is depicted in FIG. 2.
Preparation of Handling Wafers
Referring now to FIGS. 1 and 3, preparation 40 of a handling wafer 42 includes a conventional silicon substrate 44, which has a CMOS integrated circuit 46 fabricated 48 thereon, including a metallization step, and, if required, multi-layer metal interconnects. A layer of passivation oxide 50 is deposited 52, and the wafer planarized by a CMP process 54. Contact holes are formed through conventional photolithographic processes, after which, metal is deposited, followed by CMP of the metal to form a detector connected to the CMOS interconnect metal plugs 56. A refractory metal such as Al, Au, Ag, Ir, Ni, Pd or Pt, is deposited 58. Photoresist is applied and patterned to define the refractory metal to form a bottom electrode of the detectors. The refractory metal is etched, and the photoresist is stripped.
At this point, an optional layer of thin oxide may be deposited and smoothed by CMP 60, stopping at the level of the refractory metal, in order further to planarize the handling wafer surface, which provides for better bonding to the germanium layer. As depicted in FIG. 3, only the pass transistor is shown. For the sake of simplicity other devices in the detector cell are not shown.
An optional layer, having a thickness of between about 5 nm to 10 nm of polysilicon or polygermanium may be deposited 62 to promote the adhesion between the germanium and the handling wafer.
Bonding
The handling wafer and the donor wafer are bonded together. Proper surface treatment 64, 66, is necessary to create a good bond. The germanium surface of the donor wafer may be treated as hydrophilic or hydrophobic, and a similar treatment may be applied to the handling wafer. Additionally, a plasma treatment may be applied to the wafer surfaces to improve the bonding strength. Bonding 68 may be perform in the temperature range of between about 200° C. to 600° C., in either a vacuum or in another suitable ambient atmosphere.
The wafers are then split 70, leaving the germanium thin film on the handling wafer, with a thin layer of P+ silicon on the germanium thin film. This layer may be selectively etched 72, or removed by a CMP process if desired, however, this is considered to be an optional process, as the P+ silicon layer has no effect on the electrical or optical properties of the completed detector. A thin layer of indium tin oxide (ITO) 74 is deposited 76 to the top of the wafer, as depicted in FIG. 4, which ITO layers serves as the ground plate of the detector.
It may also desirable to isolate 78 each cell detector from one another to minimize cross talk between adjacent cells. This easily may be done by using a photoresist mask to etch the germanium layer, and subsequently filling the etched gap with silicon oxide 80, smoothing by CMP, and stopping at the surface of the germanium layer, before the deposition of the ITO transparent metal electrode, as shown in FIG. 5. It is noted that the P+ silicon on the top of P+ germanium and the optional N+ layer on the bottom of germanium layer are not shown in FIGS. 4 and 5. Because the detector is driven by an N-MOST, the top P+ germanium junction and the bottom N+ germanium junction are reverse biased when the NMOS pass transistor is turned on. The IR sensor is then completed 82 according to state-of-the-art processes.
Thus, a method for fabrication of a germanium infrared sensor for CMOS imagers has been disclosed. It will be appreciated that further variations and modifications thereof may be made within the scope of the invention as defined in the appended claims.

Claims (20)

1. A method of fabricating a germanium infrared sensor for a CMOS imager, comprising:
preparation of a donor wafer, including:
preparation of a silicon wafer;
ion implantation into the silicon wafer to form a P+ silicon layer;
growing an epitaxial germanium layer on the P+ silicon layer, forming a silicon-germanium interface;
cyclic annealing to form a layer of high density of defects on the germanium side of the silicon-germanium interface and to diffuse ions from the P+ silicon layer into the high defect density region of the germanium layer forming a P+ germanium layer; and
implanting hydrogen ions to a depth at least as deep as the P+ silicon layer to form a defect layer;
preparing a handling wafer, including:
preparing a silicon substrate;
fabricating a CMOS integrated circuit on the silicon substrate;
depositing a layer of passivation oxide on the CMOS integrated circuit;
forming contact holes;
depositing metal and smoothing the metal by CMP to from metal plugs in the contact holes;
depositing a layer of refractory metal;
treating the surfaces of the donor wafer and the handling wafer for bonding;
bonding the handling wafer and the donor wafer to form a bonded structure;
splitting the bonded structure along the defect layer;
depositing a layer of indium tin oxide on the germanium layer;
completing the IR sensor.
2. The method of claim 1 which further includes smoothing the germanium layer on the donor wafer by CMP.
3. The method of claim 1 which further includes implanting ions in the top surface of the germanium to form a shallow N+ layer.
4. The method of claim 1 which further includes, after said depositing a layer of refractory metal, photomasking and etching to form a bottom electrode for the sensor; and depositing a layer of thin oxide and smoothing by CMP, stopping at the level of the refractory metal.
5. The method of claim 1 which further includes, after said depositing a layer of refractory metal, depositing a layer of material taken from the group of materials consisting of polysilicon and polygermanium.
6. The method of claim 1 wherein said treating the surfaces of the donor wafer and the handling wafer for bonding includes treating bonding surfaces of the donor wafer and the handling wafer as hydrophilic or hydrophobic.
7. The method of claim 6 which further includes treating the bonding surfaces with a plasma treatment.
8. The method of claim 1 wherein said bonding is performed in a temperature range of between about 200 EC to 600 EC, in a vacuum or in a suitable ambient atmosphere.
9. The method of claim 1 wherein, after said splitting, a thin layer of P+ silicon is located on the germanium thin film, and wherein the thin Layer of P+ silicon is removed by a process taken from the group of processes consisting of selective etch and CMP process.
10. The method of claim 1 wherein before said depositing a layer of indium tin oxide on the germanium layer, each cell detector is isolated from adjacent cells by masking, patterning and etching, and subsequent filling of an etched gap with silicon oxide, and smoothing of the last deposited silicon oxide by CMP.
11. The method of claim 1 wherein said cyclic annealing includes annealing at a high temperature range of between about 800 EC to 900 EC, annealing at a low temperature of between about 700 EC to 850 EC, for between about one to ten minutes for each cycle, and which includes repeating the cyclic anneal for between about 5 to 50 cycles.
12. A method of fabricating a germanium infrared sensor for a CMOS imager, comprising:
preparation a donor wafer, including:
preparation of a silicon wafer;
ion implantation into the silicon wafer to form a P+ silicon layer;
growing an epitaxial germanium layer on the P+ silicon layer, forming a silicon-germanium interface;
cyclic annealing to from a layer of high density of defects on the germanium side of the silicon-germanium interface and to diffuse ions from the P+ silicon layer into the high defect density region of the germanium layer forming a P+ germanium layer, wherein said cyclic annealing includes annealing at a high temperature range of between about 800 EC to 900 EC, annealing at a low temperature of between about 700 EC to 850 EC, for between about one to ten minutes for each cycle, and which includes repeating the cyclic anneal for between about 5 to 50 cycles;
implanting hydrogen ions to a depth at least as deep as the P+ silicon layer to form a defect layer;
preparing a handling wafer, including:
preparing a silicon substrate;
fabricating a CMOS integrated circuit on the silicon substrate;
depositing a layer of passivation oxide on the CMOS integrated circuit;
forming contact holes;
depositing metal and smoothing the metal by CMP to from metal plugs in the contact holes;
depositing a layer of refractory metals;
treating the surfaces of the donor wafer and the handling wafer for bonding;
bonding the handling wafer and the donor wafer to form a bonded structure;
splitting the bonded structure along the defect layer;
depositing a layer of indium tin oxide on the germanium layer;
completing the IR sensor.
13. The method of claim 12 which further includes smoothing the germanium layer on the donor wafer by CMP.
14. The method of claim 12 which further includes implanting ions in the top surface of the germanium to form a shallow N+ layer.
15. The method of claim 12 which further includes, after said depositing a layer of refractory metal, photomasking and etching to form a bottom electrode for the sensor; and depositing a layer of thin oxide and smoothing by CMP, stopping at the level of the refractory metal.
16. The method of claim 12 which further includes, after said depositing a layer of refractory metal, depositing a layer of material taken from the group of materials consisting of polysilicon and polygermanium.
17. The method of claim 12 wherein said treating the surfaces of the donor wafer and the handling wafer for bonding includes treating bonding surfaces of the donor wafer and the handling wafer as hydrophilic or hydrophobic, and which further includes treating the bonding surfaces with a plasma treatment.
18. The method of claim 12 wherein said bonding is performed in a temperature range of between about 200 EC to 600 EC, in a vacuum or in a suitable ambient atmosphere.
19. The method of claim 12 wherein, after said splitting, a thin layer of P+ silicon is located on the germanium thin film, and wherein the thin layer of P+silicon is removed by a process taken from the group of processes consisting of selective etch and CMP process.
20. The method of claim 12 wherein before said depositing a layer of indium tin oxide on the germanium layer, each cell detector is isolated from adjacent cells by masking, patterning and etching, and subsequent filling of an etched gap with oxide, and smoothing of the last deposited oxide by CMP.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9911770B2 (en) 2016-05-31 2018-03-06 Omnivision Technologies, Inc. Graded-semiconductor image sensor
WO2020225588A1 (en) * 2019-05-04 2020-11-12 Trieye Ltd. Low leakage current germanium-on-silicon photo-devices
US20240120314A1 (en) * 2021-05-12 2024-04-11 Taiwan Semiconductor Manufacturing Co., Ltd. Ion implantation with annealing for substrate cutting

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4149168B2 (en) 2001-11-09 2008-09-10 株式会社半導体エネルギー研究所 Light emitting device
US7538010B2 (en) * 2003-07-24 2009-05-26 S.O.I.Tec Silicon On Insulator Technologies Method of fabricating an epitaxially grown layer
FR2857983B1 (en) * 2003-07-24 2005-09-02 Soitec Silicon On Insulator PROCESS FOR PRODUCING AN EPITAXIC LAYER
US7442599B2 (en) * 2006-09-15 2008-10-28 Sharp Laboratories Of America, Inc. Silicon/germanium superlattice thermal sensor
WO2009016261A1 (en) * 2007-08-02 2009-02-05 Technische Universität München Device for imaging and method for producing the device
US20090127644A1 (en) * 2007-11-16 2009-05-21 Anton Petrus M. VAN ARENDONK Semiconductor device comprising an image sensor, apparatus comprising such a semiconductor device and method of manufacturing such a semiconductor device
KR101419533B1 (en) * 2012-12-31 2014-07-14 성균관대학교산학협력단 defect healing method in junction of semiconductor devices with Ge
US9821066B2 (en) 2013-03-15 2017-11-21 Carefusion 2200, Inc. Tinted antiseptic solutions having improved stability
CN104752341B (en) * 2013-12-31 2018-01-30 上海丽恒光微电子科技有限公司 Infrared avalanche photodiode arrays device and forming method, laser three-dimensional imaging device
JP6437404B2 (en) * 2015-09-09 2018-12-12 東芝メモリ株式会社 Manufacturing method of semiconductor device
US9955087B1 (en) 2016-12-30 2018-04-24 Wisconsin Alumni Research Foundation Hydrogen-doped germanium nanomembranes
WO2018153503A1 (en) * 2017-02-23 2018-08-30 Iris Industries Sa Short-wave infrared detector array and method for the manufacturing thereof
FR3089348B1 (en) * 2018-11-30 2020-10-30 Commissariat Energie Atomique method of manufacturing a germanium-based, low dark current diode array
CN115039225A (en) * 2020-02-07 2022-09-09 华为技术有限公司 Optical sensor device and method for manufacturing the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6645831B1 (en) 2002-05-07 2003-11-11 Intel Corporation Thermally stable crystalline defect-free germanium bonded to silicon and silicon dioxide

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6645831B1 (en) 2002-05-07 2003-11-11 Intel Corporation Thermally stable crystalline defect-free germanium bonded to silicon and silicon dioxide

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
Colace et al., Efficient high-speed near-infrared Ge photodetectors integrated on Si substrates, Applied Physics Letters, vol. 76, No. 10, pp. 1231-1233 (2000).
Lee et al., Optimized Strained Si/Strained Ge Dual-channel Heterostructures for High Mobility P- and N-MOSFETs, IEDM 2003, pp. 429-432.
Ritenour et al., Epitaxial Strained Germanium p-MOSFETs with HfO<SUB>2 </SUB>Gate Dielectric and TaN Gate Electrode, IEDM 2003, pp. 433-436.

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9911770B2 (en) 2016-05-31 2018-03-06 Omnivision Technologies, Inc. Graded-semiconductor image sensor
US10103185B2 (en) 2016-05-31 2018-10-16 Omnivision Technologies, Inc. Graded-semiconductor image sensor
WO2020225588A1 (en) * 2019-05-04 2020-11-12 Trieye Ltd. Low leakage current germanium-on-silicon photo-devices
US11894480B2 (en) 2019-05-04 2024-02-06 Trieye Ltd. Low leakage current germanium-on-silicon photo-devices
US20240120314A1 (en) * 2021-05-12 2024-04-11 Taiwan Semiconductor Manufacturing Co., Ltd. Ion implantation with annealing for substrate cutting

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