US5917870A - Synchronization monitoring in a network element - Google Patents

Synchronization monitoring in a network element Download PDF

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US5917870A
US5917870A US08/560,073 US56007395A US5917870A US 5917870 A US5917870 A US 5917870A US 56007395 A US56007395 A US 56007395A US 5917870 A US5917870 A US 5917870A
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clock frequency
network element
signal
synchronization
comparing
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Michael Wolf
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Alcatel Lucent NV
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0691—Synchronisation in a TDM node
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0057—Operations, administration and maintenance [OAM]
    • H04J2203/006—Fault tolerance and recovery
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0089—Multiplexing, e.g. coding, scrambling, SONET

Definitions

  • the present invention relates to a network element for a digital transmission system and, more particularly, a network element having at least one interface unit which may include a device for converting an incoming optical signal of a first clock frequency to a corresponding electrical signal of the same clock frequency.
  • Such a digital transmission system is, for example, a synchronous transmission system according to the SDH/SONET standard.
  • individual network elements are interconnected by different transmission media (e.g., copper cables, optical fiber waveguides, or radio links).
  • connection between a network element and a transmission medium is provided by interface units ("network node interfaces"), which are known, for example, from ITU-T Recommendations G.703 and G.957.
  • interface units network node interfaces
  • Recommendation G.703 specifies electrical characteristics of such interface units
  • Recommendation G.957 specifies optical characteristics of such units.
  • incoming optical signals for example, are converted to electric signals by an optical-to-electrical transducer. Consequently, outgoing electrical signals are converted to optical signals by an electrical-to-optical transducer. During such a conversion, the clock frequency of the respective signal does not change.
  • each network element which is a cross-connect, for example, an internal clock frequency serves as a clock reference. Deviations of the clock frequency of an incoming signal from this internal clock frequency gives information about the synchronization status of the transmission system.
  • An overview of the subject of synchronization is given in an article by W. E. Powell et al, "Synchronization and Timing of SDH Networks", Electrical Communication (Alcatel), 4th Quarter 1993, pages 349 to 358.
  • Such monitoring is disadvantageous in that because of an unstandardized hysteresis associated with the pointer processor, the information derived from the pointer activity permits only qualified statements about the synchronization status.
  • a network element for a digital transmission system comprises at least one interface unit having a synchronization-monitoring device which compares a first clock frequency of an incoming signal with a second clock frequency fixed in the network element to derive at least one synchronization status parameter.
  • a network element for a digital transmission system comprises at least one interface unit having a device for converting an incoming optical signal of a first clock frequency to a corresponding electrical signal of the same clock frequency, wherein the interface unit further includes a synchronization-monitoring device which compares the first clock frequency with a second clock frequency fixed in the network element to derive at least one synchronization status parameter.
  • the synchronization-monitoring device of the network element comprises a phase-comparing device for comparing the first and second clock frequencies within a predetermined time interval, a memory device for storing difference values determined by the phase-comparing device, and an evaluating device for evaluating values read from the memory device at predetermined time intervals.
  • the phase-comparing device may include at least one counting device and a control device for reading from the counting device at regular time intervals and then resetting the counting device.
  • the counting device may be a 16-stage counter, for example.
  • One advantage of the invention is that incorrect synchronization can be detected at an early time, so that preventive measures can be taken.
  • a second advantage of the invention is that with the aid of the synchronization status, decisions are simplified as to how an existing transmission system can be expanded, possibly without reorganization of the synchronization architecture.
  • a third advantage of the invention is that a network operator can continuously check a synchronization performance guaranteed to his customer.
  • FIG. 1 is a block diagram of a network element according to the invention with a synchronization-monitoring device ;
  • FIG. 2 is a block diagram of a synchronization-monitoring device.
  • FIG. 1 there is shown a block diagram of a network element 1 according to the invention with a synchronization-monitoring device 6.
  • This network element 1 is, for example, a cross-connect in an exchange.
  • the network element 1 has three interface units 2, 3, and 4, which are connected to transmission media 10, 11, and 12 via ports 7, 8, and 9, respectively.
  • the interface unit 2, which contains an optical-to-electrical transducer 5 and the synchronization-monitoring device 6, is connected to an optical fiber waveguide 10 (transmission medium) via the port 7.
  • the optical-to-electrical transducer 5 converts an optical signal of a first clock frequency T e , which arrives over the optical fiber waveguide 10, to a corresponding electric signal of the same clock frequency T e .
  • This first clock frequency T e will hereinafter be referred to as the "external clock frequency”.
  • This external clock frequency T e may be divided in the network element 1 according to a predetermined division ratio. Despite this division, however, an unambiguous inference to the external clock frequency T e is always possible. A comparison which will be explained in the following is not affected by this division, i.e., even after such a division, a comparison takes place between the external frequency T e , and a second clock frequncy.
  • a common second clock frequency T i is fixed, which will hereinafter be referred to as the "internal clock frequency”.
  • the synchronization-monitoring device 6 is contained in the interface unit 2, but it may also be contained in at least one of the other interface units 3, 4.
  • the synchronization-monitoring device 6 is shown in block-diagram form in FIG. 2. It has a phasecomparing device 37, a memory device 25, and an evaluating device 26.
  • the phase-comparing device 37 has two AND gates 23, 24, two counting devices 21, 22, and a control device 20.
  • the AND gate 23 is connected to the counting device 21 by a line 31, and the AND gate 24 is connected to the counting device 22 by a line 32.
  • the counting devices 21 and 22 are connected to the control device 20 by data links 29 and 30, respectively.
  • the control device 20 is connected to the counting device 21 by a line 27 and to the counting device 22 by a line 28.
  • a divider 38 is designed to reduce the internal clock frequency T i to a clock frequency T io .
  • This clock frequency T io thus defines a time interval.
  • the divider 38 can be located at any point of the network element; in FIG. 2, it is located outside the synchronization-monitoring device 6.
  • the comparison between the clock frequency T io and the, possibly divided, external clock frequency T e in the phase-comparing device 37 is to be understood as if a comparison were made between the internal clock frequency T i and the external clock frequency T e .
  • the inputs to the AND gate 23 are the external clock frequency T e and the clock frequency T io .
  • the signal of clock frequency T io is a sequence of logic O and 1 states of equal duration.
  • the inputs to the AND gate 24 are the external clock frequency T e and the clock frequency T io .
  • One input of the AND gate 24 is an inverting input to invert the signal of frequency T io .
  • the clock frequency T io is also applied to the control device 20 over a line 36.
  • the control device 20 of the phase-comparing device 37 is connected to the memory device 25 by a line 33, and the memory device 25 is connected to the evaluating device 26 by a line 34.
  • the evaluating device is a computer in which an evaluation program is executed.
  • the evaluating device 26 forms part of the synchronization-monitoring device 6, no matter where it is located, i.e., it may be located in the interface unit 2 (FIG. 1) or at a monitoring center. There, the evaluation results (e.g., TIE) can be displayed on a screen. This is indicated in FIG. 2 by a signal on line 35 at the evaluating device 26.
  • the operation of the synchronization-monitoring device 6 is as follows.
  • the clock frequency T io defines a time interval, e.g., 1.024 s.
  • the AND gate 23 only gives a "1" output if both inputs (T e , T io ) are also "1".
  • the counting device 21 counts how often that was the case in the time interval.
  • the modified AND gate 24 is provided, i.e., this gate makes it possible to perform a comparison even if the signal of clock frequency T io is in a logic O state.
  • the counting device 22 also counts how often the input signals (T e , T io ) are equal in the measurement interval.
  • the control device 20 is supplied with the clock frequency T io so that at the end of each time interval, the control device 20 interrogates the counting devices 21, 22, transfers the number of pulses counted per time interval (count) to the memory device 25, and resets the counting devices 21, 22.
  • the number of pulses counted per time interval are a measure of the clock frequency, and thus a measure of the clock-frequency deviation to be determined. For a clock-frequency deviation of 4.6 ppm (parts per million), the count is 733 units away from a nominal value. The number of pulses counted per time interval thus represent difference values determined by the phase-comparing device 37.
  • the stored amount of data is, for example, 180 kbytes per day.
  • the amount of data is, for example, 500-5 kbytes per month, for example.
  • the values stored in the memory device 25 can be evaluated statistically:
  • the evaluating device 25 interrogates the memory device 25 at fixed time intervals, i.e., the memory device 25 is polled.
  • statistical synchronization status parameters are then obtained, such as time interval error (TIE), root mean square TIE (RMS TIE), maximum relative TIE (MRTIE), and time deviation (TDEV).
  • TIE time interval error
  • RMS TIE root mean square TIE
  • MRTIE maximum relative TIE
  • TDEV time deviation

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Optical Communication System (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

In digital transmission systems, such as synchronous transmission systems according to the SDH/SONET standard, there is a need to have information on the synchronization status of the system. A known approach is to monitor the pointer activity. This is disadvantageous in that because of a hysteresis in the pointer processor, information derived from the pointer activity only conditionally reflects the synchronization status. In a network element (1) according to the invention which forms part of a transmission system of the above type, at least one interface unit (2, 3, 4) contains, besides an optical-to-electrical transducer (5), a synchronization-monitoring device (6) which derives a synchronization status parameter, e.g., TIE, RMSTIE, by comparing an external clock frequency (Te) with an internal clock frequency (Ti). For this, the synchronization-monitoring device (6) comprises a phase-comparing device (37), a memory device (25), and an evaluating device (26).

Description

TECHNICAL FIELD
The present invention relates to a network element for a digital transmission system and, more particularly, a network element having at least one interface unit which may include a device for converting an incoming optical signal of a first clock frequency to a corresponding electrical signal of the same clock frequency.
BACKGROUND OF THE INVENTION
Such a digital transmission system is, for example, a synchronous transmission system according to the SDH/SONET standard. In such a digital transmission system, individual network elements are interconnected by different transmission media (e.g., copper cables, optical fiber waveguides, or radio links).
The connection between a network element and a transmission medium is provided by interface units ("network node interfaces"), which are known, for example, from ITU-T Recommendations G.703 and G.957. Recommendation G.703 specifies electrical characteristics of such interface units, and Recommendation G.957 specifies optical characteristics of such units. In an interface unit connected to an optical fiber waveguide, incoming optical signals, for example, are converted to electric signals by an optical-to-electrical transducer. Consequently, outgoing electrical signals are converted to optical signals by an electrical-to-optical transducer. During such a conversion, the clock frequency of the respective signal does not change.
In each network element, which is a cross-connect, for example, an internal clock frequency serves as a clock reference. Deviations of the clock frequency of an incoming signal from this internal clock frequency gives information about the synchronization status of the transmission system. An overview of the subject of synchronization is given in an article by W. E. Powell et al, "Synchronization and Timing of SDH Networks", Electrical Communication (Alcatel), 4th Quarter 1993, pages 349 to 358.
To monitor the synchronization status, it is known, (Report on ETSI-TM3 Meeting in BristoL, October 1992, page 205) to monitor the pointer activity. Monitoring the synchronization status with the aid of the pointer activity is required in BeLLcore
TA-NWT-000 436. Such monitoring is disadvantageous in that because of an unstandardized hysteresis associated with the pointer processor, the information derived from the pointer activity permits only qualified statements about the synchronization status.
DISCLOSURE OF THE INVENTION
It is the object of the invention to provide a network element for a digital transmission system wherein the synchronization status is monitored in another manner.
According to a first aspect of the present invention, a network element for a digital transmission system comprises at least one interface unit having a synchronization-monitoring device which compares a first clock frequency of an incoming signal with a second clock frequency fixed in the network element to derive at least one synchronization status parameter.
In accordance with a second aspect of the present invention, a network element for a digital transmission system comprises at least one interface unit having a device for converting an incoming optical signal of a first clock frequency to a corresponding electrical signal of the same clock frequency, wherein the interface unit further includes a synchronization-monitoring device which compares the first clock frequency with a second clock frequency fixed in the network element to derive at least one synchronization status parameter.
According further to either the first or second aspects of the present invention, the synchronization-monitoring device of the network element comprises a phase-comparing device for comparing the first and second clock frequencies within a predetermined time interval, a memory device for storing difference values determined by the phase-comparing device, and an evaluating device for evaluating values read from the memory device at predetermined time intervals. The phase-comparing device may include at least one counting device and a control device for reading from the counting device at regular time intervals and then resetting the counting device. The counting device may be a 16-stage counter, for example.
One advantage of the invention is that incorrect synchronization can be detected at an early time, so that preventive measures can be taken.
A second advantage of the invention is that with the aid of the synchronization status, decisions are simplified as to how an existing transmission system can be expanded, possibly without reorganization of the synchronization architecture.
A third advantage of the invention is that a network operator can continuously check a synchronization performance guaranteed to his customer.
These and other objects, features and advantages of the present invention will become more apparent in light of the detailed description of a best mode embodiment thereof, as illustrated in the accompanying drawing.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a network element according to the invention with a synchronization-monitoring device ; and
FIG. 2 is a block diagram of a synchronization-monitoring device.
BEST MODE FOR CARRYING OUT THE INVENTION
Referring to FIG. 1, there is shown a block diagram of a network element 1 according to the invention with a synchronization-monitoring device 6. This network element 1 is, for example, a cross-connect in an exchange. The network element 1 has three interface units 2, 3, and 4, which are connected to transmission media 10, 11, and 12 via ports 7, 8, and 9, respectively. The interface unit 2, which contains an optical-to-electrical transducer 5 and the synchronization-monitoring device 6, is connected to an optical fiber waveguide 10 (transmission medium) via the port 7.
The optical-to-electrical transducer 5 converts an optical signal of a first clock frequency Te, which arrives over the optical fiber waveguide 10, to a corresponding electric signal of the same clock frequency Te. This first clock frequency Te will hereinafter be referred to as the "external clock frequency". This external clock frequency Te may be divided in the network element 1 according to a predetermined division ratio. Despite this division, however, an unambiguous inference to the external clock frequency Te is always possible. A comparison which will be explained in the following is not affected by this division, i.e., even after such a division, a comparison takes place between the external frequency Te, and a second clock frequncy. In the network element 1, and hence in the interface units 2, 3, 4, a common second clock frequency Ti is fixed, which will hereinafter be referred to as the "internal clock frequency".
In FIG. 1, the synchronization-monitoring device 6 is contained in the interface unit 2, but it may also be contained in at least one of the other interface units 3, 4. The synchronization-monitoring device 6 is shown in block-diagram form in FIG. 2. It has a phasecomparing device 37, a memory device 25, and an evaluating device 26. The phase-comparing device 37 has two AND gates 23, 24, two counting devices 21, 22, and a control device 20. The AND gate 23 is connected to the counting device 21 by a line 31, and the AND gate 24 is connected to the counting device 22 by a line 32. The counting devices 21 and 22 are connected to the control device 20 by data links 29 and 30, respectively.
The control device 20 is connected to the counting device 21 by a line 27 and to the counting device 22 by a line 28.
A divider 38 is designed to reduce the internal clock frequency Ti to a clock frequency Tio . This clock frequency Tio thus defines a time interval. The divider 38 can be located at any point of the network element; in FIG. 2, it is located outside the synchronization-monitoring device 6.
As the clock frequency Tio is derived from the internal clock frequency Ti, the comparison between the clock frequency Tio and the, possibly divided, external clock frequency Te in the phase-comparing device 37 is to be understood as if a comparison were made between the internal clock frequency Ti and the external clock frequency Te. The inputs to the AND gate 23 are the external clock frequency Te and the clock frequency Tio. The signal of clock frequency Tio is a sequence of logic O and 1 states of equal duration. The inputs to the AND gate 24 are the external clock frequency Te and the clock frequency Tio. One input of the AND gate 24 is an inverting input to invert the signal of frequency Tio. The clock frequency Tio is also applied to the control device 20 over a line 36.
The control device 20 of the phase-comparing device 37 is connected to the memory device 25 by a line 33, and the memory device 25 is connected to the evaluating device 26 by a line 34. The evaluating device is a computer in which an evaluation program is executed. The evaluating device 26 forms part of the synchronization-monitoring device 6, no matter where it is located, i.e., it may be located in the interface unit 2 (FIG. 1) or at a monitoring center. There, the evaluation results (e.g., TIE) can be displayed on a screen. This is indicated in FIG. 2 by a signal on line 35 at the evaluating device 26.
The operation of the synchronization-monitoring device 6 is as follows.
As mentioned above, the clock frequency Tio defines a time interval, e.g., 1.024 s. The AND gate 23 only gives a "1" output if both inputs (Te, Tio) are also "1". The counting device 21 counts how often that was the case in the time interval. To perform uninterrupted measurements, the modified AND gate 24 is provided, i.e., this gate makes it possible to perform a comparison even if the signal of clock frequency Tio is in a logic O state. Thus, the counting device 22 also counts how often the input signals (Te, Tio) are equal in the measurement interval.
The control device 20 is supplied with the clock frequency Tio so that at the end of each time interval, the control device 20 interrogates the counting devices 21, 22, transfers the number of pulses counted per time interval (count) to the memory device 25, and resets the counting devices 21, 22.
The number of pulses counted per time interval are a measure of the clock frequency, and thus a measure of the clock-frequency deviation to be determined. For a clock-frequency deviation of 4.6 ppm (parts per million), the count is 733 units away from a nominal value. The number of pulses counted per time interval thus represent difference values determined by the phase-comparing device 37.
To determine the clock-frequency deviation, it is not necessary to know the absolute count; it suffices to evaluate the least significant bits of the count.
From this it follows that two bytes suffice to represent the count.
For a short-term-stability analysis, the stored amount of data is, for example, 180 kbytes per day. For a long-term-stability analysis, it is possible to reduce the amount of data by a factor of 10-1000, which gives 500-5 kbytes per month, for example.
If the fixed time interval is 1.024 s long, two 16-stage binary counting device 21, 22 are needed. The values stored in the memory device 25 can be evaluated statistically: The evaluating device 25 interrogates the memory device 25 at fixed time intervals, i.e., the memory device 25 is polled. As the evaluation result, statistical synchronization status parameters are then obtained, such as time interval error (TIE), root mean square TIE (RMS TIE), maximum relative TIE (MRTIE), and time deviation (TDEV). These parameters and their determination are known, for example, from the above-mentioned article by R. W. Cubbage, especially pages 355 to 357, or from BeLLcore TECHNICAL REFERENCE TR-NWT-001244, especially pages 2-6 to 2-9.
Although the invention has been shown and described with respect to a best mode embodiment thereof, it should be understood by those skilled in the art that the foregoing and various other changes, omissions and additions in the form and detail thereof may be made therein without departing from the spirit and scope of the invention.

Claims (14)

I claim:
1. A network element for a digital transmission system, comprising at least one interface unit, characterized in that the interface unit (2, 3, 4) includes a synchronization monitoring device (6) for comparing a first clock frequency (Te) of an incoming signal with a second clock frequency (Ti) of a signal fixed in the network element (1) for providing at least one synchronization status parameter signal, and in that the synchronization-monitoring device (6) comprises a phase-comparing device (37) for said comparing the first clock frequency (Te) with the second clock frequency (Ti) within a predetermined time interval for providing a difference value signal (33), a memory device (25) for storing said difference value signal, and an evaluating device (26) for evaluating said difference value signal read from the memory device at predetermined time intervals for providing said synchronization status parameter signal.
2. A network element as claimed in claim 1, characterized in that the phase-comparing device (37) includes at least one counting device (21, 22) and a control device (20) for reading from the counting device (21, 22) at regular time intervals and then resetting the counting device.
3. A network element as claimed in claim 2, characterized in that the counting device (21, 22) is a 16-stage counter.
4. A network element for a digital transmission system comprising at least one interface unit (2, 3, 4) which includes a device (5) for converting an incoming optical signal of a first clock frequency (Te) to a corresponding electric signal of the same clock frequency (Te) characterized in that the interface unit (2) further includes a synchronization-monitoring device (6) for comparing the first clock frequency (Te) with a second clock frequency (Ti) of a signal fixed in the network element (1) for providing at least one synchronization status parameter signal and in that the synchronization-monitoring device (6) comprises a phase-comparing device (37) for said comparing the first clock frequency (Te) with the second clock frequency (Ti) within a predetermined time interval for providing a difference value signal (33), a memory device (25) for storing said difference value signal, and an evaluating device (26) for evaluating said value signal read from the memory device at predetermined time intervals for providing said synchronization status parameter signal.
5. A network element as claimed in claim 4, characterized in that the phase-comparing device (37) includes at least one counting device (21, 22) and a control device (20) for reading from the counting device (21, 22) at regular time intervals and then resetting the counting device.
6. A network element as claimed in claim 5, characterized in that the counting device (21, 22) is a 16-stage counter.
7. A network element for a digital transmission system, comprising at least one interface unit, characterized in that the interface unit (2, 3, 4) includes a synchronization monitoring device (6) for comparing a first clock frequency (Te) of an incoming signal with a second clock frequency (Ti) of a signal fixed in the network element (1) for obtaining a difference value signal (33), said synchronization monitoring device further evaluating said difference value signal statistically at fixed time intervals to provide at least one statistical synchronization status parameter signal.
8. A network element as claimed in claim 7, characterized in that the synchronization-monitoring device (6) comprises a phase-comparing device (37) for said comparing the first clock frequency (Te) with the second clock frequency (Ti) within a predetermined time interval for providing a difference value signal (33), a memory device (25) for storing said difference value signal, and an evaluating device (26) for evaluating said difference value signal read from the memory device at predetermined time intervals for providing said synchronization status parameter signal.
9. A network element as claimed in claim 7, characterized in that the phase-comparing device (37) includes at least one counting device (21, 22) and a control device (20) for reading from the counting device (21, 22) at regular time intervals and then resetting the counting device.
10. A network element as claimed in claim 9, characterized in that the counting device (21, 22) is a 16-stage counter.
11. A network element for a digital transmission system, comprising at least one interface unit (2, 3, 4) which includes a device (5) for converting an incoming optical signal of a first clock frequency (Te) to a corresponding electric signal of the same clock frequency (Te), characterized in that the interface unit (2) further includes a synchronization-monitoring device (6) for comparing the first clock frequency (Te) with a second clock frequency (Ti) of a signal fixed in the network element (1) for obtaining a difference value signal (33), said synchronization monitoring device further evaluating said difference value signal statistically at fixed time intervals to provide at least one statistical synchronization status parameter signal.
12. A network element as claimed in claim 11, characterized in that the synchronization-monitoring device (6) comprises a phase-comparing device (37) for said comparing the first clock frequency (Te) with the second clock frequency (Ti) within a predetermined time interval for providing a difference value signal (33), a memory device (25) for storing said difference value signal, and an evaluating device (26) for evaluating said value signal read from the memory device at predetermined time intervals for providing said synchronization status parameter signal comprising at least one interface unit (2, 3, 4) which includes a device (5) for converting an incoming optical signal of a first clock frequency (Te) to a corresponding electric signal of the same clock frequency (Te), characterized in that the interface unit (2) further includes a synchronizationmonitoring device (6) for comparing the first clock frequency (Te) with a second clock frequency (Ti) of a signal fixed in the network element (1) for obtaining a difference value signal (33); said synchronization monitoring device further evaluating said difference value signal statistically at fixed time intervals to provide at least one statistical synchronization status parameter signal.
13. A network element as claimed in claim 11, characterized in that the phase-comparing device (37) includes at least one counting device (21, 22) and a control device (20) for reading from the counting device (21, 22) at regular time intervals and then resetting the counting device.
14. A network element as claimed in claim 13, characterized in that the counting device (21, 22) is a 16-stage counter.
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US6314150B1 (en) * 1997-05-15 2001-11-06 Infineon Technologies Ag Lock detector circuit for a phase-locked loop
US20010038476A1 (en) * 1999-12-11 2001-11-08 Michael Wolf Synchronous digital communications system
US20020018261A1 (en) * 1999-10-28 2002-02-14 Koji Takeguchi Transmission system
US20020064184A1 (en) * 1999-05-28 2002-05-30 Toshiaki Kinoshita SDH transmission apparatus and frame timing re-clocking method for SDH transmission apparatus
US6542832B1 (en) * 1999-08-18 2003-04-01 Fisher Controls International, Inc. Error detection and correction system for use with dual-pulse output metering devices
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US6741812B2 (en) 1999-12-11 2004-05-25 Alcatel Synchronous digital communications system
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US8451731B1 (en) 2007-07-25 2013-05-28 Xangati, Inc. Network monitoring using virtual packets
US8645527B1 (en) 2007-07-25 2014-02-04 Xangati, Inc. Network monitoring using bounded memory data structures
US9961094B1 (en) * 2007-07-25 2018-05-01 Xangati, Inc Symptom detection using behavior probability density, network monitoring of multiple observation value types, and network monitoring using orthogonal profiling dimensions
US8639797B1 (en) 2007-08-03 2014-01-28 Xangati, Inc. Network monitoring of behavior probability density
US10992555B2 (en) 2009-05-29 2021-04-27 Virtual Instruments Worldwide, Inc. Recording, replay, and sharing of live network monitoring views
EP2521292A1 (en) * 2011-05-06 2012-11-07 ADVA AG Optical Networking Clock monitoring in a synchronous network
US9021291B2 (en) 2011-05-06 2015-04-28 Adva Optical Networking Se Synchronous network
CN103916181A (en) * 2012-12-31 2014-07-09 于佳亮 Method for detecting SDH optical transmission network frequency synchronization performance
CN103916181B (en) * 2012-12-31 2017-04-19 于佳亮 Method for detecting SDH optical transmission network frequency synchronization performance
US11018506B2 (en) * 2018-07-25 2021-05-25 Hangzhou Vango Technologies, Inc. Smart grid timing synchronization method, system, device and computer readable storage medium

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CA2162824A1 (en) 1996-05-31

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