US20220285526A1 - Method of making heteroepitaxial structures and device formed by the method - Google Patents

Method of making heteroepitaxial structures and device formed by the method Download PDF

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US20220285526A1
US20220285526A1 US17/752,228 US202217752228A US2022285526A1 US 20220285526 A1 US20220285526 A1 US 20220285526A1 US 202217752228 A US202217752228 A US 202217752228A US 2022285526 A1 US2022285526 A1 US 2022285526A1
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silicon
pedestal
layer
seed area
top surface
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Steven R.J. Brueck
Stephen D. Hersee
Seung-Chang Lee
Daniel Feezell
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UNM Rainforest Innovations
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UNM Rainforest Innovations
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Definitions

  • the present disclosure is directed to a method for making a heteroepitaxial structure and devices formed by the method.
  • the integrated circuit industry has a long history of “Moore's law” scaling of silicon transistors from dimensions of over 10 microns to today's 22 nm generation. In the current 22 nm generation the industry has moved to a FinFET or tri-gate structure in which the gate is wrapped around three sides of the silicon channel to provide improved electrostatic control of the carriers.
  • CMOS circuits While further scaling is proceeding, the channel in the latest Intel tri-gate transistor is only about 20 atoms wide, so the end to scaling is clearly on the horizon.
  • the industry has identified several directions for continuing the evolution of CMOS circuits.
  • One direction that is being actively investigated is the use of higher mobility materials such as III-V semiconductors, III-N materials and Ge for the transistor channel.
  • Another alternative is the use of vertical transistors with wrap-around (gate all around) geometries, again all of the same material classes are being investigated.
  • Heteroepitaxial growth of different semiconductor and dielectric materials directly on Si(001) is another approach.
  • the main issues are defects associated with the lattice and thermal expansion mismatches between the foreign material and the Si. For large area growths, these issues give rise to dislocations and can cause cracking of the foreign film.
  • a thick buffer layer is grown to mitigate these effects and reduce the defects between the substrate and the active layer. While there has been some success with this approach, it is not compatible with integration on the very small scales of today's silicon integrated circuits.
  • An embodiment of the present disclosure is directed to a method for making a heteroepitaxial layer.
  • the method comprises providing a semiconductor substrate.
  • a seed area delineated with a selective growth mask is formed on the semiconductor substrate.
  • the seed area comprises a first material and has a linear surface dimension of less than 100 nm.
  • a heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material.
  • the device comprises a semiconductor substrate and a seed area delineated with a selective growth mask on the semiconductor substrate.
  • the seed area comprises a first material and a linear surface dimension of less than 100.
  • a heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material.
  • Another embodiment of the present disclosure is directed to a method for making a heteroepitaxial layer.
  • the method comprises providing a semiconductor substrate.
  • a nanostructured pedestal is formed on the semiconductor substrate, the pedestal having a top surface and a side surface.
  • the top surface forms a seed area having a linear surface dimension that ranges from about 10 nm to about 100 nm.
  • a selective growth mask layer is provided on the top surface and side surface of the pedestal. A portion of the selective growth mask layer is removed to expose the seed area of the pedestal.
  • An epitaxial layer is grown on the seed area.
  • Still another embodiment of the present disclosure is directed to a heteroepitaxial nanostructure.
  • the heteroepitaxial nanostructure comprises a substrate.
  • a pedestal is formed on the substrate, the pedestal having a top surface and a side surface.
  • the top surface comprises a seed area.
  • a heteroepitaxial layer is grown on the seed area of the pedestal, the seed area having a linear surface dimension that ranges from about 10 nm to about 100 nm.
  • FIGS. 1A-E illustrate a method for making a heteroepitaxial layer, according to an embodiment of the present disclosure.
  • FIGS. 2A-2F illustrate a method for making heteroepitaxial layers, according to another embodiment of the present disclosure.
  • FIG. 3 illustrates a top view of a mask employed in an embodiment of the present disclosure.
  • FIG. 4 illustrates a device structure comprising heteroepitaxially grown layers, according to an embodiment of the present disclosure.
  • FIGS. 5A-5B illustrate a schematic view of growth mask directly on a 2D substrate surface, according to an embodiment of the present disclosure.
  • FIGS. 6A-6B illustrate a schematic view of growth mask flush with silicon pedestals, according to an embodiment of the present disclosure.
  • FIGS. 7A-7B illustrate a schematic view of a growth mask extending beyond silicon pedestals, according to an embodiment of the present disclosure.
  • FIGS. 8A-8B illustrate a schematic view of silicon pedestals extending beyond growth mask, according to an embodiment of the present disclosure.
  • FIGS. 9A-9B illustrate a schematic view of non-faceted silicon pedestals extending beyond growth mask, according to an embodiment of the present disclosure.
  • FIG. 10 illustrates an isometric projection of a heterostructure FinFET showing an isolation layer, the source, gate and drain contacts labeled S, G and D respectively, according to an embodiment of the present disclosure.
  • FIG. 11 illustrates an isometric projection of a heterstructure FinFET with a dielectric isolation (shown as semi-transparent for clarity), according to an embodiment of the present disclosure.
  • FIG. 12 illustrates a layered heterostructure for channel region of a device, according to an embodiment of the present disclosure.
  • FIGS. 13-14 illustrate schematic views of vertical nanowire transistors grown seed areas, according to an embodiment of the present disclosure.
  • the present application is directed to devices and methods for forming devices in which a seed area for heteroepitaxial growth is formed on a semiconductor substrate.
  • the seed area comprises a two-dimensional area with at least one dimension less than about 100 nm.
  • the seed area comprises a linear surface dimension that ranges from about 10 nm to about 100 nm.
  • seed areas having heteroepitaxial structures with linear surface dimensions less than 20 or 25 nm can be employed.
  • a heteroepitaxial layer comprising a second material that is different from the first material can be grown using the seed area to nucleate the epitaxial growth.
  • the term “linear surface dimension” can refer to any linear dimension of the surface of the seed area, such as, for example, a width or diameter.
  • Employing seed areas having relatively small dimensions in the manner disclosed herein can have one or more of the following benefits: the ability to form heteroepitaxial structures with reduced numbers of defects compared with larger area heteroepitaxial layers; the ability to form heteroepitaxial structures with zero or substantially zero defects; the ability to form heteroepitaxial pillar structures that are flexible and/or that can accommodate strain better than heteroepitaxial layers grown on a planar substrate surface; or the ability to form small area heteroepitaxial films that can accommodate strain better than heteroepitaxial layers grown on a large area of a substrate surface.
  • the nanoscale heteroepitaxial growth of the present disclosure can exploit the greatly improved materials quality that occurs when the substrate, such as, for example a silicon fin, is nanoscale in lateral size.
  • the substrate such as, for example a silicon fin
  • the heteroepitaxial techniques and devices of the present disclosure can take advantage of the evolution of integrated circuits.
  • the dimensions of a growth area are reduced to below the average scale to nucleate a defect such as a threading dislocation, it is possible to grow heterogeneous materials without nucleating either threading dislocations or antisite defects (boundaries where two grains of the zinc-blende III-V crystal are misoriented by 180°).
  • the scale for this defect free growth is that at least one linear dimension of the growth area be much less than the mean distance between defects in a large area heteroepitaxial growth. In an embodiment, dimensions of about 100 nm or less can be employed, such as, for example, about 10 to about 20 nm.
  • the table below gives some typical dislocation densities and the corresponding average distance between dislocations. Note that to be suitable for silicon electronics, the incidence of threading dislocations that impact the electrical properties of an individual channel can be exceedingly low. Today's microprocessors contain as many as 3,000,000,000 transistors, and perhaps as many as 30,000,000,000 channels. With continued Moore's law scaling, this number will continue to climb exponentially. The allowed number of defected channels can be a very small fraction of the total number of channels.
  • the prospects for defect-free nanoscale growth are further improved by the migration of silicon integrated circuits to FinFET architectures.
  • the FinFET pedestal In contrast to the growth in a simple opening atop a bulk substrate, the FinFET pedestal is significantly more compliant, e.g. it can share the strain (lattice displacement) associated with the lattice mismatch stress with the growing film.
  • Control of strain in MOSFET channels is an important aspect of modern integrated circuit manufacturing since the strain directly impacts the electronic properties of the material.
  • Nanoscale growth provides additional approaches to controlling this strain in the FinFET channel by adjusting the dimensions of the “fin” and the thickness and layer structure of the grown material.
  • FIG. 1A-E illustrate a method for making a heteroepitaxial layer, according to an embodiment of the present disclosure.
  • the method comprises providing a substrate 10 .
  • suitable substrates include silicon wafers, silicon-on-insulator substrates, or other materials used as semiconductor substrates. Suitable substrates are commercially available and are well known in the art.
  • the semiconductor substrate comprises silicon having a (001) facet exposed for processing.
  • the cross-sections of substrate 10 shown in the figures herein can have the ⁇ 110> direction oriented into the paper.
  • Nanostructured pedestals 12 are formed on the substrate.
  • the Nanostructured pedestals 12 are comprised of any suitable material capable of acting as a seed layer for subsequent epitaxial growth.
  • suitable materials include doped or undoped single crystal silicon.
  • Other suitable materials include single crystal III-V materials, such as GaAs and GaSb, which are common substrate materials in photonics and high-speed electronics; and single crystal GaN, sapphire and SiC. Any other single crystal material that provides a suitable nucleation surface for the desired epitaxial growth can be employed.
  • the pedestals 12 can be formed from the same material as the substrate, where the substrate is a single crystal material. In other embodiments, the pedestals can be a different material form the substrate. Any desired technique for forming the single crystal pedestals can be used.
  • Such techniques include various methods for patterning and etching the substrate surface. Suitable techniques are well known in the art. For purposes of strain relief as discussed below, it is useful to have the pedestals roughly as high or higher as the smallest in-plane dimension of the seed area.
  • a selective growth mask layer 14 is provided on a top surface and side surface of the pedestal.
  • the selective growth mask layer 14 can be provided over the entire perimeter of the sidewall surface.
  • selective growth mask layer 14 is formed on at least three sides of the pedestal, including the top surface and front and back sidewalls of a pedestal. Any suitable technique for forming the selective growth mask layer, such as oxidation of the semiconductor substrate surface, or deposition of material onto the surface, can be employed. Suitable methods for forming selective growth masks are well known in the art.
  • a portion of the selective growth mask layer 14 is removed to expose at least the top surface 16 of the pedestal 12 .
  • Various suitable methods can be employed to selectively remove the top portion of selective growth mask layer 14 . Examples include anisotropically etching to selectively remove the selective growth mask layer from the top surface of the pedestal; or formation of a non-conformal layer, such as by depositing and reflowing a layer followed by an etch back process. The etch back process can employ polishing, such as chemical mechanical polishing. Yet other examples of techniques for removing a portion of selective growth mask layer 14 will be discussed in greater detail below with respect to the method of FIG. 2 .
  • the semiconductor material of pedestal 12 can optionally be selectively etched back, as shown in FIG. 1D .
  • the selective etch back remaining portions of the selective growth mask layer 14 form sidewall barriers 18 .
  • the sidewall barriers 18 can act to block defects, such as stacking faults that propagate, for example, along (111) directions (e.g., at an angle to the top surface).
  • the remaining portion of pedestal 12 comprises a (001) facet of silicon material exposed at the pedestal top surface.
  • an epitaxial layer is grown on the remaining portion of pedestal 12 .
  • the exposed top surface of pedestal 12 provides a seed area for the epitaxial growth.
  • the seed area can have at least one dimension that is less than about 100 nm.
  • Example configurations for the seed area include a rectangular area having with a width dimension ranging from about 10 nm to about 100 nm and a length dimension ranging from about 200 nm to about 2000 nm; or a circular area having a diameter ranging from, for example, about 10 nm to about 100 nm.
  • the heteroepitaxial layer comprises a Group III-V semiconductor material.
  • Group III-V semiconductor materials include nitrogen-based materials, such as gallium nitride or other Group III-N semiconductors, such as AlGaN, indium nitride (InN), and indium gallium nitride (In x Ga 1-x N).
  • Group III-V semiconductor materials include InAs and InAsSb, which have significantly higher electron mobilities and saturation velocities in comparison with Si. The techniques described also apply to semiconductor materials other than III-V materials, such as Ge.
  • the growth of the epitaxial layer is directed by the seed area of the nanostructured pedestal surface.
  • Epitaxial growth copies the underlying crystal structure of the substrate, e.g., atoms line up as if they are a continuation of the starting crystal structure.
  • the grown film might have the same symmetry as the seed area, but a different natural distance between atoms (this is the lattice mismatch mentioned above).
  • FIG. 1E illustrates an example of a heteroepitaxial nanostructure.
  • the nanostructure comprises the remaining pedestal 12 having a nano-dimensional top surface and a side surface; and the epitaxial layer 20 grown on the nano-dimensional top surface of the pedestal.
  • the remaining selective growth mask layer 14 extends above the surface of the pedestal 12 to form sidewall barriers 18 .
  • the epitaxial layer 20 can grow between and above the sidewall barriers 18 , at which point the width dimensions of the heteroepitaxial layer nanostructure may increase to overlap the insulator, as shown, for example, in FIG. 1E . Additional growth can result in further enlargement of the heteroepitaxial layer as desired.
  • FIGS. 2A-2F illustrate a method for making heteroepitaxial layers, according to another embodiment of the present disclosure.
  • the substrate 10 is a silicon substrate.
  • Pedestals 12 are formed by employing an etch mask 22 .
  • the etch mask can have width or diameter dimensions of about 1 micron or less.
  • FIG. 3 illustrates a top view, showing the etch mask 22 used to pattern the substrate.
  • any other suitable shaped pattern can be employed, such as masks for forming square or rectangle features.
  • the etch mask 22 can be any suitable mask type, such as a patterned photoresist layer or hard mask formed of, for example, silicon oxide.
  • the silicon substrate can be patterned by etching to form the pedestal 12 , as illustrated in FIG. 2B .
  • Any suitable etching process can be employed that will form the desired pedestal shape. In an embodiment, a dry etching process is employed.
  • the etch mask 22 can be removed.
  • thermal oxidation can then be carried out to form a selective growth mask layer 14 of silicon dioxide to a desired thickness.
  • the thermal oxidation process consumes the substrate material, so that the thicker the silicon dioxide layer, the smaller the resulting width dimension of the final pedestal 12 .
  • the thickness of the silicon dioxide can be varied so that the diameter or width of the silicon pedestal 12 is reduced to any desired size dimension.
  • Example width dimensions can be the same as those discussed above for FIG. 1 .
  • the pedestal 12 can be patterned to the desired final dimension during the etching step; followed by forming a selective growth mask layer to delineate the seed area by a process that does not consume the silicon to reduce the dimensions of the pedestal 12 .
  • a non-conformal layer 24 is formed over the pedestal 12 and selective growth mask layer 14 .
  • Any suitable type of non-conformal layer can be employed.
  • suitable non-conformal layers include doped silicon oxides, spin-on-glass, photoresist or other materials that can be deposited in liquid form, reflowed, polished or otherwise planarized to reduce surface topography. Suitable non-conformal layers are well known in the art.
  • the non-conformal layer can be etched back until the selective growth mask layer 14 at the top of the pedestal 12 is exposed, as illustrated in FIG. 2E .
  • the exposed portion of selective growth mask layer 14 can be removed by the same or a different etch process as is used to etch back the non-conformal layer 24 .
  • the remaining portion of the non-conformal layer 24 can then be removed if desired, such as where the non-conformal layer is a polymer.
  • the pedestal top surface can be used without further processing as a seed area for heteroepitaxial growth, if desired.
  • a single crystal semiconductor grows on the seed area 26 that is shown exposed in FIG. 2E .
  • a further selective etch back of the seed material of pedestal 12 can be carried out to form the sidewall barriers 18 prior to epitaxial growth, as illustrated in FIG. 2F .
  • the etch back of the seed material can be performed by any suitable selective etch process, such as a dry etching process.
  • Heteroepitaxial growth is then carried out between the sidewall barriers 18 .
  • Sidewall barriers 18 can block the propagation of defects, such as stacking faults and misfit dislocations, from the upper region of the heteroepitaxial layer.
  • the resulting structure is shown in FIG. 4 , according to an embodiment of the present disclosure.
  • the epitaxy conditions such as temperature and the ratio of precursor gases, can be controlled to allow for formation of a planar epitaxial layer surface.
  • a planar GaN(001) facet at the top of GaN epi-layer can be grown using appropriate growth conditions.
  • One of ordinary skill in the art would be able to determine the desired conditions without undue experimentation.
  • the pedestal structures of the present disclosure can provide one or more of the following benefits: formation of heteroepitaxial materials with reduced defects; the selective growth mask layer 14 can prevent or reduce nucleation at the pedestal sidewalls, thereby isolating the nucleation during epitaxy to the top facet of the pedestal; pedestals can provide increased flexibility and/or the silicon pedestal structure can help relieve strain resulting from the lattice mismatch between the pedestal and the epitaxial material grown thereon.
  • FIGS. 5A and 5B illustrate a semiconductor substrate 10 comprising a surface masked with any suitable selective growth mask 50 for patterning the seed areas 26 .
  • the mask 50 can be relatively thin compared to the thickness of the subsequently formed and fully-grown heteroepitaxial layer that is formed on seed areas 26 .
  • a similar embodiment is contemplated that employs a thick growth mask 50 to prevent lateral overgrowth. Again, the term thick is relative to the thickness of the fully-grown heteroepitaxial layer subsequently grown on seed areas 26 .
  • suitable growth masks include SiO 2 , Si 3 N 4 or combinations thereof.
  • the dimensions of the seed area can be any of the seed area dimensions described herein. In an embodiment, seed area dimensions in the substrate plane are ⁇ 10 nm wide by ⁇ 40 nm long. Similar dimensions can be employed for any of the seed areas illustrated in the embodiments of FIGS. 6-9 .
  • FIGS. 6A and 6B illustrate an embodiment comprising semiconductor pedestals, or plateaus, protruding from the substrate 10 to form the seed areas 26 .
  • Mask 50 can be any appropriate growth mask such as SiO 2 , Si 3 N 4 or combinations thereof, that is arranged to be more or less flush with the top surface of the seed areas 26 .
  • FIGS. 7A and 7B comprise semiconductor pedestals, or plateaus, protruding from the substrate 10 to form the seed areas 26 of the present disclosure, according to an embodiment of the present disclosure.
  • Mask 50 is formed to be higher than the top of seed areas 26 .
  • FIGS. 8A and 8B illustrate an alternative embodiment in which the growth mask 50 is lower than the top of seed areas 26 , thereby allowing heteroepitaxial growth on the top and sides of the pedestals.
  • FIGS. 9A and 9B illustrate an approach in which non-faceted pedestals protrude from the substrate, according to an embodiment of the present disclosure.
  • the mask 50 can be thinner than the top surface of seed areas 26 , thereby allowing growth on the top and sides of the pedestals, similar to the embodiment illustrated in FIG. 8A .
  • the seed areas can comprise any of the semiconductor materials described for seed areas in the present disclosure; and the materials subsequently grown thereon can comprise any of the heteroepitaxial grown semiconductors described herein.
  • the mask 50 can be any of the mask materials described herein.
  • FIG. 10 illustrates an isometric projection of a FET device 70 that can be formed using heteroepitaxial layer structures, according to an embodiment of the present disclosure.
  • Pedestal 12 can be formed using any suitable process, such as with a masking layer to prevent growth on the sidewalls of the pedestal. In an embodiment, a growth mask such as that shown in FIG. 7A can be used.
  • the silicon pedestal 12 is shown with sloping sidewalls, but could have any other desired shape.
  • heteroepitaxial growth proceeds from the exposed semiconductor surface, or seed area, of pedestal 12 .
  • the seed area surface can comprise any suitable material, including any seed area materials discussed herein.
  • the seed area surface is a Si(001) surface.
  • An isolation layer 72 can be grown on the seed area. Isolation layer 72 can be, for example, a large bandgap material, to prevent leakage of carriers from the channel into the silicon. As noted above, isolation layer 72 can also be a layer, such as an Al 0.98 Ga 0.02 As layer, that is easily oxidized following the growth to provide additional isolation.
  • An alternative strategy is to dope the silicon so that it forms a p-n junction with the channel material, also reducing leakage of carriers into the silicon. Depending on the details of the bandgap alignment between the channel material and the silicon, isolation layer 72 may or may not be necessary.
  • a layer such as but not restricted to, a high Al concentration AlGaAs layer, which can be selectively oxidized during the device processing subsequent to growth of the heteroepitaxial layer.
  • This allows epitaxial growth while at the same time providing the advantages of a semiconductor-on-oxide structure where the carriers are strongly confined to the channel.
  • the aluminum oxide layer can be selectively removed to provide access for a gate-all-around configuration. Examples of this technique are described in U.S. Provisional Patent Application 61/752,741, entitled Gate-All-Around Metal-Oxide-Semiconductor Transistors with Gate Oxides, filed Jan. 15, 2013, the disclosure of which is hereby incorporated herein by reference in its entirety.
  • Channel layer 74 is grown.
  • Channel layer 74 is a heteroepitaxial layer and can comprise any suitable materials discussed herein for heteroepitaxial growth.
  • the bandgap engineering that is common in III-V devices can be used in devices of the present disclosure to, for example, grow higher bandgap cladding layers below and above the active channel layer. This can shield the carriers in the channel from surface defects and reduces scattering and improves carrier mobilities, saturation velocities, and lifetimes.
  • channel layer 74 can comprise several layers.
  • channel layer 74 can comprise a GaAs/InGaAs/GaAs structure in which the high mobility InGaAs material is clad with upper and lower high bandgap materials to shield the carriers from the higher point defect densities at the interface with the pedestal 12 or isolation layer and at the top surface of the growth.
  • FIG. 12 shows a possible layered heterostructure sequence for the channel layer 74 , according to an embodiment of the present disclosure.
  • This structure takes advantage of bandgap engineering that is well known for III-V devices.
  • the structure comprises a bottom large bandgap material in contact with a pedestal 12 .
  • a bottom cladding functions to keep carriers away from the interface with pedestal 12 .
  • a channel region and a top cladding are formed over the bottom cladding.
  • the channel region and top cladding can optionally be repeated a number of times, as shown, to provide increased current carrying capacity if thin channel regions, such as quantum wells, are desired.
  • doping of the source and drain regions can be carried out. This can include a masked ion implantation followed by an annealing step to activate the impurities. This will modify the growth layers by impurity induced diffusion to lower the resistance of the source-gate-drain transitions.
  • a gate dielectric 76 and source “S”, drain “D” and gate “G” electrodes, as illustrated in FIG. 10 can be formed by any suitable methods. Suitable methods are known in the art.
  • FIG. 11 shows an embodiment where a dielectric spacer 80 is used to planarize the structure following the S/G/D metallization.
  • This layer can be thicker than the finFET and contact holes can be created for contacting the S/G/D, as is well known in the art.
  • Another geometry of interest is a vertical channel.
  • This embodiment lends itself to a gate all around configuration and has the significant advantage that the gate is self-aligned to the nanowires.
  • the gate length can be set by deposition processes which are much more controllable than lithography at nm dimensions. Examples of vertical MOSFETS are described in U.S. Pat. No. 8,344,361, the disclosure of which is hereby incorporated by reference in its entirety.
  • the '361 patent does not explicitly discuss heterostructure growth from a silicon substrate, and is primarily about forming two and three terminal devices.
  • FIGS. 13 and 14 illustrate a process for forming high mobility channel vertical transistors based on nanowire growth from nanoscale Si seeds.
  • the seed area can have a linear surface dimension of 100 nm or less, such as 20 or 25 nm or less, or about 10 nm.
  • the concept proceeds in a source down configuration.
  • the alternative drain down configuration is also available, as would be understood by one of ordinary skill in the art.
  • the heteroepitaxial growth starts from Si(001) pedestals 12 that can have any desired shape, such as square or round cross-sections, or extended into walls (e.g., a length dimension that is many times larger than the width dimension, such as 5, 10 or 100 times or more).
  • An optional isolation layer 72 is first grown to isolate the source from the Si material. Since the source region 82 is adjacent to the silicon in a source down embodiment, and a good contact can be provided, leakage into the silicon is not as important to the device performance as it was for the horizontal devices where the gate region was in direct contact with the silicon substrate material. Doping can be varied during the epitaxial growth to provide heavy doping in the source and drain regions 82 , 84 and reduced doping in the gate region 86 .
  • the de-lineation of the source/gate/drain regions of the nanowires refers to doping levels during the growth.
  • the vertical devices are shown in parallel, e.g. all source, gate and drain contacts are connected to the same metallization. In an actual circuit, only some of the devices will be connected in parallel to provide current carrying capability; other devices would form the channels of different transistors in accordance with the circuit design.
  • a dielectric layer 90 is provided to isolate the silicon followed by formation of the source contact layer 92 .
  • Appropriate annealing processes can be employed to assure good contact to the source regions of the nanowires. While all of the sources are shown connected in parallel; in practice, one or more of the nanowires will be in parallel to provide current carrying capability and others will be incorporated into different transistors as dictated by the circuit design.
  • a field dielectric layer 94 can be deposited to isolate the gate contact 96 from the source contact 92 . Initially, the field dielectric layer 94 can stop just short of the gate region to allow for oxidation of the nanowire to provide the gate dielectric 98 . The field dielectric 94 can then be continued to the middle of the gate region and gate contact 96 is provided.
  • gate contact 96 Following formation of gate contact 96 , additional field dielectric 100 can be deposited on top of the gate contact to completely cover the nanowires 88 . Then an etch back step can be carried out to expose the top of the drain regions and a drain contact 102 is provided. Additional processing can be used to define the various transistors and interconnections, as is the case in traditional integrated circuit manufacturing. There can be many variants on this basic process. For example, the gate oxide layer can be removed from the sidewall of the drain region and contact made using this sidewall in place of the top contact shown.

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Abstract

A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed.

Description

    RELATED APPLICATIONS
  • This application is a continuation of U.S. patent application Ser. No. 16/747,765 filed Jan. 21, 2020, which is a continuation of U.S. patent application Ser. No. 16/162,787, filed Oct. 17, 2018, which is a continuation of U.S. patent application Ser. No. 14/830,241, filed Aug. 19, 2015, now U.S. Pat. No. 10,141,418, which is a divisional of U.S. patent application Ser. No. 13/944,808, filed Jul. 17, 2013, now U.S. Pat. No. 9,142,400, which claims priority under 35 U.S.C. 119 to provisional application No. 61/672,713 filed Jul. 17, 2012, all of which applications are herein incorporated by reference in their entireties.
    • FEDERALLY SPONSORED RESEARCH
  • This invention was made with government support under Contract No. EEC-0812056 awarded by the National Science Foundation (NSF) and/or contract No. HDTRA1-11-1-0021 awarded by DTRA. The U.S. Government has certain rights in this invention.
    • FIELD OF THE DISCLOSURE
  • The present disclosure is directed to a method for making a heteroepitaxial structure and devices formed by the method.
    • BACKGROUND
  • The integrated circuit industry has a long history of “Moore's law” scaling of silicon transistors from dimensions of over 10 microns to today's 22 nm generation. In the current 22 nm generation the industry has moved to a FinFET or tri-gate structure in which the gate is wrapped around three sides of the silicon channel to provide improved electrostatic control of the carriers.
  • While further scaling is proceeding, the channel in the latest Intel tri-gate transistor is only about 20 atoms wide, so the end to scaling is clearly on the horizon. The industry has identified several directions for continuing the evolution of CMOS circuits. One direction that is being actively investigated is the use of higher mobility materials such as III-V semiconductors, III-N materials and Ge for the transistor channel. Another alternative is the use of vertical transistors with wrap-around (gate all around) geometries, again all of the same material classes are being investigated.
  • This evolution to heterostructure transistor structures requires new manufacturing approaches. Two principle directions are being investigated: wafer bonding; and heterostructure materials growth. In wafer bonding, the non-silicon materials are grown on their conventional substrates with the inclusion of a separation layer. Following the growth, the epitaxial material is bonded to a silicon wafer and selective etching is used to separate the original substrate. Films of only a few nm thickness have been transferred with this approach. Since the non-silicon material is grown using well established technologies, the issues of lattice mismatch and defects are largely controlled. However, this is a complex technology and is far from manufacturing worthy for the large area silicon substrates (today 300 nm diameter migrating to 450 nm diameter) used by the silicon integrated circuit industry. Thermal expansion mismatch issues (the expansion coefficients of the III-V materials and the Si substrate are different) remain.
  • Heteroepitaxial growth of different semiconductor and dielectric materials directly on Si(001) is another approach. The main issues are defects associated with the lattice and thermal expansion mismatches between the foreign material and the Si. For large area growths, these issues give rise to dislocations and can cause cracking of the foreign film. Traditionally a thick buffer layer is grown to mitigate these effects and reduce the defects between the substrate and the active layer. While there has been some success with this approach, it is not compatible with integration on the very small scales of today's silicon integrated circuits.
    • SUMMARY
  • An embodiment of the present disclosure is directed to a method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material.
  • Another embodiment of the present disclosure is directed to a device. The device comprises a semiconductor substrate and a seed area delineated with a selective growth mask on the semiconductor substrate. The seed area comprises a first material and a linear surface dimension of less than 100. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material.
  • Another embodiment of the present disclosure is directed to a method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A nanostructured pedestal is formed on the semiconductor substrate, the pedestal having a top surface and a side surface. The top surface forms a seed area having a linear surface dimension that ranges from about 10 nm to about 100 nm. A selective growth mask layer is provided on the top surface and side surface of the pedestal. A portion of the selective growth mask layer is removed to expose the seed area of the pedestal. An epitaxial layer is grown on the seed area.
  • Still another embodiment of the present disclosure is directed to a heteroepitaxial nanostructure. The heteroepitaxial nanostructure comprises a substrate. A pedestal is formed on the substrate, the pedestal having a top surface and a side surface. The top surface comprises a seed area. A heteroepitaxial layer is grown on the seed area of the pedestal, the seed area having a linear surface dimension that ranges from about 10 nm to about 100 nm.
  • It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present teachings, as claimed.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawing, which is incorporated in and constitutes a part of this specification, illustrates an embodiment of the present teachings and together with the description, serves to explain the principles of the present teachings.
  • FIGS. 1A-E illustrate a method for making a heteroepitaxial layer, according to an embodiment of the present disclosure.
  • FIGS. 2A-2F illustrate a method for making heteroepitaxial layers, according to another embodiment of the present disclosure.
  • FIG. 3 illustrates a top view of a mask employed in an embodiment of the present disclosure.
  • FIG. 4 illustrates a device structure comprising heteroepitaxially grown layers, according to an embodiment of the present disclosure.
  • FIGS. 5A-5B illustrate a schematic view of growth mask directly on a 2D substrate surface, according to an embodiment of the present disclosure.
  • FIGS. 6A-6B illustrate a schematic view of growth mask flush with silicon pedestals, according to an embodiment of the present disclosure.
  • FIGS. 7A-7B illustrate a schematic view of a growth mask extending beyond silicon pedestals, according to an embodiment of the present disclosure.
  • FIGS. 8A-8B illustrate a schematic view of silicon pedestals extending beyond growth mask, according to an embodiment of the present disclosure.
  • FIGS. 9A-9B illustrate a schematic view of non-faceted silicon pedestals extending beyond growth mask, according to an embodiment of the present disclosure.
  • FIG. 10 illustrates an isometric projection of a heterostructure FinFET showing an isolation layer, the source, gate and drain contacts labeled S, G and D respectively, according to an embodiment of the present disclosure.
  • FIG. 11 illustrates an isometric projection of a heterstructure FinFET with a dielectric isolation (shown as semi-transparent for clarity), according to an embodiment of the present disclosure.
  • FIG. 12 illustrates a layered heterostructure for channel region of a device, according to an embodiment of the present disclosure.
  • FIGS. 13-14 illustrate schematic views of vertical nanowire transistors grown seed areas, according to an embodiment of the present disclosure.
    •
  • It should be noted that some details of the figure have been simplified and are drawn to facilitate understanding of the embodiments rather than to maintain strict structural accuracy, detail, and scale.
    • DESCRIPTION OF THE EMBODIMENTS
  • Reference will now be made in detail to embodiments of the present teachings, examples of which are illustrated in the accompanying drawing. In the drawings, like reference numerals have been used throughout to designate identical elements. In the following description, reference is made to the accompanying drawing that forms a part thereof, and in which is shown by way of illustration a specific exemplary embodiment in which the present teachings may be practiced. The following description is, therefore, merely exemplary.
  • The present application is directed to devices and methods for forming devices in which a seed area for heteroepitaxial growth is formed on a semiconductor substrate. The seed area comprises a two-dimensional area with at least one dimension less than about 100 nm. In an embodiment, the seed area comprises a linear surface dimension that ranges from about 10 nm to about 100 nm. In another embodiment, seed areas having heteroepitaxial structures with linear surface dimensions less than 20 or 25 nm can be employed. A heteroepitaxial layer comprising a second material that is different from the first material can be grown using the seed area to nucleate the epitaxial growth. In this application, the term “linear surface dimension” can refer to any linear dimension of the surface of the seed area, such as, for example, a width or diameter.
  • Employing seed areas having relatively small dimensions in the manner disclosed herein can have one or more of the following benefits: the ability to form heteroepitaxial structures with reduced numbers of defects compared with larger area heteroepitaxial layers; the ability to form heteroepitaxial structures with zero or substantially zero defects; the ability to form heteroepitaxial pillar structures that are flexible and/or that can accommodate strain better than heteroepitaxial layers grown on a planar substrate surface; or the ability to form small area heteroepitaxial films that can accommodate strain better than heteroepitaxial layers grown on a large area of a substrate surface.
  • The nanoscale heteroepitaxial growth of the present disclosure can exploit the greatly improved materials quality that occurs when the substrate, such as, for example a silicon fin, is nanoscale in lateral size. Thus by using nanoscale heteroepitaxial growth onto, for example, a 10 nm wide silicon area, which is already only ˜20 atoms wide, the heteroepitaxial techniques and devices of the present disclosure can take advantage of the evolution of integrated circuits. When the dimensions of a growth area are reduced to below the average scale to nucleate a defect such as a threading dislocation, it is possible to grow heterogeneous materials without nucleating either threading dislocations or antisite defects (boundaries where two grains of the zinc-blende III-V crystal are misoriented by 180°). The scale for this defect free growth is that at least one linear dimension of the growth area be much less than the mean distance between defects in a large area heteroepitaxial growth. In an embodiment, dimensions of about 100 nm or less can be employed, such as, for example, about 10 to about 20 nm. The table below gives some typical dislocation densities and the corresponding average distance between dislocations. Note that to be suitable for silicon electronics, the incidence of threading dislocations that impact the electrical properties of an individual channel can be exceedingly low. Today's microprocessors contain as many as 3,000,000,000 transistors, and perhaps as many as 30,000,000,000 channels. With continued Moore's law scaling, this number will continue to climb exponentially. The allowed number of defected channels can be a very small fraction of the total number of channels.
  • Typical Threading Average
    Dislocation Distance between
    Material/Substrate Density (cm−2) Dislocations (μm)
    Ge0.23Si0.77/Si(001) 5 × 105 14
    GaAs/Si(001) 1 × 105 3.2
    GaAs/GaAs 1 × 104 100
    InAs/Si(001) 1 × 107 3.2
    GaN/sapphire 1 × 109 0.32
    GaN/SiC 5 × 108 0.45
    GaN/GaN 1 × 106 10
    GaN/Si(111)  1 × 1010 0.1
  • The prospects for defect-free nanoscale growth are further improved by the migration of silicon integrated circuits to FinFET architectures. In contrast to the growth in a simple opening atop a bulk substrate, the FinFET pedestal is significantly more compliant, e.g. it can share the strain (lattice displacement) associated with the lattice mismatch stress with the growing film. Control of strain in MOSFET channels is an important aspect of modern integrated circuit manufacturing since the strain directly impacts the electronic properties of the material. Nanoscale growth provides additional approaches to controlling this strain in the FinFET channel by adjusting the dimensions of the “fin” and the thickness and layer structure of the grown material.
  • FIG. 1A-E illustrate a method for making a heteroepitaxial layer, according to an embodiment of the present disclosure. The method comprises providing a substrate 10. Examples of suitable substrates include silicon wafers, silicon-on-insulator substrates, or other materials used as semiconductor substrates. Suitable substrates are commercially available and are well known in the art. In an embodiment, the semiconductor substrate comprises silicon having a (001) facet exposed for processing. As an example, the cross-sections of substrate 10 shown in the figures herein can have the <110> direction oriented into the paper.
  • Nanostructured pedestals 12 are formed on the substrate. The Nanostructured pedestals 12 are comprised of any suitable material capable of acting as a seed layer for subsequent epitaxial growth. Examples of suitable materials include doped or undoped single crystal silicon. Other suitable materials include single crystal III-V materials, such as GaAs and GaSb, which are common substrate materials in photonics and high-speed electronics; and single crystal GaN, sapphire and SiC. Any other single crystal material that provides a suitable nucleation surface for the desired epitaxial growth can be employed. In an embodiment, the pedestals 12 can be formed from the same material as the substrate, where the substrate is a single crystal material. In other embodiments, the pedestals can be a different material form the substrate. Any desired technique for forming the single crystal pedestals can be used. Examples of such techniques include various methods for patterning and etching the substrate surface. Suitable techniques are well known in the art. For purposes of strain relief as discussed below, it is useful to have the pedestals roughly as high or higher as the smallest in-plane dimension of the seed area.
  • Referring to FIG. 1B, a selective growth mask layer 14 is provided on a top surface and side surface of the pedestal. In an embodiment, the selective growth mask layer 14 can be provided over the entire perimeter of the sidewall surface. In an embodiment, selective growth mask layer 14 is formed on at least three sides of the pedestal, including the top surface and front and back sidewalls of a pedestal. Any suitable technique for forming the selective growth mask layer, such as oxidation of the semiconductor substrate surface, or deposition of material onto the surface, can be employed. Suitable methods for forming selective growth masks are well known in the art.
  • Referring to FIG. 1C, a portion of the selective growth mask layer 14 is removed to expose at least the top surface 16 of the pedestal 12. Various suitable methods can be employed to selectively remove the top portion of selective growth mask layer 14. Examples include anisotropically etching to selectively remove the selective growth mask layer from the top surface of the pedestal; or formation of a non-conformal layer, such as by depositing and reflowing a layer followed by an etch back process. The etch back process can employ polishing, such as chemical mechanical polishing. Yet other examples of techniques for removing a portion of selective growth mask layer 14 will be discussed in greater detail below with respect to the method of FIG. 2.
  • After exposing the top surface of the pedestals 12, the semiconductor material of pedestal 12 can optionally be selectively etched back, as shown in FIG. 1D. As a result of the selective etch back, remaining portions of the selective growth mask layer 14 form sidewall barriers 18. The sidewall barriers 18 can act to block defects, such as stacking faults that propagate, for example, along (111) directions (e.g., at an angle to the top surface).
  • Any suitable process for selectively etching back the pedestal 12 can be employed. Suitable etch back processes are well known in the art. In an embodiment, the remaining portion of pedestal 12 comprises a (001) facet of silicon material exposed at the pedestal top surface.
  • Following the selective etch back, an epitaxial layer is grown on the remaining portion of pedestal 12. The exposed top surface of pedestal 12 provides a seed area for the epitaxial growth. As described above, the seed area can have at least one dimension that is less than about 100 nm. Example configurations for the seed area include a rectangular area having with a width dimension ranging from about 10 nm to about 100 nm and a length dimension ranging from about 200 nm to about 2000 nm; or a circular area having a diameter ranging from, for example, about 10 nm to about 100 nm.
  • In an embodiment, the heteroepitaxial layer comprises a Group III-V semiconductor material. Examples of Group III-V semiconductor materials include nitrogen-based materials, such as gallium nitride or other Group III-N semiconductors, such as AlGaN, indium nitride (InN), and indium gallium nitride (InxGa1-xN). Other examples of Group III-V semiconductor materials include InAs and InAsSb, which have significantly higher electron mobilities and saturation velocities in comparison with Si. The techniques described also apply to semiconductor materials other than III-V materials, such as Ge.
  • The growth of the epitaxial layer is directed by the seed area of the nanostructured pedestal surface. Epitaxial growth copies the underlying crystal structure of the substrate, e.g., atoms line up as if they are a continuation of the starting crystal structure. In the case of heteroepitaxial growth, the grown film might have the same symmetry as the seed area, but a different natural distance between atoms (this is the lattice mismatch mentioned above).
  • FIG. 1E illustrates an example of a heteroepitaxial nanostructure. The nanostructure comprises the remaining pedestal 12 having a nano-dimensional top surface and a side surface; and the epitaxial layer 20 grown on the nano-dimensional top surface of the pedestal. In an embodiment, the remaining selective growth mask layer 14 extends above the surface of the pedestal 12 to form sidewall barriers 18. The epitaxial layer 20 can grow between and above the sidewall barriers 18, at which point the width dimensions of the heteroepitaxial layer nanostructure may increase to overlap the insulator, as shown, for example, in FIG. 1E. Additional growth can result in further enlargement of the heteroepitaxial layer as desired.
  • FIGS. 2A-2F illustrate a method for making heteroepitaxial layers, according to another embodiment of the present disclosure. As illustrated in FIG. 2A, the substrate 10 is a silicon substrate. Pedestals 12 are formed by employing an etch mask 22. The etch mask can have width or diameter dimensions of about 1 micron or less. FIG. 3 illustrates a top view, showing the etch mask 22 used to pattern the substrate. However, any other suitable shaped pattern can be employed, such as masks for forming square or rectangle features. The etch mask 22 can be any suitable mask type, such as a patterned photoresist layer or hard mask formed of, for example, silicon oxide.
  • Using the etch mask 22, the silicon substrate can be patterned by etching to form the pedestal 12, as illustrated in FIG. 2B. Any suitable etching process can be employed that will form the desired pedestal shape. In an embodiment, a dry etching process is employed.
  • Following etching, the etch mask 22 can be removed. In an embodiment, thermal oxidation can then be carried out to form a selective growth mask layer 14 of silicon dioxide to a desired thickness. The thermal oxidation process consumes the substrate material, so that the thicker the silicon dioxide layer, the smaller the resulting width dimension of the final pedestal 12. Thus, the thickness of the silicon dioxide can be varied so that the diameter or width of the silicon pedestal 12 is reduced to any desired size dimension. Example width dimensions can be the same as those discussed above for FIG. 1. Alternatively, the pedestal 12 can be patterned to the desired final dimension during the etching step; followed by forming a selective growth mask layer to delineate the seed area by a process that does not consume the silicon to reduce the dimensions of the pedestal 12.
  • Referring to FIG. 2D, a non-conformal layer 24 is formed over the pedestal 12 and selective growth mask layer 14. Any suitable type of non-conformal layer can be employed. Examples of suitable non-conformal layers include doped silicon oxides, spin-on-glass, photoresist or other materials that can be deposited in liquid form, reflowed, polished or otherwise planarized to reduce surface topography. Suitable non-conformal layers are well known in the art.
  • The non-conformal layer can be etched back until the selective growth mask layer 14 at the top of the pedestal 12 is exposed, as illustrated in FIG. 2E. The exposed portion of selective growth mask layer 14 can be removed by the same or a different etch process as is used to etch back the non-conformal layer 24. The remaining portion of the non-conformal layer 24 can then be removed if desired, such as where the non-conformal layer is a polymer.
  • Once exposed, the pedestal top surface can be used without further processing as a seed area for heteroepitaxial growth, if desired. During epitaxy, a single crystal semiconductor grows on the seed area 26 that is shown exposed in FIG. 2E.
  • Alternatively, a further selective etch back of the seed material of pedestal 12 can be carried out to form the sidewall barriers 18 prior to epitaxial growth, as illustrated in FIG. 2F. The etch back of the seed material can be performed by any suitable selective etch process, such as a dry etching process. Heteroepitaxial growth is then carried out between the sidewall barriers 18. Sidewall barriers 18 can block the propagation of defects, such as stacking faults and misfit dislocations, from the upper region of the heteroepitaxial layer. The resulting structure is shown in FIG. 4, according to an embodiment of the present disclosure.
  • The epitaxy conditions, such as temperature and the ratio of precursor gases, can be controlled to allow for formation of a planar epitaxial layer surface. For example, a planar GaN(001) facet at the top of GaN epi-layer can be grown using appropriate growth conditions. One of ordinary skill in the art would be able to determine the desired conditions without undue experimentation.
  • The pedestal structures of the present disclosure can provide one or more of the following benefits: formation of heteroepitaxial materials with reduced defects; the selective growth mask layer 14 can prevent or reduce nucleation at the pedestal sidewalls, thereby isolating the nucleation during epitaxy to the top facet of the pedestal; pedestals can provide increased flexibility and/or the silicon pedestal structure can help relieve strain resulting from the lattice mismatch between the pedestal and the epitaxial material grown thereon.
  • Still other embodiments are contemplated. FIGS. 5A and 5B illustrate a semiconductor substrate 10 comprising a surface masked with any suitable selective growth mask 50 for patterning the seed areas 26. The mask 50 can be relatively thin compared to the thickness of the subsequently formed and fully-grown heteroepitaxial layer that is formed on seed areas 26. A similar embodiment is contemplated that employs a thick growth mask 50 to prevent lateral overgrowth. Again, the term thick is relative to the thickness of the fully-grown heteroepitaxial layer subsequently grown on seed areas 26. Examples of suitable growth masks include SiO2, Si3N4 or combinations thereof. The dimensions of the seed area can be any of the seed area dimensions described herein. In an embodiment, seed area dimensions in the substrate plane are ˜10 nm wide by ˜40 nm long. Similar dimensions can be employed for any of the seed areas illustrated in the embodiments of FIGS. 6-9.
  • FIGS. 6A and 6B illustrate an embodiment comprising semiconductor pedestals, or plateaus, protruding from the substrate 10 to form the seed areas 26. Mask 50 can be any appropriate growth mask such as SiO2, Si3N4 or combinations thereof, that is arranged to be more or less flush with the top surface of the seed areas 26.
  • FIGS. 7A and 7B comprise semiconductor pedestals, or plateaus, protruding from the substrate 10 to form the seed areas 26 of the present disclosure, according to an embodiment of the present disclosure. Mask 50 is formed to be higher than the top of seed areas 26.
  • FIGS. 8A and 8B illustrate an alternative embodiment in which the growth mask 50 is lower than the top of seed areas 26, thereby allowing heteroepitaxial growth on the top and sides of the pedestals. FIGS. 9A and 9B illustrate an approach in which non-faceted pedestals protrude from the substrate, according to an embodiment of the present disclosure. The mask 50 can be thinner than the top surface of seed areas 26, thereby allowing growth on the top and sides of the pedestals, similar to the embodiment illustrated in FIG. 8A. In any of the embodiments of FIGS. 5 to 9, the seed areas can comprise any of the semiconductor materials described for seed areas in the present disclosure; and the materials subsequently grown thereon can comprise any of the heteroepitaxial grown semiconductors described herein. Similarly, the mask 50 can be any of the mask materials described herein.
  • FIG. 10 illustrates an isometric projection of a FET device 70 that can be formed using heteroepitaxial layer structures, according to an embodiment of the present disclosure. Pedestal 12 can be formed using any suitable process, such as with a masking layer to prevent growth on the sidewalls of the pedestal. In an embodiment, a growth mask such as that shown in FIG. 7A can be used. The silicon pedestal 12 is shown with sloping sidewalls, but could have any other desired shape.
  • In an embodiment, heteroepitaxial growth proceeds from the exposed semiconductor surface, or seed area, of pedestal 12. The seed area surface can comprise any suitable material, including any seed area materials discussed herein. In an embodiment, the seed area surface is a Si(001) surface. An isolation layer 72 can be grown on the seed area. Isolation layer 72 can be, for example, a large bandgap material, to prevent leakage of carriers from the channel into the silicon. As noted above, isolation layer 72 can also be a layer, such as an Al0.98Ga0.02As layer, that is easily oxidized following the growth to provide additional isolation. An alternative strategy is to dope the silicon so that it forms a p-n junction with the channel material, also reducing leakage of carriers into the silicon. Depending on the details of the bandgap alignment between the channel material and the silicon, isolation layer 72 may or may not be necessary.
  • In an embodiment, it is possible to grow a layer, such as but not restricted to, a high Al concentration AlGaAs layer, which can be selectively oxidized during the device processing subsequent to growth of the heteroepitaxial layer. This allows epitaxial growth while at the same time providing the advantages of a semiconductor-on-oxide structure where the carriers are strongly confined to the channel. Additionally, the aluminum oxide layer can be selectively removed to provide access for a gate-all-around configuration. Examples of this technique are described in U.S. Provisional Patent Application 61/752,741, entitled Gate-All-Around Metal-Oxide-Semiconductor Transistors with Gate Oxides, filed Jan. 15, 2013, the disclosure of which is hereby incorporated herein by reference in its entirety.
  • Following the growth of the optional isolation layer, a channel layer 74 is grown. Channel layer 74 is a heteroepitaxial layer and can comprise any suitable materials discussed herein for heteroepitaxial growth. In an embodiment, the bandgap engineering that is common in III-V devices can be used in devices of the present disclosure to, for example, grow higher bandgap cladding layers below and above the active channel layer. This can shield the carriers in the channel from surface defects and reduces scattering and improves carrier mobilities, saturation velocities, and lifetimes.
  • In an embodiment, channel layer 74 can comprise several layers. For example, channel layer 74 can comprise a GaAs/InGaAs/GaAs structure in which the high mobility InGaAs material is clad with upper and lower high bandgap materials to shield the carriers from the higher point defect densities at the interface with the pedestal 12 or isolation layer and at the top surface of the growth.
  • FIG. 12 shows a possible layered heterostructure sequence for the channel layer 74, according to an embodiment of the present disclosure. This structure takes advantage of bandgap engineering that is well known for III-V devices. The structure comprises a bottom large bandgap material in contact with a pedestal 12. A bottom cladding functions to keep carriers away from the interface with pedestal 12. A channel region and a top cladding are formed over the bottom cladding. As is well known in the art, the channel region and top cladding can optionally be repeated a number of times, as shown, to provide increased current carrying capacity if thin channel regions, such as quantum wells, are desired.
  • Following the heteroepitaxial growth step of channel layer 74, doping of the source and drain regions can be carried out. This can include a masked ion implantation followed by an annealing step to activate the impurities. This will modify the growth layers by impurity induced diffusion to lower the resistance of the source-gate-drain transitions. A gate dielectric 76 and source “S”, drain “D” and gate “G” electrodes, as illustrated in FIG. 10, can be formed by any suitable methods. Suitable methods are known in the art.
  • FIG. 11 shows an embodiment where a dielectric spacer 80 is used to planarize the structure following the S/G/D metallization. This layer can be thicker than the finFET and contact holes can be created for contacting the S/G/D, as is well known in the art.
  • Another geometry of interest is a vertical channel. This embodiment lends itself to a gate all around configuration and has the significant advantage that the gate is self-aligned to the nanowires. The gate length can be set by deposition processes which are much more controllable than lithography at nm dimensions. Examples of vertical MOSFETS are described in U.S. Pat. No. 8,344,361, the disclosure of which is hereby incorporated by reference in its entirety. The '361 patent does not explicitly discuss heterostructure growth from a silicon substrate, and is primarily about forming two and three terminal devices.
  • FIGS. 13 and 14 illustrate a process for forming high mobility channel vertical transistors based on nanowire growth from nanoscale Si seeds. The seed area can have a linear surface dimension of 100 nm or less, such as 20 or 25 nm or less, or about 10 nm. For specificity, the concept proceeds in a source down configuration. However, the alternative drain down configuration is also available, as would be understood by one of ordinary skill in the art.
  • As shown, the heteroepitaxial growth starts from Si(001) pedestals 12 that can have any desired shape, such as square or round cross-sections, or extended into walls (e.g., a length dimension that is many times larger than the width dimension, such as 5, 10 or 100 times or more). An optional isolation layer 72 is first grown to isolate the source from the Si material. Since the source region 82 is adjacent to the silicon in a source down embodiment, and a good contact can be provided, leakage into the silicon is not as important to the device performance as it was for the horizontal devices where the gate region was in direct contact with the silicon substrate material. Doping can be varied during the epitaxial growth to provide heavy doping in the source and drain regions 82, 84 and reduced doping in the gate region 86.
  • The de-lineation of the source/gate/drain regions of the nanowires refers to doping levels during the growth. The vertical devices are shown in parallel, e.g. all source, gate and drain contacts are connected to the same metallization. In an actual circuit, only some of the devices will be connected in parallel to provide current carrying capability; other devices would form the channels of different transistors in accordance with the circuit design.
  • Following the growth of the nanowire 88, a dielectric layer 90 is provided to isolate the silicon followed by formation of the source contact layer 92. Appropriate annealing processes can be employed to assure good contact to the source regions of the nanowires. While all of the sources are shown connected in parallel; in practice, one or more of the nanowires will be in parallel to provide current carrying capability and others will be incorporated into different transistors as dictated by the circuit design.
  • Following formation of the source contact 92, a field dielectric layer 94 can be deposited to isolate the gate contact 96 from the source contact 92. Initially, the field dielectric layer 94 can stop just short of the gate region to allow for oxidation of the nanowire to provide the gate dielectric 98. The field dielectric 94 can then be continued to the middle of the gate region and gate contact 96 is provided.
  • Following formation of gate contact 96, additional field dielectric 100 can be deposited on top of the gate contact to completely cover the nanowires 88. Then an etch back step can be carried out to expose the top of the drain regions and a drain contact 102 is provided. Additional processing can be used to define the various transistors and interconnections, as is the case in traditional integrated circuit manufacturing. There can be many variants on this basic process. For example, the gate oxide layer can be removed from the sidewall of the drain region and contact made using this sidewall in place of the top contact shown.
  • Using methods of the present disclosure, growth of the channels and the source and drain regions of transistor structures can be carried out simultaneously. An advantage is that the transitions between the source, channel and drain regions are single crystal material thereby providing high-quality, low-resistance transitions. Threading dislocations in the source/drain regions are relatively benign since these are less critical heavily doped regions, where the electrical impact of the dislocation is reduced by screen associate with the high concentration of carriers. This is true for both horizontal and vertical geometries.
  • Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements. Moreover, all ranges disclosed herein are to be understood to encompass any and all sub-ranges subsumed therein.
  • While the present teachings have been illustrated with respect to one or more implementations, alterations and/or modifications can be made to the illustrated examples without departing from the spirit and scope of the appended claims. In addition, while a particular feature of the present teachings may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular function. Furthermore, to the extent that the terms “including,” “includes,” “having,” “has,” “with,” or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term “comprising.” Further, in the discussion and claims herein, the term “about” indicates that the value listed may be somewhat altered, as long as the alteration does not result in nonconformance of the process or structure to the illustrated embodiment. Finally, “exemplary” indicates the description is used as an example, rather than implying that it is an ideal.
  • Other embodiments of the present teachings will be apparent to those skilled in the art from consideration of the specification and practice of the present teachings disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the present teachings being indicated by the following claims.

Claims (16)

1-30. (canceled)
31. A method for making a heteroepitaxial layer, the method comprising:
providing a silicon semiconductor substrate;
forming a nanostructured pedestal on the semiconductor substrate, the pedestal having a top surface and a side surface;
providing a selective growth mask layer on the top surface and side surface of the pedestal;
removing a portion of the selective growth mask layer to expose the top surface of the pedestal;
selectively etching-back the exposed top surface of the pedestal to form a seed area, the seed area having a first linear surface dimension that ranges from about 10 nm to about 50 nm; and
growing a silicon-germanium heteroepitaxial layer on the seed area without nucleating substantially any threading dislocations, at least a portion of the silicon-germanium heteroepitaxial layer extending above the selective growth mask layer and having a width dimension that is wider than a corresponding width dimension of the seed area,
wherein the portion of the silicon-germanium heteroepitaxial layer above the selective growth mask layer has a polygonal cross-sectional shape.
32. The method of claim 31, wherein the silicon-germanium heteroepitaxial layer is substantially defect-free.
33. The method of claim 31, wherein the silicon-germanium heteroepitaxial layer slopes outward proximate the seed area and slopes inward distal from the seed area.
34. The method of claim 31, wherein an entire silicon-germanium heteroepitaxial layer is grown above a top surface of the selective growth mask layer.
35. The method of claim 31, wherein the silicon semiconductor substrate comprises silicon having a [001] direction normal to the substrate surface.
36. The method of claim 31, wherein the nanostructured pedestal comprises a single crystal material chosen from silicon, III-V materials, sapphire and SiC.
37. The method of claim 31, wherein the nanostructured pedestal comprises a single crystal material chosen from GaAs, GaSb and GaN.
38. The method of claim 31, wherein the seed area comprises a (001) plane of silicon.
39. The method of claim 31, wherein the silicon-germanium heteroepitaxial layer comprises a semiconductor material other than III-V materials.
40. The method of claim 31, wherein the silicon-germanium heteroepitaxial layer comprises Ge0.23Si0.77.
41. The method of claim 31, further comprising forming a portion of a transistor from the silicon-germanium heteroepitaxial layer.
42. A method for making a heteroepitaxial layer, the method comprising:
providing a silicon semiconductor substrate;
forming a nanostructured pedestal on the semiconductor substrate, the pedestal having a top surface and a side surface;
providing a selective growth mask layer on the top surface and side surface of the pedestal;
removing a portion of the selective growth mask layer to expose the top surface of the pedestal;
selectively etching-back the exposed top surface of the pedestal to form a seed area, the seed area having a linear surface dimension that ranges from about 10 nm to about 50 nm and a second linear surface dimension that ranges from about 200 nm to about 5000 nm; and
growing a silicon-germanium heteroepitaxial layer on the seed area without nucleating substantially any threading dislocations, at least a portion of the silicon-germanium heteroepitaxial layer extending above the selective growth mask layer and having a width dimension that is wider than a corresponding width dimension of the seed area,
wherein the portion of the silicon-germanium heteroepitaxial layer above the selective growth mask layer has a polygonal cross-sectional shape.
43. The method of claim 42, wherein the silicon semiconductor substrate comprises silicon having a [001] direction normal to the substrate surface.
44. The method of claim 42, wherein the seed area comprises a (001) plane of silicon.
45. The method of claim 44, wherein the silicon-germanium heteroepitaxial layer comprises Ge0.23Si0.77.
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US16/162,787 US11342438B1 (en) 2012-07-17 2018-10-17 Device with heteroepitaxial structure made using a growth mask
US16/747,765 US11342441B2 (en) 2012-07-17 2020-01-21 Method of forming a seed area and growing a heteroepitaxial layer on the seed area
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9142400B1 (en) 2012-07-17 2015-09-22 Stc.Unm Method of making a heteroepitaxial layer on a seed area
WO2014209393A1 (en) * 2013-06-28 2014-12-31 Intel Corporation NANOSTRUCTURES AND NANOFEATURES WITH Si (111) PLANES ON Si (100) WAFERS FOR III-N EPITAXY
US10468406B2 (en) * 2014-10-08 2019-11-05 Northrop Grumman Systems Corporation Integrated enhancement mode and depletion mode device structure and method of making the same
US9691758B1 (en) * 2016-03-11 2017-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Fin-type resistor
US10936756B2 (en) 2017-01-20 2021-03-02 Northrop Grumman Systems Corporation Methodology for forming a resistive element in a superconducting structure
US11881520B2 (en) 2017-11-30 2024-01-23 Intel Corporation Fin patterning for advanced integrated circuit structure fabrication
US10665666B2 (en) * 2017-12-08 2020-05-26 International Business Machines Corporation Method of forming III-V on insulator structure on semiconductor substrate
KR20210026825A (en) * 2019-09-02 2021-03-10 삼성전자주식회사 Semiconductor devices including source/drain regions having antimony doped layer
US20220328688A1 (en) * 2021-04-08 2022-10-13 Nexgen Power Systems, Inc. Method and system for control of sidewall orientation in vertical gallium nitride field effect transistors

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080111163A1 (en) * 2006-11-14 2008-05-15 Infineon Technologies Ag Field effect transistor with a fin structure
US20090057846A1 (en) * 2007-08-30 2009-03-05 Doyle Brian S Method to fabricate adjacent silicon fins of differing heights
US20090170251A1 (en) * 2007-12-31 2009-07-02 Been-Yih Jin Fabrication of germanium nanowire transistors
US20110169101A1 (en) * 2008-09-16 2011-07-14 Gerben Doornbos Fin Field Effect Transistor (FINFET)
US20120217474A1 (en) * 2011-02-25 2012-08-30 Agency For Science, Technology And Research Photonic device and method of making the same
US20130026539A1 (en) * 2011-07-27 2013-01-31 Advanced Ion Beam Technology, Inc. Replacement source/drain finfet fabrication

Family Cites Families (291)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US688555A (en) 1901-07-19 1901-12-10 Ernest A Eastmann Buckle.
GB1437112A (en) 1973-09-07 1976-05-26 Mullard Ltd Semiconductor device manufacture
US4222792A (en) 1979-09-10 1980-09-16 International Business Machines Corporation Planar deep oxide isolation process utilizing resin glass and E-beam exposure
US4651179A (en) 1983-01-21 1987-03-17 Rca Corporation Low resistance gallium arsenide field effect transistor
US4571819A (en) 1984-11-01 1986-02-25 Ncr Corporation Method for forming trench isolation structures
US4551394A (en) 1984-11-26 1985-11-05 Honeywell Inc. Integrated three-dimensional localized epitaxial growth of Si with localized overgrowth of GaAs
US5236546A (en) 1987-01-26 1993-08-17 Canon Kabushiki Kaisha Process for producing crystal article
US5166767A (en) 1987-04-14 1992-11-24 National Semiconductor Corporation Sidewall contact bipolar transistor with controlled lateral spread of selectively grown epitaxial layer
US4876210A (en) 1987-04-30 1989-10-24 The University Of Delaware Solution growth of lattice mismatched and solubility mismatched heterostructures
GB2207281B (en) 1987-07-24 1992-02-05 Plessey Co Plc A method of providing refilled trenches
WO1989001235A1 (en) 1987-08-03 1989-02-09 Ford Microelectronics, Inc. High effective barrier height transistor and method of making same
US5098850A (en) 1989-06-16 1992-03-24 Canon Kabushiki Kaisha Process for producing substrate for selective crystal growth, selective crystal growth process and process for producing solar battery by use of them
US5403751A (en) 1990-11-29 1995-04-04 Canon Kabushiki Kaisha Process for producing a thin silicon solar cell
US5269852A (en) 1991-05-27 1993-12-14 Canon Kabushiki Kaisha Crystalline solar cell and method for producing the same
JPH05121317A (en) 1991-10-24 1993-05-18 Rohm Co Ltd Method for forming soi structure
US5208172A (en) 1992-03-02 1993-05-04 Motorola, Inc. Method for forming a raised vertical transistor
US5229316A (en) 1992-04-16 1993-07-20 Micron Technology, Inc. Semiconductor processing method for forming substrate isolation trenches
ATE169350T1 (en) 1992-12-04 1998-08-15 Siemens Ag METHOD FOR PRODUCING A LATERALLY DEFINED, SINGLE CRYSTALS AREA BY MEANS OF SELECTIVE EPITAXY AND ITS APPLICATION FOR PRODUCING A BIPOLAR TRANSISTOR AND A MOS TRANSISTOR
US5324683A (en) 1993-06-02 1994-06-28 Motorola, Inc. Method of forming a semiconductor structure having an air region
US5661313A (en) 1993-09-09 1997-08-26 The United States Of America As Represented By The Secretary Of The Navy Electroluminescent device in silicon on sapphire
US5453395A (en) 1994-03-21 1995-09-26 United Microelectronics Corp. Isolation technology using liquid phase deposition
US5702976A (en) 1995-10-24 1997-12-30 Micron Technology, Inc. Shallow trench isolation using low dielectric constant insulator
US6039803A (en) 1996-06-28 2000-03-21 Massachusetts Institute Of Technology Utilization of miscut substrates to improve relaxed graded silicon-germanium and germanium layers on silicon
US5702977A (en) 1997-03-03 1997-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. Shallow trench isolation method employing self-aligned and planarized trench fill dielectric layer
US6348096B1 (en) 1997-03-13 2002-02-19 Nec Corporation Method for manufacturing group III-V compound semiconductors
US5854126A (en) 1997-03-31 1998-12-29 Siemens Aktiengesellschaft Method for forming metallization in semiconductor devices with a self-planarizing material
JPH10340482A (en) 1997-06-09 1998-12-22 Hitachi Ltd Optical information recording medium
JPH113936A (en) 1997-06-13 1999-01-06 Nec Corp Manufacture of semiconductor device
KR100230431B1 (en) 1997-07-25 1999-11-15 윤종용 Method of forming trench isolation using two kinds of oxides films
KR20010024041A (en) 1997-09-16 2001-03-26 자르밀라 제트. 흐르벡 CO-PLANAR Si AND Ge COMPOSITE SUBSTRATE AND METHOD OF PRODUCING SAME
US5880007A (en) 1997-09-30 1999-03-09 Siemens Aktiengesellschaft Planarization of a non-conformal device layer in semiconductor fabrication
WO1999023693A1 (en) 1997-10-30 1999-05-14 Sumitomo Electric Industries, Ltd. GaN SINGLE CRYSTALLINE SUBSTRATE AND METHOD OF PRODUCING THE SAME
JP3085272B2 (en) 1997-12-19 2000-09-04 富士電機株式会社 Method for forming thermal oxide film on silicon carbide semiconductor device
US6057207A (en) 1998-03-25 2000-05-02 Taiwan Semiconductor Manufacturing Company Shallow trench isolation process using chemical-mechanical polish with self-aligned nitride mask on HDP-oxide
US6049650A (en) 1998-04-17 2000-04-11 Seagate Technology, Inc. Structure for micro-machine optical tooling and method for making and using
JP3702700B2 (en) 1999-03-31 2005-10-05 豊田合成株式会社 Group III nitride compound semiconductor device and method for manufacturing the same
EP1181718A4 (en) 1999-04-02 2005-03-30 Silicon Valley Group Thermal Improved trench isolation process to deposit a trench fill oxide prior to sidewall liner oxidation growth
TW461096B (en) 1999-05-13 2001-10-21 Hitachi Ltd Semiconductor memory
JP3555500B2 (en) 1999-05-21 2004-08-18 豊田合成株式会社 Group III nitride semiconductor and method of manufacturing the same
US6048775A (en) 1999-05-24 2000-04-11 Vanguard International Semiconductor Corporation Method to make shallow trench isolation structure by HDP-CVD and chemical mechanical polish processes
US6270353B1 (en) 1999-06-07 2001-08-07 International Business Machines Corporation Low cost shallow trench isolation using non-conformal dielectric material
WO2000077831A2 (en) 1999-06-11 2000-12-21 Quester Technology, Inc. Methods for regulating surface sensitivity of insulating films in semiconductor devices
US6228691B1 (en) 1999-06-30 2001-05-08 Intel Corp. Silicon-on-insulator devices and method for producing the same
KR20010009416A (en) 1999-07-09 2001-02-05 윤종용 Trench-type isolation method using a thin nitride film
US8994104B2 (en) 1999-09-28 2015-03-31 Intel Corporation Contact resistance reduction employing germanium overlayer pre-contact metalization
KR100345400B1 (en) 1999-10-08 2002-07-26 한국전자통신연구원 A trench formation method with tick edge oxide
US6291296B1 (en) 1999-10-12 2001-09-18 Advanced Micro Devices, Inc. Method for removing anti-reflective coating layer using plasma etch process before contact CMP
US6812053B1 (en) 1999-10-14 2004-11-02 Cree, Inc. Single step pendeo- and lateral epitaxial overgrowth of Group III-nitride epitaxial layers with Group III-nitride buffer layer and resulting structures
KR100338771B1 (en) 1999-11-12 2002-05-30 윤종용 Simplified trench isolation method comprising hydrogen annealing step
EP1102327B1 (en) 1999-11-15 2007-10-03 Matsushita Electric Industrial Co., Ltd. Field effect semiconductor device
US6261929B1 (en) 2000-02-24 2001-07-17 North Carolina State University Methods of forming a plurality of semiconductor layers using spaced trench arrays
US20050184302A1 (en) 2000-04-04 2005-08-25 Toshimasa Kobayashi Nitride semiconductor device and method of manufacturing the same
US6362071B1 (en) 2000-04-05 2002-03-26 Motorola, Inc. Method for forming a semiconductor device with an opening in a dielectric layer
KR20010112738A (en) 2000-06-12 2001-12-21 윤종용 Trench isolation method of semiconductor integrated circuit
US7301199B2 (en) 2000-08-22 2007-11-27 President And Fellows Of Harvard College Nanoscale wires and related devices
US6413802B1 (en) 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
KR100346845B1 (en) 2000-12-16 2002-08-03 삼성전자 주식회사 Method for forming shallow trench isolation in semiconductor device
US6541349B2 (en) 2001-01-18 2003-04-01 International Business Machines Corporation Shallow trench isolation using non-conformal dielectric and planarizatrion
JP3679720B2 (en) 2001-02-27 2005-08-03 三洋電機株式会社 Nitride semiconductor device and method for forming nitride semiconductor
JP2002270516A (en) 2001-03-07 2002-09-20 Nec Corp Growing method of iii group nitride semiconductor, film thereof and semiconductor element using the same
JP3705142B2 (en) 2001-03-27 2005-10-12 ソニー株式会社 Nitride semiconductor device and manufacturing method thereof
GB0111207D0 (en) 2001-05-08 2001-06-27 Btg Int Ltd A method to produce germanium layers
FR2826179A1 (en) 2001-06-14 2002-12-20 St Microelectronics Sa Deep insulating trench in a semiconductor substrate with side walls and base covered with an insulating material defining an empty cavity and forming a plug to seal this cavity
JP3875047B2 (en) 2001-06-22 2007-01-31 シャープ株式会社 Method for evaluating plane orientation dependence of semiconductor substrate and semiconductor device using the same
US20030015704A1 (en) 2001-07-23 2003-01-23 Motorola, Inc. Structure and process for fabricating semiconductor structures and devices utilizing the formation of a compliant substrate for materials used to form the same including intermediate surface cleaning
US20030054608A1 (en) 2001-09-17 2003-03-20 Vanguard International Semiconductor Corporation Method for forming shallow trench isolation in semiconductor device
FR2830984B1 (en) 2001-10-17 2005-02-25 St Microelectronics Sa INSULATION TRENCH AND METHOD OF MAKING SAME
JP2003142728A (en) 2001-11-02 2003-05-16 Sharp Corp Manufacturing method of semiconductor light emitting element
US6835246B2 (en) 2001-11-16 2004-12-28 Saleem H. Zaidi Nanostructures for hetero-expitaxial growth on silicon substrates
US7226504B2 (en) 2002-01-31 2007-06-05 Sharp Laboratories Of America, Inc. Method to form thick relaxed SiGe layer with trench structure
JP4092927B2 (en) 2002-02-28 2008-05-28 豊田合成株式会社 Group III nitride compound semiconductor, group III nitride compound semiconductor element, and method for manufacturing group III nitride compound semiconductor substrate
WO2004061969A1 (en) 2002-12-16 2004-07-22 The Regents Of The University Of California Growth of planar, non-polar a-plane gallium nitride by hydride vapor phase epitaxy
FR2840452B1 (en) 2002-05-28 2005-10-14 Lumilog PROCESS FOR THE EPITAXIC PRODUCTION OF A GALLIUM NITRIDE FILM SEPARATED FROM ITS SUBSTRATE
US6642090B1 (en) 2002-06-03 2003-11-04 International Business Machines Corporation Fin FET devices from bulk semiconductor and method for forming
US7358121B2 (en) 2002-08-23 2008-04-15 Intel Corporation Tri-gate devices and methods of fabrication
US6815241B2 (en) 2002-09-25 2004-11-09 Cao Group, Inc. GaN structures having low dislocation density and methods of manufacture
KR100481209B1 (en) 2002-10-01 2005-04-08 삼성전자주식회사 MOS Transistor having multiple channels and method of manufacturing the same
US6855990B2 (en) 2002-11-26 2005-02-15 Taiwan Semiconductor Manufacturing Co., Ltd Strained-channel multiple-gate transistor
US7012314B2 (en) 2002-12-18 2006-03-14 Agere Systems Inc. Semiconductor devices with reduced active region defects and unique contacting schemes
US6794718B2 (en) 2002-12-19 2004-09-21 International Business Machines Corporation High mobility crystalline planes in double-gate CMOS technology
KR20040055463A (en) 2002-12-21 2004-06-26 주식회사 하이닉스반도체 Method for forming isolation layer in semiconductor device
US6762483B1 (en) 2003-01-23 2004-07-13 Advanced Micro Devices, Inc. Narrow fin FinFET
US6885055B2 (en) 2003-02-04 2005-04-26 Lee Jong-Ho Double-gate FinFET device and fabricating method thereof
KR100471189B1 (en) 2003-02-19 2005-03-10 삼성전자주식회사 Field effect transistors having a vertical channel and methods of fabricating the same
US7176115B2 (en) 2003-03-20 2007-02-13 Matsushita Electric Industrial Co., Ltd. Method of manufacturing Group III nitride substrate and semiconductor device
CN1826694B (en) 2003-04-04 2012-04-25 库纳诺公司 Nanowhiskers with PN junctions and methods of fabricating thereof
US6838322B2 (en) 2003-05-01 2005-01-04 Freescale Semiconductor, Inc. Method for forming a double-gated semiconductor device
JP4105044B2 (en) 2003-06-13 2008-06-18 株式会社東芝 Field effect transistor
US7045401B2 (en) 2003-06-23 2006-05-16 Sharp Laboratories Of America, Inc. Strained silicon finFET device
US7514328B2 (en) 2003-06-26 2009-04-07 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween
KR100517559B1 (en) 2003-06-27 2005-09-28 삼성전자주식회사 Fin field effect transistor and method for forming of fin therein
KR100521382B1 (en) 2003-06-30 2005-10-12 삼성전자주식회사 Method for fabricating a finfet in a semiconductor device
US6812119B1 (en) 2003-07-08 2004-11-02 Advanced Micro Devices, Inc. Narrow fins by oxidation in double-gate finfet
KR100487567B1 (en) 2003-07-24 2005-05-03 삼성전자주식회사 Method for fabricating a finfet in a semiconductor device
US6835618B1 (en) 2003-08-05 2004-12-28 Advanced Micro Devices, Inc. Epitaxially grown fin for FinFET
US7196374B1 (en) 2003-09-03 2007-03-27 Advanced Micro Devices, Inc. Doped structure for FinFET devices
US6919258B2 (en) 2003-10-02 2005-07-19 Freescale Semiconductor, Inc. Semiconductor device incorporating a defect controlled strained channel structure and method of making the same
KR100578130B1 (en) 2003-10-14 2006-05-10 삼성전자주식회사 Multi silicon fins for finfet and method for fabricating the same
US6977194B2 (en) 2003-10-30 2005-12-20 International Business Machines Corporation Structure and method to improve channel mobility by gate electrode stress modification
KR100515061B1 (en) 2003-10-31 2005-09-14 삼성전자주식회사 Semiconductor devices having a fin field effect transistor and methods for forming the same
US7888201B2 (en) 2003-11-04 2011-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors
GB0326321D0 (en) 2003-11-12 2003-12-17 Univ Warwick Formation of lattice-tuning semiconductor substrates
US7247534B2 (en) 2003-11-19 2007-07-24 International Business Machines Corporation Silicon device on Si:C-OI and SGOI and method of manufacture
US7198995B2 (en) 2003-12-12 2007-04-03 International Business Machines Corporation Strained finFETs and method of manufacture
KR20060109956A (en) 2003-12-23 2006-10-23 코닌클리즈케 필립스 일렉트로닉스 엔.브이. Semiconductor device comprising a heterojunction
US7268058B2 (en) 2004-01-16 2007-09-11 Intel Corporation Tri-gate transistors and methods to fabricate same
EP1555688B1 (en) 2004-01-17 2009-11-11 Samsung Electronics Co., Ltd. Method of manufacturing a multi-sided-channel finfet transistor
US7385247B2 (en) 2004-01-17 2008-06-10 Samsung Electronics Co., Ltd. At least penta-sided-channel type of FinFET transistor
US7118987B2 (en) 2004-01-29 2006-10-10 Taiwan Semiconductor Manufacturing Co., Ltd. Method of achieving improved STI gap fill with reduced stress
US20050167655A1 (en) 2004-01-29 2005-08-04 International Business Machines Corporation Vertical nanotube semiconductor device structures and methods of forming the same
KR100526889B1 (en) 2004-02-10 2005-11-09 삼성전자주식회사 Fin field effect transistor structure
US7205210B2 (en) 2004-02-17 2007-04-17 Freescale Semiconductor, Inc. Semiconductor structure having strained semiconductor and method therefor
KR100532353B1 (en) 2004-03-11 2005-11-30 삼성전자주식회사 FinFET and Method of manufacturing the same
US7154118B2 (en) 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
KR100605104B1 (en) 2004-05-04 2006-07-26 삼성전자주식회사 Fin Field Effect Transistor Device And Method Of Fabricating The Same
US7205201B2 (en) 2004-08-09 2007-04-17 System General Corp. CMOS compatible process with different-voltage devices
US7271464B2 (en) 2004-08-24 2007-09-18 Micron Technology, Inc. Liner for shallow trench isolation
US7514739B2 (en) 2004-08-27 2009-04-07 Samsung Electronics Co., Ltd Nonvolatile semiconductor device and method of fabricating the same
KR100591770B1 (en) 2004-09-01 2006-06-26 삼성전자주식회사 Flash memory device using a semiconductor fin and method for fabricating the same
US8821635B2 (en) 2004-09-14 2014-09-02 Arizona Board Of Regents On Behalf Of Arizona State University Method for growing Si-Ge semiconductor materials and devices on substrates
US20060113603A1 (en) 2004-12-01 2006-06-01 Amberwave Systems Corporation Hybrid semiconductor-on-insulator structures and related methods
KR100672826B1 (en) 2004-12-03 2007-01-22 삼성전자주식회사 FinFET and Method of manufacturing the same
US7229901B2 (en) 2004-12-16 2007-06-12 Wisconsin Alumni Research Foundation Fabrication of strained heterojunction structures
KR100849177B1 (en) 2005-01-04 2008-07-30 삼성전자주식회사 Semiconductor integrated circuit devices employing a MOS transistor with facet channels and methods of fabricating the same
KR100614655B1 (en) 2005-01-13 2006-08-22 삼성전자주식회사 Method Of Forming Device Isolation Layer Of Semiconductor Device
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US20060207647A1 (en) * 2005-03-16 2006-09-21 General Electric Company High efficiency inorganic nanorod-enhanced photovoltaic devices
KR100688542B1 (en) 2005-03-28 2007-03-02 삼성전자주식회사 Vertical type nanotube semiconductor device and method of manufacturing the same
US20070267722A1 (en) 2006-05-17 2007-11-22 Amberwave Systems Corporation Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US8324660B2 (en) 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
EP1882268B1 (en) 2005-05-17 2016-12-14 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US9153645B2 (en) * 2005-05-17 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
EP1891679A1 (en) 2005-06-16 2008-02-27 QuNano AB Semiconductor nanowire transistor
US7807523B2 (en) 2005-07-01 2010-10-05 Synopsys, Inc. Sequential selective epitaxial growth
US7238586B2 (en) 2005-07-21 2007-07-03 United Microelectronics Corp. Seamless trench fill method utilizing sub-atmospheric pressure chemical vapor deposition technique
WO2007014294A2 (en) 2005-07-26 2007-02-01 Amberwave Systems Corporation Solutions integrated circuit integration of alternative active area materials
WO2007022359A2 (en) 2005-08-16 2007-02-22 The Regents Of The University Of California Vertical integrated silicon nanowire field effect transistors and methods of fabrication
US8120060B2 (en) 2005-11-01 2012-02-21 Massachusetts Institute Of Technology Monolithically integrated silicon and III-V electronics
US7309626B2 (en) 2005-11-15 2007-12-18 International Business Machines Corporation Quasi self-aligned source/drain FinFET process
US7525160B2 (en) 2005-12-27 2009-04-28 Intel Corporation Multigate device with recessed strain regions
US20070183185A1 (en) 2006-01-11 2007-08-09 The Regents Of The University Of California Finfet-based sram with feedback
WO2007086008A1 (en) 2006-01-25 2007-08-02 Nxp B.V. Tunneling transistor with barrier
ATE529894T1 (en) 2006-01-25 2011-11-15 Nxp Bv NANOWIRE TUNNEL TRANSISTOR
KR100790869B1 (en) 2006-02-16 2008-01-03 삼성전자주식회사 Single crystal substrate and fabrication method thereof
KR101019941B1 (en) 2006-03-10 2011-03-09 에스티씨. 유엔엠 Pulsed growth of gan nanowires and applications in group ? nitride semiconductor substrate materials and devices
JP2007250665A (en) 2006-03-14 2007-09-27 Toshiba Corp Semiconductor device and its manufacturing method
JP2007258485A (en) 2006-03-23 2007-10-04 Toshiba Corp Semiconductor device and its manufacturing method
US7901968B2 (en) 2006-03-23 2011-03-08 Asm America, Inc. Heteroepitaxial deposition over an oxidized surface
US7777250B2 (en) 2006-03-24 2010-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures and related methods for device fabrication
US7582516B2 (en) 2006-06-06 2009-09-01 International Business Machines Corporation CMOS devices with hybrid channel orientations, and methods for fabricating the same using faceted epitaxy
US7517764B2 (en) 2006-06-29 2009-04-14 International Business Machines Corporation Bulk FinFET device
US7745319B2 (en) 2006-08-22 2010-06-29 Micron Technology, Inc. System and method for fabricating a fin field effect transistor
KR100748261B1 (en) 2006-09-01 2007-08-09 경북대학교 산학협력단 Fin field effect transistor haiving low leakage current and method of manufacturing the finfet
US8173551B2 (en) 2006-09-07 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Defect reduction using aspect ratio trapping
EP1900681B1 (en) 2006-09-15 2017-03-15 Imec Tunnel Field-Effect Transistors based on silicon nanowires
WO2008036256A1 (en) 2006-09-18 2008-03-27 Amberwave Systems Corporation Aspect ratio trapping for mixed signal applications
EP2064744A2 (en) 2006-09-19 2009-06-03 QuNano AB Assembly of nanoscaled field effect transistors
WO2008039534A2 (en) 2006-09-27 2008-04-03 Amberwave Systems Corporation Quantum tunneling devices and circuits with lattice- mismatched semiconductor structures
WO2008039495A1 (en) 2006-09-27 2008-04-03 Amberwave Systems Corporation Tri-gate field-effect transistors formed by aspect ratio trapping
DE102006046377A1 (en) 2006-09-29 2008-04-03 Advanced Micro Devices, Inc., Sunnyvale Semiconductor device e.g. integrated circuit, has active semiconductor regions with peripheries formed by isolation trenches with dielectric filling materials, respectively, where filling materials are comprised of silicon nitride
WO2008051503A2 (en) 2006-10-19 2008-05-02 Amberwave Systems Corporation Light-emitter-based devices with lattice-mismatched semiconductor structures
KR100766232B1 (en) 2006-10-31 2007-10-10 주식회사 하이닉스반도체 Non-volatile memory device and manufacturing method of the same
KR100836761B1 (en) 2006-12-08 2008-06-10 삼성전자주식회사 Finfet and method of manufacturing the same
US8049203B2 (en) * 2006-12-22 2011-11-01 Qunano Ab Nanoelectronic structure and method of producing such
US8183587B2 (en) * 2006-12-22 2012-05-22 Qunano Ab LED with upstanding nanowire structure and method of producing such
EP1975988B1 (en) 2007-03-28 2015-02-25 Siltronic AG Multilayered semiconductor wafer and process for its production
JP4473889B2 (en) 2007-04-26 2010-06-02 株式会社東芝 Semiconductor device
US7732276B2 (en) 2007-04-26 2010-06-08 Spansion Llc Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications
US7667271B2 (en) 2007-04-27 2010-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field-effect transistors
US7888583B2 (en) * 2007-05-07 2011-02-15 Wisconsin Alumni Research Foundation Semiconductor nanowire thermoelectric materials and devices, and processes for producing same
US8450165B2 (en) 2007-05-14 2013-05-28 Intel Corporation Semiconductor device having tipless epitaxial source/drain regions
US7939862B2 (en) 2007-05-30 2011-05-10 Synopsys, Inc. Stress-enhanced performance of a FinFet using surface/channel orientations and strained capping layers
US7995892B2 (en) 2007-06-01 2011-08-09 Lawrence Livermore National Security, Llc Low loss, high and low index contrast waveguides in semiconductors
US20080315430A1 (en) 2007-06-22 2008-12-25 Qimonda Ag Nanowire vias
JP2009054886A (en) 2007-08-28 2009-03-12 Toshiba Corp Nonvolatile semiconductor memory
KR101093588B1 (en) 2007-09-07 2011-12-15 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Multi-junction solar cells
US8053810B2 (en) 2007-09-07 2011-11-08 International Business Machines Corporation Structures having lattice-mismatched single-crystalline semiconductor layers on the same lithographic level and methods of manufacturing the same
US7892956B2 (en) 2007-09-24 2011-02-22 International Business Machines Corporation Methods of manufacture of vertical nanowire FET devices
US8188513B2 (en) 2007-10-04 2012-05-29 Stc.Unm Nanowire and larger GaN based HEMTS
JP4966153B2 (en) 2007-10-05 2012-07-04 株式会社東芝 Field effect transistor and manufacturing method thereof
US7939889B2 (en) 2007-10-16 2011-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing resistance in source and drain regions of FinFETs
US8288756B2 (en) 2007-11-30 2012-10-16 Advanced Micro Devices, Inc. Hetero-structured, inverted-T field effect transistor
US8062951B2 (en) 2007-12-10 2011-11-22 International Business Machines Corporation Method to increase effective MOSFET width
US8129763B2 (en) 2008-02-07 2012-03-06 International Business Machines Corporation Metal-oxide-semiconductor device including a multiple-layer energy filter
CN101527327B (en) * 2008-03-07 2012-09-19 清华大学 Solar cell
KR20090097424A (en) 2008-03-11 2009-09-16 주식회사 하이닉스반도체 Method of forming the trench isolation layer for semiconductor device
US8133797B2 (en) 2008-05-16 2012-03-13 Novellus Systems, Inc. Protective layer to enable damage free gap fill
US8183667B2 (en) 2008-06-03 2012-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial growth of crystalline material
US8274097B2 (en) 2008-07-01 2012-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of edge effects from aspect ratio trapping
US8981427B2 (en) 2008-07-15 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Polishing of small composite semiconductor materials
US8604441B2 (en) 2008-07-24 2013-12-10 The Regents Of The University Of California Layered semiconductor neutron detectors
US20110168976A1 (en) * 2008-07-24 2011-07-14 The Regents Of The University Of California Micro- and nano-structured led and oled devices
US8241970B2 (en) 2008-08-25 2012-08-14 International Business Machines Corporation CMOS with channel P-FinFET and channel N-FinFET having different crystalline orientations and parallel fins
US8212336B2 (en) 2008-09-15 2012-07-03 Acorn Technologies, Inc. Field effect transistor source or drain with a multi-facet surface
CN102160145B (en) 2008-09-19 2013-08-21 台湾积体电路制造股份有限公司 Formation of devices by epitaxial layer overgrowth
US8367520B2 (en) 2008-09-22 2013-02-05 Soitec Methods and structures for altering strain in III-nitride materials
JP5679628B2 (en) 2008-12-16 2015-03-04 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． Semiconductor device and manufacturing method thereof
US7915642B2 (en) 2008-12-30 2011-03-29 Intel Corporation Apparatus and methods for forming a modulation doped non-planar transistor
US7851790B2 (en) 2008-12-30 2010-12-14 Intel Corporation Isolated Germanium nanowire on Silicon fin
US8263462B2 (en) 2008-12-31 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Dielectric punch-through stoppers for forming FinFETs having dual fin heights
US20110272763A1 (en) 2009-02-12 2011-11-10 Yuichiro Sasaki Semiconductor device and method for fabricating the same
US9768305B2 (en) 2009-05-29 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Gradient ternary or quaternary multiple-gate transistor
WO2010151604A2 (en) * 2009-06-26 2010-12-29 California Institute Of Technology Methods for fabricating passivated silicon nanowires and devices thus obtained
US8101473B2 (en) 2009-07-10 2012-01-24 Hewlett-Packard Development Company, L.P. Rounded three-dimensional germanium active channel for transistors and sensors
US8264021B2 (en) 2009-10-01 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Finfets and methods for forming the same
US8440517B2 (en) 2010-10-13 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET and method of fabricating the same
US8264032B2 (en) 2009-09-01 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Accumulation type FinFET, circuits and fabrication method thereof
US8383503B2 (en) 2009-08-05 2013-02-26 GlobalFoundries, Inc. Methods for forming semiconductor structures using selectively-formed sidewall spacers
US8169024B2 (en) * 2009-08-18 2012-05-01 International Business Machines Corporation Method of forming extremely thin semiconductor on insulator (ETSOI) device without ion implantation
US8362568B2 (en) 2009-08-28 2013-01-29 International Business Machines Corporation Recessed contact for multi-gate FET optimizing series resistance
US9245805B2 (en) 2009-09-24 2016-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Germanium FinFETs with metal gates and stressors
US8362575B2 (en) 2009-09-29 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Controlling the shape of source/drain regions in FinFETs
US8030144B2 (en) 2009-10-09 2011-10-04 Globalfoundries Inc. Semiconductor device with stressed fin sections, and related fabrication methods
EP2315239A1 (en) 2009-10-23 2011-04-27 Imec A method of forming monocrystalline germanium or silicon germanium
US9953885B2 (en) 2009-10-27 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. STI shape near fin bottom of Si fin in bulk FinFET
US8415718B2 (en) 2009-10-30 2013-04-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming epi film in substrate trench
DE102009046246B4 (en) * 2009-10-30 2012-04-12 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG Manufacturing method and semiconductor device with deformation technology in three-dimensional transistors based on globally deformed semiconductor base layers
WO2011063163A2 (en) * 2009-11-19 2011-05-26 California Institute Of Technology Methods for fabricating self-aligning arrangements on semiconductors
US8426923B2 (en) 2009-12-02 2013-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple-gate semiconductor device and method
US8313999B2 (en) 2009-12-23 2012-11-20 Intel Corporation Multi-gate semiconductor device with self-aligned epitaxial source and drain
US8169025B2 (en) 2010-01-19 2012-05-01 International Business Machines Corporation Strained CMOS device, circuit and method of fabrication
US8362572B2 (en) 2010-02-09 2013-01-29 Taiwan Semiconductor Manufacturing Co., Ltd. Lower parasitic capacitance FinFET
US8310013B2 (en) 2010-02-11 2012-11-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a FinFET device
US8609497B2 (en) 2010-02-12 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method of dual EPI process for semiconductor device
US8937353B2 (en) 2010-03-01 2015-01-20 Taiwan Semiconductor Manufacturing Co., Ltd. Dual epitaxial process for a finFET device
US8399931B2 (en) 2010-06-30 2013-03-19 Taiwan Semiconductor Manufacturing Company, Ltd. Layout for multiple-fin SRAM cell
EP2378557B1 (en) 2010-04-19 2015-12-23 Imec Method of manufacturing a vertical TFET
TWI562195B (en) * 2010-04-27 2016-12-11 Pilegrowth Tech S R L Dislocation and stress management by mask-less processes using substrate patterning and methods for device fabrication
EP2384816B1 (en) 2010-05-04 2018-04-04 IMEC vzw Method of manufacturing a nanochannel device
US8729627B2 (en) 2010-05-14 2014-05-20 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel integrated circuit devices
US8455929B2 (en) 2010-06-30 2013-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of III-V based devices on semiconductor substrates
US8062963B1 (en) 2010-10-08 2011-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a semiconductor device having an epitaxy region
US8729559B2 (en) * 2010-10-13 2014-05-20 Soraa, Inc. Method of making bulk InGaN substrates and devices thereon
US9166022B2 (en) 2010-10-18 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Fin-like field effect transistor (FinFET) device and method of manufacturing same
US8367498B2 (en) 2010-10-18 2013-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. Fin-like field effect transistor (FinFET) device and method of manufacturing same
US8753942B2 (en) 2010-12-01 2014-06-17 Intel Corporation Silicon and silicon germanium nanowire structures
US9385050B2 (en) 2011-01-06 2016-07-05 Globalfoundries Inc. Structure and method to fabricate resistor on finFET processes
US8236634B1 (en) 2011-03-17 2012-08-07 International Business Machines Corporation Integration of fin-based devices and ETSOI devices
US8435845B2 (en) 2011-04-06 2013-05-07 International Business Machines Corporation Junction field effect transistor with an epitaxially grown gate structure
US9761666B2 (en) 2011-06-16 2017-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel field effect transistor
US8618556B2 (en) 2011-06-30 2013-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET design and method of fabricating same
US8697522B2 (en) 2011-07-05 2014-04-15 International Business Machines Corporation Bulk finFET with uniform height and bottom isolation
US9716044B2 (en) 2011-08-18 2017-07-25 Taiwan Semiconductor Manufacturing Company, Ltd. Interlayer dielectric structure with high aspect ratio process (HARP)
US8841701B2 (en) 2011-08-30 2014-09-23 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device having a channel defined in a diamond-like shape semiconductor structure
US8728881B2 (en) 2011-08-31 2014-05-20 Institute of Microelectronics, Chinese Academy of Sciences Semiconductor device and method for manufacturing the same
US8890207B2 (en) 2011-09-06 2014-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET design controlling channel thickness
US8723272B2 (en) 2011-10-04 2014-05-13 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of manufacturing same
US8723236B2 (en) * 2011-10-13 2014-05-13 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of manufacturing same
US8722501B2 (en) 2011-10-18 2014-05-13 United Microelectronics Corp. Method for manufacturing multi-gate transistor device
US8624326B2 (en) 2011-10-20 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of manufacturing same
US9099388B2 (en) 2011-10-21 2015-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. III-V multi-channel FinFETs
US9105661B2 (en) 2011-11-03 2015-08-11 Taiwan Semconductor Manufacturing Company, Ltd. Fin field effect transistor gate oxide
KR101805634B1 (en) 2011-11-15 2017-12-08 삼성전자 주식회사 Semiconductor device comprising III-V group barrier and method of manufacturing the same
CN103137686B (en) 2011-11-24 2016-01-06 中芯国际集成电路制造(北京)有限公司 Semiconductor device and manufacture method thereof
KR101891458B1 (en) 2011-12-20 2018-08-24 인텔 코포레이션 Semiconductor device having iii-v semiconductor material layer
CN104011841B (en) 2011-12-21 2018-01-26 英特尔公司 For the method for the fin for forming metal oxide semiconductor device structure
US9012284B2 (en) * 2011-12-23 2015-04-21 Intel Corporation Nanowire transistor devices and forming techniques
US9087687B2 (en) 2011-12-23 2015-07-21 International Business Machines Corporation Thin heterostructure channel device
US8486770B1 (en) 2011-12-30 2013-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming CMOS FinFET device
WO2013101237A1 (en) 2011-12-31 2013-07-04 Intel Corporation Hard mask etch stop for tall fins
US8735993B2 (en) 2012-01-31 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET body contact and method of making same
US8659032B2 (en) * 2012-01-31 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET and method of fabricating the same
US20130200459A1 (en) 2012-02-02 2013-08-08 International Business Machines Corporation Strained channel for depleted channel semiconductor devices
US8664060B2 (en) 2012-02-07 2014-03-04 United Microelectronics Corp. Semiconductor structure and method of fabricating the same
JP6196987B2 (en) * 2012-02-14 2017-09-13 ヘキサジェム アーベー Electronics based on gallium nitride nanowires
EP2629320B1 (en) 2012-02-15 2018-10-17 IMEC vzw Mask structure and method for defect-free heteroepitaxial deposition
US8742509B2 (en) 2012-03-01 2014-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for FinFETs
US8836016B2 (en) 2012-03-08 2014-09-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures and methods with high mobility and high energy bandgap materials
US9105654B2 (en) 2012-03-21 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain profile for FinFET
US8987835B2 (en) 2012-03-27 2015-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with a buried semiconductor material between two fins
US8652932B2 (en) 2012-04-17 2014-02-18 International Business Machines Corporation Semiconductor devices having fin structures, and methods of forming semiconductor devices having fin structures
US9041115B2 (en) 2012-05-03 2015-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Structure for FinFETs
US20130302954A1 (en) 2012-05-10 2013-11-14 Globalfoundries Inc. Methods of forming fins for a finfet device without performing a cmp process
US8680576B2 (en) 2012-05-16 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS device and method of forming the same
US8603893B1 (en) 2012-05-17 2013-12-10 GlobalFoundries, Inc. Methods for fabricating FinFET integrated circuits on bulk semiconductor substrates
US8580642B1 (en) 2012-05-21 2013-11-12 Globalfoundries Inc. Methods of forming FinFET devices with alternative channel materials
US8669147B2 (en) 2012-06-11 2014-03-11 Globalfoundries Inc. Methods of forming high mobility fin channels on three dimensional semiconductor devices
US10535735B2 (en) 2012-06-29 2020-01-14 Intel Corporation Contact resistance reduced P-MOS transistors employing Ge-rich contact layer
US9142400B1 (en) 2012-07-17 2015-09-22 Stc.Unm Method of making a heteroepitaxial layer on a seed area
US8809131B2 (en) 2012-07-17 2014-08-19 International Business Machines Corporation Replacement gate fin first wire last gate all around devices
US8652891B1 (en) 2012-07-25 2014-02-18 The Institute of Microelectronics Chinese Academy of Science Semiconductor device and method of manufacturing the same
US9728464B2 (en) 2012-07-27 2017-08-08 Intel Corporation Self-aligned 3-D epitaxial structures for MOS device fabrication
US8946033B2 (en) 2012-07-30 2015-02-03 International Business Machines Corporation Merged fin finFET with (100) sidewall surfaces and method of making same
US9059292B2 (en) 2012-08-02 2015-06-16 International Business Machines Corporation Source and drain doping profile control employing carbon-doped semiconductor material
US8993402B2 (en) 2012-08-16 2015-03-31 International Business Machines Corporation Method of manufacturing a body-contacted SOI FINFET
US8963206B2 (en) 2012-08-27 2015-02-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method for increasing fin density
US8669167B1 (en) 2012-08-28 2014-03-11 International Business Machines Corporation Techniques for metal gate workfunction engineering to enable multiple threshold voltage FINFET devices
US9082873B2 (en) 2012-09-20 2015-07-14 International Business Machines Corporation Method and structure for finFET with finely controlled device width
US20140264488A1 (en) * 2013-03-15 2014-09-18 Globalfoundries Inc. Methods of forming low defect replacement fins for a finfet semiconductor device and the resulting devices
JP6235267B2 (en) 2013-07-31 2017-11-22 セコム株式会社 Patrol work support system, patrol work support method, and patrol work support system program
US9786782B2 (en) 2015-10-23 2017-10-10 International Business Machines Corporation Source/drain FinFET channel stressor structure

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080111163A1 (en) * 2006-11-14 2008-05-15 Infineon Technologies Ag Field effect transistor with a fin structure
US20090057846A1 (en) * 2007-08-30 2009-03-05 Doyle Brian S Method to fabricate adjacent silicon fins of differing heights
US20090170251A1 (en) * 2007-12-31 2009-07-02 Been-Yih Jin Fabrication of germanium nanowire transistors
US20110169101A1 (en) * 2008-09-16 2011-07-14 Gerben Doornbos Fin Field Effect Transistor (FINFET)
US20120217474A1 (en) * 2011-02-25 2012-08-30 Agency For Science, Technology And Research Photonic device and method of making the same
US20130026539A1 (en) * 2011-07-27 2013-01-31 Advanced Ion Beam Technology, Inc. Replacement source/drain finfet fabrication

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