US20170301632A1 - Package and method of manufacturing the same - Google Patents

Package and method of manufacturing the same Download PDF

Info

Publication number
US20170301632A1
US20170301632A1 US15/637,220 US201715637220A US2017301632A1 US 20170301632 A1 US20170301632 A1 US 20170301632A1 US 201715637220 A US201715637220 A US 201715637220A US 2017301632 A1 US2017301632 A1 US 2017301632A1
Authority
US
United States
Prior art keywords
substrate
package
dicing
plated
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US15/637,220
Inventor
Do Jae Yoo
Kyu Hwan Oh
Jong In Ryu
Jae Hyun Lim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electro Mechanics Co Ltd
Original Assignee
Samsung Electro Mechanics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electro Mechanics Co Ltd filed Critical Samsung Electro Mechanics Co Ltd
Priority to US15/637,220 priority Critical patent/US20170301632A1/en
Publication of US20170301632A1 publication Critical patent/US20170301632A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Definitions

  • the molded parts 130 may be formed on both surfaces of the substrate 100 so as to surround the electronic components 120 in order to safely protect the electronic components 120 , wires, connection parts, and the like from external impact.
  • connection pattern 102 is formed on one side surface of the lower surface of the substrate 100 is shown in the drawings by way of example, but the present disclosure is not limited thereto.
  • the connection pattern 102 may be formed at various positions and in various shapes depending on a position of the plated tail 101 connected to the connection pattern 102 .
  • the plated tail 101 and the connection pattern 102 may be formed on the upper surface of the substrate or an intermediate circuit layer of the substrate.
  • the lower package 500 is not particularly limited and is a typical package on which components are mounted.
  • the package may have a typical package on package (POP) structure in which the lower package 500 is connected to an upper package through external connection terminals, for example, the solder bumps 140 .
  • POP package on package

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The method of manufacturing a package comprising: preparing a strip substrate having a plurality of separate package regions which are partitioned by a dicing region and via pads which are connected to one ends of plated tails which are divided to be disconnected in the dicing region; mounting at least one electronic component on at least one surface of each package region of the substrate; forming a connection pattern having conductivity in disconnected portions of the plated tails to form electrical connections therebetween; forming a molded part on the surface of the substrate to enclose the electronic component; forming at least one via penetrating through the molded part by applying current through the plated tails; and dicing the substrate in the dicing region to divide the substrate into separate packages, each having the connection pattern exposed to the exterior of the substrate.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application is a divisional of application Ser. No. 14/810,947 filed on Jul. 28, 2015, which claims the benefit of priority of Korean Patent Application No. 10-2014-0097069 filed on Jul. 30, 2014, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.
    • BACKGROUND
  • The present disclosure relates to a package and a method of manufacturing the same.
  • Recent electronic devices have been required to have a package thickness of 1.15 mmT or less, based on a double-sided substrate, and a subminiature size according to reductions in the thicknesses of mobile phones. Accordingly, the mounting density of modules has increased.
    • SUMMARY
  • An aspect of the present disclosure provides a package having a plating mold via interconnect ion structure in which electrodes may be formed, and a method of manufacturing the same.
  • An aspect of the present disclosure also provides a package having a significantly reduced influence of a plated tail, and a method of manufacturing the same.
  • An aspect of the present disclosure also provides a package capable of excellently implementing electromagnetic wave interference and electromagnetic wave susceptibility characteristics after performing a dicing process for dividing the substrate into separate packages, and a method of manufacturing the same.
  • According to an aspect of the present disclosure may include: vias formed in molded parts surrounding electronic components so as to be electrically connected to circuit layers of a substrate; and a connection pattern connected to one end of a plated tail connected to the circuit layer connected to the via so as to be exposed to the exterior of the substrate.
    • BRIEF DESCRIPTION OF DRAWINGS
  • The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
  • FIG. 1 is a cross-sectional view illustrating a package according to an exemplary embodiment in the present disclosure;
  • FIG. 2 is a cross-sectional view illustrating a package according to another exemplary embodiment in the present disclosure; and
  • FIGS. 3 through 9 are process cross-sectional views illustrating a method of manufacturing a package according to an exemplary embodiment in the present disclosure in a process sequence.
    •  DETAILED DESCRIPTION
  • Exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.
  • The disclosure may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
  • In the drawings, the shapes and dimensions of elements may be exaggerated for clarity, and the same reference numerals will be used throughout to designate the same or like elements.
  • A term “package” used in the present disclosure is a concept including wireless communications such as Wi-Fi, and an electronic element module, and is not limited to a bare package.
  • Package
  • FIG. 1 is a cross-sectional view illustrating a package according to an embodiment in the present disclosure.
  • Referring to FIG. 1, a package 1000 may include a substrate 100 having a plurality of circuit layers, one or more electronic components 120 mounted on both surfaces of the substrate 100, molded parts 130 formed on both surfaces of the substrate 100 so as to surround the electronic components 120, vias 113 formed in the molded parts 130 so as to be electrically connected to the circuit layers of the substrate 100, and a connection pattern 102 connected to one end of a plated tail 101 connected to the circuit layer connected to the via 113 and exposed to the exterior of the substrate 100.
  • The substrate 100 is a circuit substrate having one or more circuit layers formed on an insulating layer, and as the substrate 100, various kinds of substrates such as a substrate, a printed circuit board, and a metal substrate which are well known in the art may be used.
  • As an example of the insulating layer, a resin insulating layer may be used in a case of the printed circuit board or a ceramic insulating layer may be used in a case of the substrate, for example. As materials of the resin insulating layer, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, a resin having a reinforcement material such as a glass fiber or an inorganic filler impregnated in the thermosetting resin and the thermoplastic resin, for example, prepreg may be used. In addition, a photo-curable resin, and the like, may be used. However, the materials of the resin insulating layer are not particularly limited thereto.
  • As a material of the circuit layer, any material may be used without being limited as long as it is used as a conductive metal for a circuit in a circuit substrate field, and copper is typically used in the printed circuit board.
  • As the circuit layers, mounting electrodes for mounting the electronic component 120, or circuit patterns that electrically connect the mounting electrodes to each other may be formed. In addition, vias for an electrical connection may be formed between the respective layers of the substrate 100.
  • According to the present exemplary embodiment, as the circuit layers, via pads 111 may be formed on a lower surface of the substrate 100 and ground electrodes 112, a part of conductive pattern, may be formed on an upper surface of the substrate 100. The via pads 111 and the ground electrodes 112 will be described below together with a related configuration.
  • The electronic components 120 may be mounted on both surfaces of the substrate 100 by a typical wire bonding or flip-chip bonding. Further, the electronic components 120 may be embedded in the substrate 100.
  • The electronic components 120 may include various electronic elements such as passive elements and active elements, and any electronic elements may be all used as the electronic components 120 as long as they may be mounted on the substrate 100 or be embedded in the substrate 100.
  • The molded parts 130 may be formed on both surfaces of the substrate 100 so as to surround the electronic components 120 in order to safely protect the electronic components 120, wires, connection parts, and the like from external impact.
  • The molded parts 130 may be made of, for example, an insulating material including a resin material such as an epoxy molded compound (EMC) or a silicon based epoxy, or the like, but is not particularly limited thereto.
  • The vias 113 that penetrate through the molded parts 130 may be formed in the molded parts 130 so as to be in surface-contact with the via pads 111 of the substrate 100 and be electrically connected to the via pads 111. The via 113 may have an external connection terminal for a connection with an external component or a package formed on a lower end thereof, for example, a solder bump 140.
  • Here, the plated tail 101 formed to be coplanar with the via pad 111 may be connected to the via pad 111. The connection pattern 102 may be connected to one end of the plated tail 101 and be exposed to the exterior of the substrate 100. That is, a side surface of the connection pattern 102 may be formed on to be substantially coplanar with a side surface of the substrate 100, so as to be exposed to the side surface of the substrate 100.
  • The case in which the connection pattern 102 is formed on one side surface of the lower surface of the substrate 100 is shown in the drawings by way of example, but the present disclosure is not limited thereto. For example, the connection pattern 102 may be formed at various positions and in various shapes depending on a position of the plated tail 101 connected to the connection pattern 102. For example, the plated tail 101 and the connection pattern 102 may be formed on the upper surface of the substrate or an intermediate circuit layer of the substrate.
  • If necessary, the connection pattern 102 may or may not have conductivity.
  • Since the connection pattern 102 demonstrates conductivity at the time of plating the via 113 in a process of manufacturing the package, the connection pattern 102 may be connected to the plated tail 101 and may be electro-plated by a current applied through the plated tail 101 connected thereto. On the contrary, the connection pattern 102 may lose conductivity in a final product by a separate nonconductor treatment after forming the via 113 by the plating process, during a dicing process for dividing the substrate into separate packages, or after the dicing process.
  • However, the present inventive concept is not limited thereto. If necessary, the connection pattern 102 may be formed to retain conductivity in the finished product by omitting the nonconductor treatment. Alternatively, portions of the connection pattern 102 may retain conductivity, but the other portions thereof may lose conductivity. In this case, the portions of the connection pattern 102 having conductivity may be used for circuit wiring together with the plated tail 101.
  • For example, in a case in which the connection pattern 102 illustrated in FIG. 1 retains conductivity, the connection pattern 102 may be electrically connected to the shielding part 150. Therefore, the connection pattern 102 and the plated tail 101 connected thereto may serve as ground electrodes, and the via 113 and the solder bump 140 electrically connected to the plated tail may serve as a ground via and a ground terminal, respectively. In this case, the ground electrodes 112 may be omitted.
  • The connection pattern 102 may have conductivity at the time of plating of the via 113, for example, using a method of transforming the connection pattern 102 into an insulator by using thermal oxidation characteristics of a connection material having conductivity, transforming the connection pattern 102 into the insulator by using oxidation characteristics by laser irradiation, using characteristics in which the connection material having conductivity is transformed into the insulator by a mechanical process, or using magnetic characteristics of the connection material having conductivity, or transforming the connection pattern 102 into the insulator by using an alignment of a metal core of the connection material having conductivity, and may be then transformed into an insulator that does not have conductivity. The method of transforming the connection material having conductivity into the insulator is not limited thereto, and any method may be used as long as it is known in the art.
  • For example, the connection pattern 102 may be formed of a conductive resin such as a Cu epoxy paste, and the surface thereof may lose conductivity by oxidizing a conductive material such as Cu.
  • Therefore, the electrodes may be stably formed by a mold via connection structure formed by the electroplating process. Further, since the connection pattern having conductivity which is connected to the plated tail is transformed into the nonconductor that does not have conductivity by the dicing process for dividing the substrate into the separate packages or by the subsequent separate nonconductor treatment, an influence of the plated tail left within the package may be significantly reduced.
  • The circuit layer of the substrate 100 may further include a ground electrode 112 formed to be exposed to the exterior of the substrate 100.
  • The ground electrode 112 may be formed as a metal wiring pattern on the upper surface of the substrate 100. The ground electrode 112 may be formed to be long along the side surface of the substrate 100 on the upper surface of the substrate 100 which is formed in a quadrangular shape. The ground electrode 112 may be formed along at least one side surface of four side surfaces of the substrate 100. A side surface of the ground electrode 112 may be formed to be coplanar with the side surface of the substrate 100, so as to be exposed to the side surface of the substrate 100.
  • In FIG. 1, the case in which the ground electrode 112 is formed along the side surface of the substrate 100 on the upper surface of the substrate 100 is described by way of example, but the present disclosure is not limited thereto. For example, the ground electrode 112 may be formed on the lower surface of the substrate 100 or an intermediate circuit layer of the substrate 100. In addition, when the ground electrode 112 needs to be electrically connected to a terminal of the electronic component 120, the ground electrode 112 is formed so that a portion thereof is protruded to a lower portion of the electronic component 120, whereby the protruded portion may be electrically connected to the terminal of the electronic component 120.
  • Further, a shielding part 150 may be formed on outer surfaces of the molded part 130 and the substrate 100 so as to cover an upper surface and side surfaces of the package 1000.
  • The shielding part 150 may be electrically connected to the exposed portion of the ground electrode 112.
  • The shielding part 150 may accommodate the electronic component 120 and may be formed on the outer surface of the molded part 130, so as to shield an unnecessary electromagnetic wave introduced from the outside of the substrate 100. In addition, the shielding part 15 may prevent an electromagnetic wave generated by the electronic component 120 from being radiated to the outside. The shielding part 150 may be formed so as to be closely adhered to the molded part and cover the outer surface of the molded part 130.
  • The shielding part 150 needs to be necessarily grounded in order to shield the electromagnetic wave. To this end, the package 1000 may be configured so that the shielding part 150 is electrically connected to the ground electrode 112. More particularly, the shielding part 150 may be electrically connected to the ground electrode 112 exposed to the exterior of the substrate 100.
  • The shielding part 150 may be formed of various materials having conductivity and may be formed in a metal case shape, but is not limited thereto. That is, the shielding part 150 may be completed by being formed of a resin material containing conductive powders or directly forming a metal thin film. In the case of forming the metal thin film, various technologies such as a sputtering method, a vapor deposition method, an electroplating method, an electroless plating method, and the like, may be used.
  • In addition, the shielding part 150 may be a metal thin film formed by a spray coating method. The spray coating method has advantages in which it may form a uniform application layer and has low investment costs in equipments as compared to other processes. In addition, the shielding part 150 may be a metal thin film formed by a screen printing method.
  • The package 1000 having the configuration as described above may protect the electronic component 120 mounted on the substrate 100 by the molded parts 130 from external force and further improve an effect of shielding the electromagnetic wave by the shielding part 150 formed on the outer surface of the molded part 130.
  • In addition, by using the ground electrode 112 formed on the upper surface of the substrate 100 in order to ground the shielding part 150 for shielding the electromagnetic wave, the shielding part 150 may be easily grounded.
  • Meanwhile, in the package 1000 according to an exemplary embodiment in the present disclosure, after a plurality of packages are simultaneously formed on the substrate having a strip shape, the plurality of packages may be formed in separate packages by a dicing process. A detailed description thereof will be provided in a description of a method of manufacturing a package to be described below.
  • The package 1000 may also be mounted on a main board of a mobile phone.
  • FIG. 2 is a cross-sectional view illustrating a package according to another exemplary embodiment in the present disclosure. Hereinafter, a description of overlapped configurations will be omitted.
  • Referring to FIG. 2, a package 2000 may include a substrate 100 having a plurality of circuit layers, one or more electronic components 120 mounted on both surfaces of the substrate 100, molded parts 130 formed on both surfaces of the substrate 100 so as to surround the electronic components 120, vias 113 formed in the molded parts 130 so as to be electrically connected to the circuit layers of the substrate 100, a connection pattern 102 connected to one end of a plated tail 101 connected to the circuit layer connected to the via 113 and exposed to the exterior of the substrate 100, solder bumps 140 formed in the vias 113, and a lower package 500 connected to the solder bumps 140 so as to be mounted thereon.
  • The lower package 500 is not particularly limited and is a typical package on which components are mounted. The package may have a typical package on package (POP) structure in which the lower package 500 is connected to an upper package through external connection terminals, for example, the solder bumps 140.
  • The package 2000 may also be mounted on a main board of a mobile phone.
  • Method of Manufacturing Package
  • FIGS. 3 through 9 are process cross-sectional views illustrating a method of manufacturing a package according to an exemplary embodiment in the present disclosure in a process sequence.
  • First, referring to FIG. 3, a strip substrate 1000 a having a plurality of separate package regions A which are partitioned by a dicing region B and having via pads 111 connected to one end of plated tails 101 which are separated so as to be disconnected at the dicing region B may be prepared.
  • The strip substrate 1000 a is to simultaneously manufacture a plurality of separate packages and has a plurality of separate package regions A partitioned thereon, and the packages may be manufactured for each of the plurality of separate package regions A.
  • The substrate 1000 a may be a multilayer circuit substrate having a plurality of circuit layers, wherein each circuit layer may include circuit patterns that electrically connect mounting electrodes to each other, external connection terminals, the mounting electrodes, vias, and the like.
  • According to the present exemplary embodiment, the substrate 1000 a may have the via pads 111 formed thereon. The via pad 111 may be connected to one end of the plated tail 101. The plated tail 101 may have disconnected portions C which are separated so as to be disconnected in the dicing region B. The plated tail 101 may be formed to be coplanar with the via pad 111.
  • Meanwhile, the substrate 1000 a may have at least one circuit pattern extended from the separate package region A to the dicing region B. According to the present exemplary embodiment, the circuit patterns extended to the dicing region B may be ground electrodes 112.
  • When the strip substrate 1000 a is diced for each of the separate package regions A, the ground electrodes 112 may be formed along side surfaces of the diced separate substrates.
  • Selectively, when the strip substrate 1000 a is diced for each of the separate package regions A, the ground electrodes 112 may be formed along an overall edge of the diced separate substrates.
  • Since the via pads 111 and the ground electrodes 112 as described above may be formed by the same method as a method of forming a general circuit pattern, a detailed description thereof will be omitted.
  • Next, referring to FIG. 4, at least one electronic component 120 is mounted on both surfaces of each of the separate package regions A and connection patterns 102 a having conductivity are formed on the disconnected portions C of the plated tail 101, thereby electrically connecting the separated plated tails 101.
  • The same kind of electronic component 120 and the same number of electronic components 120 may be disposed and mounted on each of the separate package regions A.
  • In the present operation, since the connection pattern 102 a has conductivity, a current may be applied through the plated tails 101 which are connected to each other in a plating operation to be described below.
  • The connection pattern 102 a having conductivity may be formed to be coplanar with the via pad 111.
  • Next, referring to FIG. 5, the molded parts 130 may be formed on both surfaces of the substrate so as to surround the electronic components 120.
  • The molded parts 130 may be formed by injecting, for example, an insulating material including a resin material such as an epoxy molded compound (EMC) or a silicon based epoxy, or the like, into the substrate, but is not particularly limited thereto.
  • Next, referring to FIG. 6, the current may be applied through the plated tail 101 connected by the connection pattern 102 a having conductivity, thereby forming the vias 113 penetrating through the molded part 130 on the via pads 111. The vias 113 may be extended from the via pads 111 to a lower surface of the molded part 130. As result, since a lower surface thereof is formed to be substantially coplanar with the lower surface of the molded part 130, the vias 113 may be exposed to the lower surface of the molded part 130.
  • Specifically, via holes penetrating through the molded part 130 so as to expose the via pads 111 are first formed and the current is then applied through the plated tail 101 connected to the via pads 111, such that the vias 113 may be formed by filling the via holes with an electroplating layer.
  • In this case, the solder bumps 140 as the external connection terminals may be selectively formed on the exposed portions of the vias 113.
  • However, the present disclosure is not limited thereto, but the solder bumps 140 may also be mounted on each of the separate packages after the dicing process in which the substrate is diced into the separate packages, if necessary.
  • Next, referring to FIG. 7, the substrate may be divided into the separate packages having the connection pattern 102 exposed externally by dicing the substrate in the dicing region B.
  • The dicing process of the substrate in the dicing region B may be performed by a router, a blade, laser, or a combination thereof.
  • Here, the connection pattern 102 a having conductivity may be transformed into a nonconductor that does not have conductivity by heat, laser, or the like generated in the dicing process of the substrate in the dicing region B, and consequently, may become a connection pattern 102 that does not have conductivity.
  • As described above, since the connection pattern demonstrates conductivity at the time of plating the via 113, the connection pattern may be connected to the plated tail 101 and the electroplating process may be performed by the current applied through the plated tail 101 connected to the connection pattern. On the contrary, after the vias 113 are formed by the plating process, the connection pattern having conductivity may lose conductivity by the dicing process for dividing the substrate into the separate packages.
  • Selectively, a nonconductor treatment is separately performed for the exposed portions of the connection pattern having conductivity after the dicing process, such that the connection pattern may also lose conductivity in the finished product.
  • In addition, the connection pattern having conductivity may lose conductivity by heat, laser, or the like generated in the dicing process and a separate nonconductor treatment may also be additionally performed for the exposed portions of the connection pattern at the same time, if necessary.
  • The connection pattern may have conductivity at the time of plating of the via 113, for example, using a method of transforming the connection pattern into an insulator by using thermal oxidation characteristics of a connection material having conductivity, transforming the connection pattern into the insulator by using oxidation characteristics by laser irradiation, using characteristics in which the connection material having conductivity is transformed into the insulator by a mechanical process, or using magnetic characteristics of the connection material having conductivity, or transforming the connection pattern into the insulator by using an alignment of a metal core of the connection material having conductivity, and may be then transformed into an insulator that does not have conductivity. The method of transforming the connection material having conductivity into the insulator is not limited thereto, and any method may be used as long as it is known in the art.
  • Therefore, the electrodes may be stably formed by the mold via connection structure formed by the electroplating process. Further, since the connection pattern having conductivity which is connected to the plated tail is transformed into the nonconductor that does not have conductivity by the dicing process for dividing the substrate into the separate packages and/or by the subsequent separate nonconductor treatment, an influence of the plated tail left within the package may be significantly reduced.
  • Meanwhile, the ground electrode 112 may also be diced by the dicing process to be exposed to the exterior of the separate package.
  • Next, referring to FIG. 8, the shielding part 150 may be formed so as to cover at least portion of outer surfaces of the separate packages which are diced and divided as described above. Here, the shielding part 150 may be electrically connected to the exposed portion of the ground electrode 112.
  • In order to implement an electromagnetic wave shield and ground preventing power of an electromagnetic wave from being transitioned into an inner portion/outer portion of the package, the shielding part 150 may be configured by forming a thin and uniform coating film made of a material of shielding the electromagnetic wave on outer walls of the molded parts 130.
  • The shielding part 150 may be formed by a typical plating method, an ion plating method, a spray coating method, a vacuum deposition method, or the like, but is not particularly limited thereto.
  • Examples of a conductive filler contained in the shielding part 150 may include a metallic based material (e.g., Ag, Cu, Ni), a metallic complex material, a carbon based material, a conductive polymer based material, or the like.
  • By forming the shielding part 150 as described above, noise due to radio wave inter-disturbance between transmitting and receiving apparatuses may be shielded, an efficiency deterioration and life reduction of internal components may be prevented, and harm against a body due to the electromagnetic wave which is self generated may be prevented.
  • Next, referring to FIG. 9, the lower package 500 may be mounted on the solder bumps 140.
  • The lower package 500 is not particularly limited and is a typical package on which components are mounted. The package may have a typical package on package (POP) structure in which the lower package 500 is connected to an upper package through external connection terminals, for example, the solder bumps 140.
  • However, since the process of forming the package in the POP structure including the lower package 500 is a process which is additionally performed, if necessary, it may be omitted.
  • Therefore, the package in which the shielding part shown in FIG. 8 is formed may be directly mounted on the main board of the mobile phone, or the package of the POP structure including the lower package may also be mounted on the main board, if necessary.
  • While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present invention as defined by the appended claims.

Claims (11)

What is claimed is:
1. A method of manufacturing a package, the method comprising:
preparing a strip substrate having a plurality of separate package regions which are partitioned by a dicing region and via pads which are connected to one ends of plated tails which are divided to be disconnected in the dicing region;
mounting at least one electronic component on at least one surface of each package region of the substrate;
forming a connection pattern having conductivity in disconnected portions of the plated tails to form electrical connections therebetween;
forming a molded part on the surface of the substrate to enclose the electronic component;
forming at least one via penetrating through the molded part by applying current through the plated tails; and
dicing the substrate in the dicing region to divide the substrate into separate packages, each having the connection pattern exposed to the exterior of the substrate.
2. The method of claim 1, wherein the forming of the via includes:
forming a via hole penetrating through the molded part to expose the via pad; and
forming the via by applying the current through the plated tail connected to the via pad to allow the via hole to be filled with an electroplating layer.
3. The method of claim 1, wherein the connection pattern having conductivity becomes nonconductive by the dicing of the substrate in the dicing region.
4. The method of claim 1, wherein the dicing of the substrate in the dicing region is performed using a router, a blade, a laser, or combinations thereof.
5. The method of claim 1, further comprising removing conductivity from the exposed portion of the connection pattern after the dividing of the substrate into the separate packages.
6. The method of claim 1, wherein the connection pattern is formed to be co-planar with the via pad.
7. The method of claim 1, wherein the substrate has at least one circuit pattern extended from the separate package region to the dicing region; and
the circuit pattern is exposed to the exterior of the separate package by the dicing of the substrate in the dicing region.
8. The method of claim 7, wherein the circuit pattern is a ground electrode.
9. The method of claim 8, wherein the ground electrode is formed to be elongated on an edge of the separate package region.
10. The method of claim 7, further comprising forming a shielding part to cover at least a portion of the separate package after the dividing of the substrate into the separate packages,
wherein the shielding part is electrically connected to the exposed portion of the circuit pattern.
11. A method of manufacturing a package, the method comprising:
preparing a strip substrate having a plurality of separate package regions which are partitioned by a dicing region and one or more circuit layers which are connected to one ends of plated tails which are divided to be disconnected in the dicing region;
mounting at least one electronic component on at least one surface of each package region of the substrate;
forming a connection pattern having conductivity in disconnected portions of the plated tails to form electrical connections therebetween;
forming a molded part on the surface of the substrate to enclose the electronic component;
forming at least one via penetrating through the molded part by applying current to the circuit layer connected to one ends of the plated tails through the plated tails;
dicing the substrate in the dicing region to divide the substrate into separate packages, each having the connection pattern exposed to the exterior of the substrate;
mounting a solder bump on the via; and
mounting a lower package on the solder bump.
US15/637,220 2014-07-30 2017-06-29 Package and method of manufacturing the same Abandoned US20170301632A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/637,220 US20170301632A1 (en) 2014-07-30 2017-06-29 Package and method of manufacturing the same

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR10-2014-0097069 2014-07-30
KR1020140097069A KR101616625B1 (en) 2014-07-30 2014-07-30 Semiconductor package and method of manufacturing the same
US14/810,947 US9748179B2 (en) 2014-07-30 2015-07-28 Package and method of manufacturing the same
US15/637,220 US20170301632A1 (en) 2014-07-30 2017-06-29 Package and method of manufacturing the same

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US14/810,947 Division US9748179B2 (en) 2014-07-30 2015-07-28 Package and method of manufacturing the same

Publications (1)

Publication Number Publication Date
US20170301632A1 true US20170301632A1 (en) 2017-10-19

Family

ID=55180821

Family Applications (2)

Application Number Title Priority Date Filing Date
US14/810,947 Active US9748179B2 (en) 2014-07-30 2015-07-28 Package and method of manufacturing the same
US15/637,220 Abandoned US20170301632A1 (en) 2014-07-30 2017-06-29 Package and method of manufacturing the same

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US14/810,947 Active US9748179B2 (en) 2014-07-30 2015-07-28 Package and method of manufacturing the same

Country Status (2)

Country Link
US (2) US9748179B2 (en)
KR (1) KR101616625B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111816629A (en) * 2020-09-14 2020-10-23 甬矽电子(宁波)股份有限公司 Electromagnetic shielding packaging structure and manufacturing method thereof

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016080333A1 (en) * 2014-11-21 2016-05-26 株式会社村田製作所 Module
KR102117477B1 (en) * 2015-04-23 2020-06-01 삼성전기주식회사 Semiconductor package and manufacturing method thereof
US10037897B2 (en) * 2016-11-29 2018-07-31 Taiwan Semiconductor Manufacturing Co., Ltd. Inter-fan-out wafer level packaging with coaxial TIV for 3D IC low-noise packaging
JP2017204511A (en) * 2016-05-10 2017-11-16 ソニー株式会社 Semiconductor device, semiconductor device manufacturing method and electronic apparatus
CN107424974A (en) * 2016-05-24 2017-12-01 胡迪群 Package substrate with flush type noise shielding wall
WO2018053208A1 (en) * 2016-09-15 2018-03-22 Skyworks Solutions, Inc. Through-mold features for shielding applications
WO2018067578A1 (en) 2016-10-04 2018-04-12 Skyworks Solutions, Inc. Dual-sided radio-frequency package with overmold structure
US10103125B2 (en) * 2016-11-28 2018-10-16 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
KR102266668B1 (en) * 2016-12-02 2021-06-21 가부시키가이샤 무라타 세이사쿠쇼 high frequency module
KR102246040B1 (en) * 2016-12-14 2021-04-29 가부시키가이샤 무라타 세이사쿠쇼 Circuit module
US10497656B2 (en) * 2017-01-30 2019-12-03 Skyworks Solutions, Inc. Dual-sided module with land-grid array (LGA) footprint
KR102639101B1 (en) * 2017-02-24 2024-02-22 에스케이하이닉스 주식회사 Semiconductor package having electro-magnetic interference shielding structure
US10361145B2 (en) * 2017-07-18 2019-07-23 Skyworks Solutions, Inc. Through-mold openings for dual-sided packaged modules with ball grid arrays
EP3462486B1 (en) 2017-09-29 2021-03-24 Qorvo US, Inc. Process for making a double-sided module with electromagnetic shielding
JP6908127B2 (en) * 2017-11-02 2021-07-21 株式会社村田製作所 Circuit module
US10535612B2 (en) * 2017-12-15 2020-01-14 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
KR102446108B1 (en) * 2018-03-23 2022-09-22 가부시키가이샤 무라타 세이사쿠쇼 High-frequency modules and communication devices
CN214123862U (en) * 2018-03-23 2021-09-03 株式会社村田制作所 High-frequency module and communication device
US20200075547A1 (en) * 2018-08-31 2020-03-05 Qorvo Us, Inc. Double-sided integrated circuit module having an exposed semiconductor die
CN112385024B (en) * 2018-10-11 2023-11-10 深圳市修颐投资发展合伙企业（有限合伙） Fan-out packaging method and fan-out packaging board
US11201467B2 (en) 2019-08-22 2021-12-14 Qorvo Us, Inc. Reduced flyback ESD surge protection
CN114424333A (en) * 2019-09-19 2022-04-29 株式会社村田制作所 Module
US11463116B2 (en) * 2019-09-20 2022-10-04 Murata Manufacturing Co., Ltd. Radio frequency module and communication device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5886877A (en) * 1995-10-13 1999-03-23 Meiko Electronics Co., Ltd. Circuit board, manufacturing method therefor, and bump-type contact head and semiconductor component packaging module using the circuit board
US20090133917A1 (en) * 2007-11-28 2009-05-28 Shinko Electric Industries Co., Ltd. Multilayered Circuit Board for Connection to Bumps
US9129954B2 (en) * 2013-03-07 2015-09-08 Advanced Semiconductor Engineering, Inc. Semiconductor package including antenna layer and manufacturing method thereof

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19637018A1 (en) 1996-09-12 1998-03-19 Bayer Ag Process for the production of rigid and flexible circuits
US6949822B2 (en) 2000-03-17 2005-09-27 International Rectifier Corporation Semiconductor multichip module package with improved thermal performance; reduced size and improved moisture resistance
US7038917B2 (en) * 2002-12-27 2006-05-02 Vlt, Inc. Low loss, high density array interconnection
US7451539B2 (en) 2005-08-08 2008-11-18 Rf Micro Devices, Inc. Method of making a conformal electromagnetic interference shield
US7342303B1 (en) 2006-02-28 2008-03-11 Amkor Technology, Inc. Semiconductor device having RF shielding and method therefor
CN101617400A (en) * 2007-01-31 2009-12-30 富士通微电子株式会社 Semiconductor device and manufacture method thereof
US7745910B1 (en) * 2007-07-10 2010-06-29 Amkor Technology, Inc. Semiconductor device having RF shielding and method therefor
KR101126767B1 (en) * 2007-10-26 2012-03-29 삼성테크윈 주식회사 Method for Manufacturing Printed Circuit Board And Printed Circuit Board Manufactured by the Method
US8212339B2 (en) * 2008-02-05 2012-07-03 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
JP5195903B2 (en) * 2008-03-31 2013-05-15 株式会社村田製作所 Electronic component module and method for manufacturing the electronic component module
US8410584B2 (en) * 2008-08-08 2013-04-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
US8110441B2 (en) * 2008-09-25 2012-02-07 Stats Chippac, Ltd. Method of electrically connecting a shielding layer to ground through a conductive via disposed in peripheral region around semiconductor die
US20100110656A1 (en) * 2008-10-31 2010-05-06 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
US8110902B2 (en) * 2009-02-19 2012-02-07 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
US8212340B2 (en) * 2009-07-13 2012-07-03 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
US8378466B2 (en) * 2009-11-19 2013-02-19 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with electromagnetic interference shielding
US8569894B2 (en) * 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
TWI489610B (en) * 2010-01-18 2015-06-21 矽品精密工業股份有限公司 Method for making emi shielding package structure
US8199518B1 (en) * 2010-02-18 2012-06-12 Amkor Technology, Inc. Top feature package and method
US8946886B1 (en) * 2010-05-13 2015-02-03 Amkor Technology, Inc. Shielded electronic component package and method
KR101141443B1 (en) * 2010-05-31 2012-05-04 삼성전기주식회사 Method for manufacturing semiconductor package
KR101171512B1 (en) * 2010-06-08 2012-08-06 삼성전기주식회사 Method for manufacturing semiconductor package
KR101185457B1 (en) * 2011-01-07 2012-10-02 앰코 테크놀로지 코리아 주식회사 Semiconductor package for stack and method for manufacturing the same
JP5668627B2 (en) * 2011-07-19 2015-02-12 株式会社村田製作所 Circuit module
US8786060B2 (en) * 2012-05-04 2014-07-22 Advanced Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
US9172131B2 (en) * 2013-03-15 2015-10-27 Advanced Semiconductor Engineering, Inc. Semiconductor structure having aperture antenna
CN103400825B (en) * 2013-07-31 2016-05-18 日月光半导体制造股份有限公司 Semiconductor package part and manufacture method thereof
KR20140041643A (en) 2014-02-28 2014-04-04 삼성전기주식회사 Semiconductor package

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5886877A (en) * 1995-10-13 1999-03-23 Meiko Electronics Co., Ltd. Circuit board, manufacturing method therefor, and bump-type contact head and semiconductor component packaging module using the circuit board
US20090133917A1 (en) * 2007-11-28 2009-05-28 Shinko Electric Industries Co., Ltd. Multilayered Circuit Board for Connection to Bumps
US9129954B2 (en) * 2013-03-07 2015-09-08 Advanced Semiconductor Engineering, Inc. Semiconductor package including antenna layer and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111816629A (en) * 2020-09-14 2020-10-23 甬矽电子(宁波)股份有限公司 Electromagnetic shielding packaging structure and manufacturing method thereof
CN111816629B (en) * 2020-09-14 2020-12-15 甬矽电子(宁波)股份有限公司 Electromagnetic shielding packaging structure and manufacturing method thereof

Also Published As

Publication number Publication date
KR20160014913A (en) 2016-02-12
US20160035678A1 (en) 2016-02-04
KR101616625B1 (en) 2016-04-28
US9748179B2 (en) 2017-08-29

Similar Documents

Publication Publication Date Title
US9748179B2 (en) Package and method of manufacturing the same
US9401333B2 (en) Semiconductor device
US20110298111A1 (en) Semiconductor package and manufactring method thereof
US9706661B2 (en) Electronic device module and manufacturing method thereof
US8043892B2 (en) Semiconductor die package and integrated circuit package and fabricating method thereof
US9362209B1 (en) Shielding technique for semiconductor package including metal lid
US20150131231A1 (en) Electronic component module and manufacturing method thereof
JP5729186B2 (en) Semiconductor device and manufacturing method thereof
US7915715B2 (en) System and method to provide RF shielding for a MEMS microphone package
US10553954B2 (en) Wireless device
CN111834337A (en) Electronic component module and method for manufacturing electronic component module
US10347571B1 (en) Intra-package interference isolation
US11382207B2 (en) Electronic device module and method of manufacturing electronic device module
CN106711123A (en) Semiconductor package and method of manufacturing the same
US20210120664A1 (en) Electronic device module
KR101141443B1 (en) Method for manufacturing semiconductor package
KR101741648B1 (en) Semiconductor package having electromagnetic waves shielding means, and method for manufacturing the same
US20170263571A1 (en) Electronic component built-in substrate and method for manufacturing the same
US10123415B2 (en) Wiring substrate and production method therefor
KR101350610B1 (en) Semiconductor package
KR20130016560A (en) Semiconductor package and manufacturing method thereof
KR20160134215A (en) Semiconductor package and method for manufacturing the same

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION