US20170141142A1

US20170141142A1 - Optoelectronics and cmos integration on goi substrate

Info

Publication number: US20170141142A1
Application number: US15/420,115
Authority: US
Inventors: Effendi Leobandung; Ning Li; Devendra K. Sadana
Original assignee: International Business Machines Corp
Current assignee: International Business Machines Corp
Priority date: 2015-03-18
Filing date: 2017-01-31
Publication date: 2017-05-18
Anticipated expiration: 2035-03-18
Also published as: GB2538594A; US11114479B2; GB201604088D0; US20190214413A1; DE102016105057B4; CN105990375A; US20160276330A1; DE102016105057A1; US10283537B2; US9601476B2; CN105990375B; US9362444B1; US10784292B2; US20190221592A1; GB2538594B

Abstract

A single chip including an optoelectronic device on the semiconductor layer in a first region, the optoelectronic device comprises a bottom cladding layer, an active region, and a top cladding layer, wherein the bottom cladding layer is above and in direct contact with the semiconductor layer, the active region is above and in direct contact with the bottom cladding layer, and the top cladding layer is above and in direct contact with the active region, a silicon device on the substrate extension layer in a second region, a device insulator layer substantially covering both the optoelectronic device in the first region and the silicon device in the second region, and a waveguide embedded within the device insulator layer in direct contact with a sidewall of the active region of the optoelectronic device.

Description

BACKGROUND

The present invention generally relates to semiconductor device manufacturing, and more particularly to the formation and integration of a III-V semiconductor optoelectronic device and a silicon complementary metal-oxide-semiconductor (CMOS) device on a single chip.
As micro-electronic systems continue to scale down, the resultant electrical interconnect density would have to accommodate increased power dissipation, signal delay and cross-talk, while running at extremely high clock speeds. Current trends indicate that in less than a decade the power consumed by interconnects might become the limiting factor in determining the switching speeds in integrated circuits. To overcome these problems the integration of optical interconnects and systems alongside conventional Silicon (Si) based micro-electronic circuits would be a major step forward. Light based intra and inter-chip communication would diminish latency considerably and reduce power consumption by eliminating capacitive interconnect loss. Improved opto-electronic integration can also help increase the speed of transceiver circuits used in optical communication systems, thereby increasing the overall bandwidth.

SUMMARY

According to one embodiment of the present invention, a method is provided. The method may include forming a semiconductor-on-insulator (SOI) substrate in a first region and a second region, the SOI substrate includes a semiconductor layer on a first insulator layer, and the first insulator layer is on a substrate; removing the semiconductor layer and the insulator layer from the second region, wherein a top surface of the substrate is exposed; forming a second insulator layer on the semiconductor layer in the first region; forming a substrate extension layer on the exposed substrate in the second region; forming the device on the substrate extension layer; forming a device insulator layer covering the device in the second region; forming a waveguide in the second insulator layer; and forming the optoelectronic device in the first region, the optoelectronic device has a bottom cladding layer, an active region, and a top cladding layer, wherein the bottom cladding layer is on the semiconductor layer, the active region is on the bottom cladding layer, and the top cladding layer is on the active region.
According to another embodiment of the present invention, a method is provided. The method may include forming a stack of layers on a substrate in a first region and in a second region, the stack of layers include a semiconductor layer on the substrate, a first insulator layer on the semiconductor layer, a waveguide on the first insulator layer, a second insulator layer on the waveguide, and a device base layer on the second insulator layer; forming the device on the device base layer in the second region; forming a device insulator layer on the device and on the device base layer in the second region; and forming the optoelectronic device in the first region, the optoelectronic device has a bottom cladding layer, an active region, and a top cladding layer, wherein the bottom cladding layer is on the semiconductor layer, the active region is on the bottom cladding layer, and the top cladding layer is on the active region.
According to another embodiment of the present invention, a structure is provided. The structure may include a silicon substrate in a first region and a second region of a single chip; a germanium layer above the substrate in at least the first region; the optoelectronic device on the germanium layer in the first region, the optoelectronic device has a bottom cladding layer, an active region adjacent to a waveguide, and a top cladding layer, wherein the bottom cladding layer is on the germanium layer, the active region is on the bottom cladding layer, and the top cladding layer is on the active region; and the silicon device on a silicon layer in the second region.

BRIEF DESCRIPTION OF THE DRAWINGS

The following detailed description, given by way of example and not intended to limit the invention solely thereto, will best be appreciated in conjunction with the accompanying drawings, in which:

FIG. 1 is a cross section view of a semiconductor structure, according to an exemplary embodiment;

FIG. 2 is a cross section view of the semiconductor structure and illustrates the removal of a semiconductor layer and first insulator layer from a first region of a semiconductor-on-insulator (SOI) substrate, according to an exemplary embodiment;

FIG. 3 is a cross section view of the semiconductor structure and illustrates the formation of a device in a second region of the SOI substrate, according to an exemplary embodiment;

FIG. 4 is a cross section view of the semiconductor structure and illustrates the formation of a waveguide above the semiconductor layer in the first region, according to an exemplary embodiment;

FIG. 5 is a cross section view of the semiconductor structure and illustrates the formation of an optoelectronic device in the first region, according to an exemplary embodiment;

FIG. 6 is a cross section view of the semiconductor structure and illustrates the formation of an optoelectronic device contact and a device contact, according to an exemplary embodiment;

FIG. 7 is a cross section view of the semiconductor structure and illustrates a top view of the semiconductor structure, according to an exemplary embodiment;

FIG. 8 is a cross section view of an alternative semiconductor structure and illustrates the formation of a stack of layers on a substrate, according to an exemplary embodiment;

FIG. 9 is a cross section view of the alternative semiconductor structure and illustrates the formation of a device in a second region of an SOI substrate, according to an exemplary embodiment; and

FIG. 10 is a cross section view of the alternative semiconductor structure and illustrates the formation of an optoelectronic device in a first region of the SOI substrate, according to an exemplary embodiment.

The drawings are not necessarily to scale. The drawings are merely schematic representations, not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention. In the drawings, like numbering represents like elements.

DETAILED DESCRIPTION

Detailed embodiments of the claimed structures and methods are disclosed herein; however, it can be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. This invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this invention to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.
References in the specification to “one embodiment”, “an embodiment”, “an example embodiment”, etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
For purposes of the description hereinafter, the terms “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the disclosed structures and methods, as oriented in the drawing figures. The terms “overlying”, “atop”, “on top”, “positioned on” or “positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure may be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.
In the interest of not obscuring the presentation of embodiments of the present invention, in the following detailed description, some processing steps or operations that are known in the art may have been combined together for presentation and for illustration purposes and in some instances may have not been described in detail. In other instances, some processing steps or operations that are known in the art may not be described at all. It should be understood that the following description is rather focused on the distinctive features or elements of various embodiments of the present invention.
The present invention generally relates to semiconductor device manufacturing, and more particularly to the formation and integration of a III-V semiconductor optoelectronic device and a silicon complementary metal-oxide-semiconductor (CMOS) device on a single chip. Ideally, it may be desirable to form a III-V semiconductor optoelectronic device and a silicon CMOS device on the same chip to create new pathways for optical interconnects and to reduce production time and cost. One way to fabricate a III-V semiconductor optoelectronic device and a silicon CMOS device on a single chip may include forming a silicon substrate in a first and second region on a single chip, forming a germanium layer in the first region, using the germanium layer as a seed layer to form a III-V semiconductor optoelectronic device, and using the silicon in the second region as a seed layer to form a silicon CMOS device. One embodiment by which to form an integrated III-V semiconductor optoelectronic device and a silicon CMOS device on the same chip is described in detail below referring to the accompanying drawings FIGS. 1-10. It should be noted, an optoelectronic device may include, for example, an optoelectronic transmitting device, such as a laser, or an optoelectronic receiving device, such as a detector, but other devices may be used.
With reference to FIG. 1, a demonstrative illustration of a structure 100 is provided during an intermediate step of a method of fabricating a III-V semiconductor optoelectronic device and a Si CMOS device on a single chip, according to an embodiment. More specifically, the method can start with providing a semiconductor-on-insulator (SOI) substrate.
The SOI substrate may be in a first region 101 and in a second region 103 of a single chip. The SOI substrate may include (from bottom to top) a substrate 102, a first insulator layer 104, and a semiconductor layer 106. The SOI substrate may be formed using any SOI substrate formation technique known in the art, such as, for example, Separation by Ion Implantation of Oxygen (SIMOX) or layer transfer. If a layer transfer process is employed, an optional thinning step may follow the bonding of two semiconductor wafers together. The optional thinning step can reduce the thickness of a layer to a desirable thickness.
The substrate 102 may include; a bulk semiconductor substrate, a layered semiconductor substrate (e.g., Si/SiGe), a silicon-on-insulator substrate (SOI), or a SiGe-on-insulator substrate (SGOI). The substrate 102 may include any semiconductor material known in the art, such as, for example; Si, Ge, SiGe, SiC, SiGeC, Ga, GaAs, InAs, InP, or other elemental or compound semiconductors. In an embodiment, the substrate 102 is a bulk silicon substrate. The substrate 102 may include, for example; an n-type, p-type, or undoped semiconductor material and may have a monocrystalline, polycrystalline, or amorphous structure.
The first insulator layer 104 may be formed on the substrate 102 using any deposition techniques known in the art, such as, for example; ion implantation, thermal or plasma oxidation or nitridation, chemical vapor deposition, and/or physical vapor deposition. The first insulator layer 104 may be any dielectric material known in the art, such as, for example; oxides, nitrides, or oxynitrides. The first insulator layer 104 may have a thickness ranging from about 1 nm to about 500 nm, but other thicknesses may be used. In an embodiment, the first insulator layer 104 is SiO₂having a thickness of about 200 nm. In another embodiment, the first insulator layer 104 may include multiple dielectric layers or a stack of dielectric layers including a silicon oxide layer and/or a silicon nitride layer. It should be noted; the first insulator layer 104 may also be referred to as a buried dielectric layer or a buried oxide (BOX) layer.
The semiconductor layer 106 may be formed on the first insulator layer 104 using any deposition technique known in the art, such as, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, or physical vapor deposition. The semiconductor layer 106 may be any semiconductor material known in the art, such as, for example, Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other semiconductors. The semiconductor layer 106 may have a thickness ranging from about 1 nm to about 500 nm, but other thicknesses may be used. In an embodiment, the semiconductor layer 106 is germanium and has a thickness of about 100 nm.
In an embodiment, a III-V semiconductor layer may be subsequently formed on the semiconductor layer 106 (further described below). The lattice mismatch is larger between silicon and a III-V semiconductor than between germanium and the III-V semiconductor; therefore, germanium may be a better material to use as the semiconductor layer 106 for the subsequent formation of a III-V semiconductor optoelectronic device.
With reference to FIG. 2, a demonstrative illustration of the structure 100 is provided during an intermediate step of a method of fabricating a III-V semiconductor optoelectronic device and a Si CMOS device on a single chip, according to an embodiment. More specifically, the method can include removing the semiconductor layer 106 and the first insulator layer 104 from the second region 103 and forming a second insulator layer 108 on the semiconductor layer 106.
It should be noted, germanium may be a good material for the growth of a III-V semiconductor optoelectronic device; however, silicon may be better suited for the formation of other devices, such as, for example, a CMOS device. Therefore, the germanium may be removed from the second region 103 to allow for subsequent formation of silicon devices.
The semiconductor layer 106 and the first insulator layer 104 may be removed from the second region 103 using any etching technique known in the art, such as, for example, photolithography and/or reactive ion etching process. A top surface of the substrate 102 may be exposed in the second region 103.
The second insulator layer 108 may be formed on the semiconductor layer 106 using any deposition technique known in the art, such as, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, or physical vapor deposition. In an embodiment, the second insulator layer 108 is formed on the semiconductor layer 106 by depositing a blanket insulator layer over the semiconductor layer 106 in the first region 101 and the substrate 102 in the second region 103 followed by an etching process removing the blanket insulator layer from the second region 103. The second insulator layer 108 may remain on the semiconductor layer 106 and on sidewalls of the semiconductor layer 106 and first insulator layer 104 adjacent to the second region 103. The second insulator layer 108 may be any dielectric material known in the art, such as, for example, oxides, nitrides, or oxynitrides. The second insulator layer 108 may have a thickness ranging from about 1 μm to about 5 μm, but other thicknesses may be used. In an embodiment, the second insulator layer 108 is the same material as the first insulator layer (e.g., SiO₂) and has a thickness of about 2 μm above the semiconductor layer 106.
With reference to FIG. 3, a demonstrative illustration of the structure 100 is provided during an intermediate step of a method of fabricating a III-V semiconductor optoelectronic device and a Si CMOS device on a single chip, according to an embodiment. More specifically, the method can include forming a device 112 on a substrate extension layer 110 in the second region 103.
The substrate extension layer 110 may be formed on the substrate 102 in the second region 103 using any deposition technique known in the art, such as, for example, epitaxial growth, chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, or physical vapor deposition. The substrate extension layer 110 may be any semiconductor material known in the art, such as, for example, Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other semiconductors. In an embodiment, the substrate extension layer 110 is the same material as the substrate 102 (e.g., Si) and the substrate extension layer 110 is grown on the exposed substrate 102 in the second region 103 using an epitaxial growth process.
The device 112 may be formed on the substrate extension layer 110 using any device formation technique known in the art, such as, for example, a deposition, masking, and etching process. The device 112 may be any electrical device known in the art, such as, for example, a Si CMOS device, SiGe or III-V channel MOSFETs, bipolar junction transistors, or any other devices used in the art. In an embodiment, the device 112 is a Si CMOS device. The device 112 may be used to send signals to a laser or detector, as is known in the art. In the illustrated embodiment, two sets of three devices 112 are formed on the substrate extension layer 110; however, other device configurations may be used.
A device insulator layer 109 may be formed on the device 112 using any deposition technique known in the art, such as, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, or physical vapor deposition. The device insulator layer 109 may be any dielectric material known in the art, such as, for example, oxides, nitrides, or oxynitrides. In an embodiment, the device insulator layer 109 is the same material as the first and second insulator layers 104, 108 (e.g., SiO₂). A top surface of the second insulator layer 108 and the device insulator layer 109 may be planarized using any polishing technique known in the art, such as, for example, a chemical-mechanical polishing process.
With reference to FIG. 4, a demonstrative illustration of the structure 100 is provided during an intermediate step of a method of fabricating a III-V semiconductor optoelectronic device and a Si CMOS device on a single chip, according to an embodiment. More specifically, the method can include forming a waveguide 114 in the first region 101.
The waveguide 114 may be formed in the first region 101 by etching a trench in the second insulator layer 108, forming the waveguide 114 in the trench, and reforming the second insulator layer 108 above the waveguide 114. The trench may be formed in the second insulator layer 108 using any etching technique known in the art, such as, for example, a reactive ion etching process. A portion of the second insulator layer 108 may remain underneath the trench. The portion of the second insulator layer 108 remaining underneath the trench may have a thickness of about 1 μm. The trench may not extent to the second region 103 (i.e., there may be a portion of the second insulator layer 108 between the trench and the second region 103).
The waveguide 114 may be deposited in the trench using any deposition technique known in the art, such as, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, or physical vapor deposition. The waveguide 114 may be any waveguide material known in the art, such as, for example, nitrides, oxides, or oxynitrides. In an embodiment, the waveguide 114 is SiN.
The second insulator layer 108 may be reformed on the waveguide 114 using any deposition technique known in the art, such as, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, or physical vapor deposition. The top surface of the second insulator layer 108 may be planarized using any polishing technique known in the art, such as, for example, a chemical-mechanical polishing process. In an embodiment, the second insulator layer 108 has a thickness of about 1 μm above a top surface of the waveguide 114.
With reference to FIG. 5, a demonstrative illustration of the structure 100 is provided during an intermediate step of a method of fabricating a III-V semiconductor optoelectronic device and a Si CMOS device on a single chip, according to an embodiment. More specifically, the method can include forming an optoelectronic device 115 on the semiconductor layer 106 in the first region 101.
Various types of structures have been advocated for semiconductor lasers and detectors; one typical structure is the double hetero structure. The double hetero structure is a structure such that, using two types of different compound semiconductors, the compound semiconductor with a smaller bandgap is sandwiched between the compound semiconductors with larger bandgaps.
The optoelectronic device 115 may include (from bottom to top) a bottom cladding layer 116, an active region 118, and a top cladding layer 117 (e.g., a double hetero structure). The optoelectronic device 115 may have a width (w) ranging from about 1 μm to about 10 μm and a length ranging from about 100 μm to about 500 μm, but other dimensions may be used.
The optoelectronic device 115 may be formed by etching a trench in the second insulator layer 108 using any etching technique known in the art, such as, for example, a photolithography and/or reactive ion etching process. The trench may be formed in the first region 101 and may expose a top surface of the semiconductor layer 106 and a sidewall of the waveguide 114.
The bottom cladding layer 116 may be formed in the trench and on the semiconductor layer 106 using any deposition technique known in the art, such as, for example, epitaxial growth or chemical vapor deposition. The bottom cladding layer 116 may include any semiconductor material known in the art, such as, for example, IV semiconductors and/or III-V semiconductors. In an embodiment, the bottom cladding layer 116 is AlGaAs. The bottom cladding layer 116 may be doped in-situ and may be p-type or n-type.
The active region 118 may be formed on the bottom cladding layer 116 using any deposition technique known in the art, such as, for example, epitaxial growth or chemical vapor deposition. The active region 118 may include any semiconductor material known in the art, such as, for example, IV semiconductors and/or III-V semiconductors. In an embodiment, the active region 118 is GaAs formed using epitaxial growth. The active region 118 may have the same lattice structure as the bottom cladding layer 116, however, the active region 118 may have a lower bandgap. The active region 118 may be in contact with the sidewall of the waveguide 114, such that signals can flow between the active region 118 and the waveguide 114.
The top cladding layer 117 may be formed on the active region 118 using any deposition technique known in the art, such as, for example, epitaxial growth or chemical vapor deposition. The top cladding layer 117 may include any semiconductor material known in the art, such as, for example, IV semiconductors and/or III-V semiconductors. The top cladding layer 117 may be doped in-situ and may be p-type or n-type. In an embodiment, the top cladding layer 117 is the same material as the bottom cladding layer 116 (e.g., AlGaAs) and may have an opposite charge from the bottom cladding layer 116 (e.g., a p-type top cladding layer 117 and an n-type bottom cladding layer 116). The top and bottom cladding layers 117, 116 may be used as a barrier layer which may confine electrons in the active region 118.
With reference to FIG. 6, a demonstrative illustration of the structure 100 is provided during an intermediate step of a method of fabricating a III-V semiconductor optoelectronic device and a Si CMOS device on a single chip, according to an embodiment. More specifically, the method can include forming an optoelectronic device contact 122 and a device contact 124 through a top insulator layer. It should be noted, for illustrative purposes, the first insulator layer 104, the second insulator layer 108, the device insulator layer 109 and the top insulator layer may be shown as a combined insulator 111.
The top insulator layer may be formed on the optoelectronic device 115, on the second insulator layer 108, and on the device insulator layer 109 using any deposition techniques known in the art, such as, for example; ion implantation, thermal or plasma oxidation or nitridation, chemical vapor deposition, and/or physical vapor deposition. The top insulator layer may be any dielectric material known in the art, such as, for example; oxides, nitrides, or oxynitrides. In an embodiment, the top insulator layer is the same material as the first insulator layer 104, the second insulator layer 108, and the device insulator layer 109 (e.g., SiO₂).
An optoelectronic device contact trench and a device contact trench may be etched in the combined insulator 111 using any etching technique known in the art, such as, for example, a photolithography and/or reactive ion etching process. The optoelectronic device contact trench may include two trenches (e.g., a first trench and a second trench). The first trench may extend through the combined insulator 111 and expose a top surface of the top cladding layer 116. A second trench may extend through the combined insulator 111 and expose a top surface of the bottom cladding layer 117. The device contact trench may include a set of trenches corresponding to the number of devices used. The device contact trench may extend through the combined insulator 111 and expose a top surface of the device 112.
The optoelectronic device contact 122 may be formed in the optoelectronic device contact trench using any deposition technique known in the art, such as, for example, atomic layer deposition, molecular layer deposition, chemical vapor deposition, in-situ radical assisted deposition, metalorganic chemical vapor deposition, molecular beam epitaxy, physical vapor deposition, sputtering, plating, evaporation, ion beam deposition, electron beam deposition, laser assisted deposition, chemical solution deposition, or any combination thereof. The optoelectronic device contact 122 may be any conductive material known in the art, such as, for example, tungsten, aluminum, silver, gold, alloys thereof, or any other conductive material. A layer of silicide 113 may line the bottom of the optoelectronic device contact 122.
The device contact 124 may be formed in the device contact trench using any deposition technique known in the art, such as, for example, atomic layer deposition, molecular layer deposition, chemical vapor deposition, in-situ radical assisted deposition, metalorganic chemical vapor deposition, molecular beam epitaxy, physical vapor deposition, sputtering, plating, evaporation, ion beam deposition, electron beam deposition, laser assisted deposition, chemical solution deposition, or any combination thereof. The device contact 124 may be any conductive material known in the art, such as, for example, tungsten, aluminum, silver, gold, alloys thereof, or any other conductive material. A layer of silicide 119 may line the bottom of the device contact 124.
With reference to FIG. 7, a demonstrative illustration of the structure 100 is provided during an intermediate step of a method of fabricating a III-V semiconductor optoelectronic device and a Si CMOS device on a single chip, according to an embodiment. More specifically, the optoelectronic device 115 (described above) may include a set of lasers 115 a and a set of detectors 115 b. The lasers 115 a may connect to the detectors 115 b (i.e., intra-chip connections) or to separate detectors (i.e., inter-chip connections). In an embodiment, there are two first regions 101, one region having the lasers 115 a and another having the detectors 115 b, where the second region 103 is between the two first regions 101. It should be noted, FIG. 7 is a top view of structure 100. Additionally, FIG. 7 is an exemplary illustration of a possible configuration, but other configurations may be used.
With reference to FIG. 8, a demonstrative illustration of a structure 200 is provided during an intermediate step of a method of fabricating a III-V semiconductor optoelectronic device and a Si CMOS device on a single chip, according to an embodiment. More specifically, the method can start with a stack of layers including (from bottom to top) the substrate 102, a semiconductor layer 206, a first insulator layer 204, a waveguide 214, a second insulator 208, and a device base layer 210. It should be noted, structure 200 is exemplary of a waveguide-first embodiment (rather than a device-first embodiment as illustrated in FIGS. 1-6).
The semiconductor layer 206 may be formed on the substrate 102. The semiconductor layer 206 may be a similar material, and formed using a similar process, as the semiconductor layer 106 illustrated in FIG. 1. The first insulator layer 204 may be formed on the semiconductor layer 206. The first insulator layer 204 may be a similar material, and formed using a similar process, as the first insulator layer 104 illustrated in FIG. 1. The waveguide 214 may be formed on the first insulator layer 104. The waveguide 214 may be a similar material, and formed using a similar process, as the waveguide 114 illustrated in FIG. 4. The second insulator layer 208 may be formed on the waveguide 214. The second insulator 208 may be a similar material, and formed using a similar process, as the second insulator layer 108 illustrated in FIG. 2. The device base layer 210 may be formed on the second insulator layer 208. The device base layer 210 may be a similar material, and formed using a similar process, as the substrate extension layer 110 illustrated in FIG. 3.
The stack of layers may be in the first region 101 and in the second region 103. In an embodiment, the substrate 102 is silicon, the semiconductor layer 206 is germanium, the first insulator layer 204 is SiO₂, the second insulator layer 208 is SiO₂, the waveguide 214 is SiN, and the device base layer 210 is silicon.
With reference to FIG. 9, a demonstrative illustration of the structure 200 is provided during an intermediate step of a method of fabricating a III-V semiconductor optoelectronic device and a Si CMOS device on a single chip, according to an embodiment. More specifically, the method can include forming a device 212 on the device base layer 210 in the second region 103. The device 212 may be a similar material, and formed using a similar process, as the device 112 illustrated in FIG. 3. A device insulator layer 209 may be formed on the device 212 and the device base layer 210. The device insulator layer 209 may be a similar material, and formed using a similar process, as the device insulator layer 109 illustrated in FIG. 3.
With reference to FIG. 10, a demonstrative illustration of the structure 200 is provided during an intermediate step of a method of fabricating a III-V semiconductor optoelectronic device and a Si CMOS device on a single chip, according to an embodiment. More specifically, the method can include forming an optoelectronic device 215 in the first region 101.
The optoelectronic device 215 may be similar materials, and formed using a similar process, as the optoelectronic device 115 illustrated in FIG. 5. The optoelectronic device 215 may include a bottom cladding layer 216, an active region 218, and a top cladding layer 217 formed in a trench on a top surface of the semiconductor layer 206. The structure 200 may be similar to structure 100; however, the waveguide 214 may extend underneath the device 212.
One benefit to having a laser/detector formed on the same chip as a device may include quicker processing times and lower processing costs. Germanium may be used as the semiconductor seed layer for the laser/detector because a closer lattice structure between germanium and a III-V semiconductor may result in less stress and/or misfit dislocations. The germanium may be grown on a silicon substrate or oxide such that the germanium can bridge the gap in lattice mismatch between a silicon substrate and a III-V semiconductor laser/detector.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The terminology used herein was chosen to best explain the principles of the embodiment, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

What is claimed is:

1. A single chip comprising:

a semiconductor-on-insulator (SOI) substrate in a first region, the SOI substrate includes a semiconductor layer on a first insulator layer, and the first insulator layer is on a bulk substrate;

a substrate extension layer on the bulk substrate in a second region, wherein an upper surface of the substrate extension layer is above an upper surface of the semiconductor layer;

an optoelectronic device on the semiconductor layer in the first region, the optoelectronic device comprises a bottom cladding layer, an active region, and a top cladding layer, wherein the bottom cladding layer is above and in direct contact with the semiconductor layer, the active region is above and in direct contact with the bottom cladding layer, and the top cladding layer is above and in direct contact with the active region;

a silicon device on the substrate extension layer in the second region;

a device insulator layer substantially covering both the optoelectronic device in the first region and the silicon device in the second region; and

a waveguide embedded within the device insulator layer in direct contact with a sidewall of the active region of the optoelectronic device.

2. The single chip according to claim 1, wherein the optoelectronic device comprises a III-V semiconductor material.

3. The single chip according to claim 1, wherein both the top cladding layer and the bottom cladding layer are AlGaAs and the active region is GaAs.

4. The single chip according to claim 1, wherein the silicon device is a silicon complementary metal-oxide-semiconductor (CMOS) device.

5. The single chip according to claim 1, further comprising:

a first contact, a second contact, and a device contact, wherein the first contact is directly connected to the top cladding layer, the second contact is directly connected to the bottom cladding layer, and the device contact is directly connected to the silicon device.

6. The single chip according to claim 1, wherein the semiconductor layer is germanium.

7. A single chip comprising:

a optoelectronic device on top of a semiconductor layer of a silicon-on-insulator substrate in a first region of the single chip, the silicon-on-insulator substrate comprises the semiconductor layer above and in direct contact with a first insulator layer, and the first insulator layer is on a bulk silicon substrate;

a silicon device on top of the bulk silicon substrate in a second region of the single chip;

wherein an upper surface of the bulk silicon substrate in the first region is below an upper surface of the bulk silicon substrate in the second region.

8. The single chip according to claim 7, wherein the optoelectronic device comprises a III-V semiconductor material.

9. The single chip according to claim 7, wherein the optoelectronic device comprises AlGaAs cladding layers and a GaAs active region.

10. The single chip according to claim 7, wherein the silicon device is a silicon complementary metal-oxide-semiconductor (CMOS) device.

11. The single chip according to claim 7, further comprising:

a first contact and a device contact, wherein the first contact is directly connected to the optoelectronic device and the device contact is directly connected to the silicon device.

12. The single chip according to claim 7, wherein the optoelectronic device comprises a bottom cladding layer, an active region, and a top cladding layer, wherein the bottom cladding layer is above and in direct contact with the semiconductor layer, the active region is above and in direct contact with the bottom cladding layer, and the top cladding layer is above and in direct contact with the active region.

13. The single chip according to claim 7, further comprising:

a device insulator layer substantially covering both the optoelectronic device in the first region and the silicon device in the second region.

14. The single chip according to claim 7, further comprising:

a waveguide embedded within a device insulator layer in direct contact with a sidewall of an active region of the optoelectronic device.

15. A structure comprising:

a silicon substrate in a first region and a second region of a single chip;

a germanium layer above the silicon substrate in at least the first region;

an optoelectronic device on the germanium layer in the first region, the optoelectronic device has a bottom cladding layer, an active region adjacent to and contacting a waveguide, and a top cladding layer, wherein the bottom cladding layer is on the germanium layer, the active region is on the bottom cladding layer, and the top cladding layer is on the active region; and

a silicon device on a silicon layer in the second region.

16. The structure according to claim 15, wherein the optoelectronic device comprises a III-V semiconductor material.

17. The structure according to claim 15, wherein both the top cladding layer and the bottom cladding layer are AlGaAs and the active region is GaAs.

18. The structure according to claim 15, wherein the silicon device is a silicon complementary metal-oxide-semiconductor (CMOS) device.

19. The structure according to claim 15, further comprising:

20. The structure according to claim 15, wherein an upper surface of the silicon layer in the second region is above an upper surface of the germanium layer in the first region.