US20090294897A1 - Seal ring structure for integrated circuits - Google Patents

Seal ring structure for integrated circuits Download PDF

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Publication number
US20090294897A1
US20090294897A1 US12/340,737 US34073708A US2009294897A1 US 20090294897 A1 US20090294897 A1 US 20090294897A1 US 34073708 A US34073708 A US 34073708A US 2009294897 A1 US2009294897 A1 US 2009294897A1
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United States
Prior art keywords
seal ring
ring structure
structure according
region
integrated circuit
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Abandoned
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US12/340,737
Inventor
Tung-Hsing Lee
Tien-Chang Chang
Yuan-Hung Chung
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MediaTek Inc
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MediaTek Inc
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Publication date
Application filed by MediaTek Inc filed Critical MediaTek Inc
Priority to US12/340,737 priority Critical patent/US20090294897A1/en
Assigned to MEDIATEK INC. reassignment MEDIATEK INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHANG, TIEN-CHANG, CHUNG, YUAN-HUNG, LEE, TUNG-HSING
Priority to JP2009064272A priority patent/JP5064431B2/en
Priority to CN2009101362916A priority patent/CN101593737B/en
Priority to TW098115691A priority patent/TWI396255B/en
Publication of US20090294897A1 publication Critical patent/US20090294897A1/en
Priority to US12/850,640 priority patent/US8212323B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5225—Shielding layers formed together with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention related to semiconductor devices and, more particularly, to a seal ring structure for an integrated circuit that is capable of reducing substrate noise coupling.
  • an integrated circuit chip includes a seal ring used to protect it from moisture degradation or ionic contamination.
  • the seal ring is made of a stack of metal and contact/via layers and is manufactured step by step as sequential depositions of insulators and metals in conjunction together with the fabrication of the integrated circuit elements.
  • the noise such as digital noise
  • V DD digital power signal line
  • signal pad of a digital circuit propagates through the seal ring and adversely affects the performance of the sensitive analog and/or RF circuit.
  • FIG. 1 is a schematic, cross-sectional diagram showing a seal ring structure 524 according to the related art.
  • the seal ring structure 524 is divided into two portions including a first portion 524 a and a second portion 524 b spaced apart from the first portion 524 a. Between the first portion 524 a and the second portion 524 b, there is provided a chipped region 525 .
  • the second portion 524 b comprises a conductive rampart 701 that is made of a stack of metal layers (M 1 and M 2 ) and contact/via layers (C and V 1 ).
  • the second portion 524 b further comprises a P+ region 702 situated under the conductive rampart 701 and a P well 704 under the P+ region 702 .
  • the P+ region 702 and the P well 704 are isolated from the P+ region 602 and the P well 604 under the conductive rampart 601 of the first portion 524 a by a shallow trench isolation (STI) structure 760 .
  • STI shallow trench isolation
  • the seal ring structure in the present invention which comprises a seal ring structure for an integrated circuit, comprising: a seal ring disposed along a periphery of the integrated circuit, wherein the seal ring is divided into at least a first portion and a second portion, and wherein the second portion is positioned facing and shielding an analog and/or RF circuit block from a noise; a P+ region in a P substrate and positioned under the second portion; and a shallow trench isolation (STI) structure surrounding the P+ region and laterally extending underneath a conductive rampart of the second portion.
  • STI shallow trench isolation
  • the present invention provides a seal ring structure for an integrated circuit comprising: a seal ring disposed along a periphery of the integrated circuit, wherein the seal ring is divided into at least a first portion and a second portion, and wherein the second portion is positioned facing and shielding an analog and/or RF circuit block from a noise; a deep N well in a P substrate and positioned under the second portion; a P+ region within the deep N well; and a shallow trench isolation (STI) structure surrounding the P+ region.
  • STI shallow trench isolation
  • FIG. 1 is a schematic, cross-sectional diagram showing a seal ring structure according to the related art
  • FIG. 2 is a schematic, planar view of an integrated circuit chip with a seal ring structure in accordance with one embodiment of this invention
  • FIG. 3 is a perspective, enlarged top view showing layout of the second portion of the seal ring according to this invention.
  • FIG. 4 is a schematic, cross-sectional view taken along line I-I′ of FIG. 2 ;
  • FIG. 5 is a schematic, cross-sectional view illustrating another embodiment of this invention.
  • FIG. 6 is a schematic, cross-sectional view illustrating yet another embodiment of this invention.
  • FIG. 7 is a schematic, planar view of an integrated circuit chip with a seal ring structure in accordance with another preferred embodiment of this invention.
  • the present invention pertains to a seal ring structure for an integrated circuit chip.
  • the number of seal ring(s) in the seal ring structure depends on requirements and is not limited to what is illustrated in the embodiments. If there is an outer seal ring, it may be a continuous ring, while an inner seal ring may be divided into at least two portions including a conductive rampart that is situated in front of a sensitive analog and/or RF circuit block of the integrated circuit chip.
  • a deep N well under the conductive rampart shields the analog and/or RF circuit from substrate noise, which, for example, propagates through the outer seal ring, thereby reducing the noise-coupling effects.
  • the continuous outer seal ring keeps the moisture and corrosive substances from entering the IC.
  • the present invention is capable of mitigating or eliminating resistive coupling noise by extending underneath a separated metal rampart portion of an inner seal ring and/or removing a P well from underneath the separated metal rampart portion of the inner seal ring.
  • the resistive coupling is switching transients coupled resistively into bulk through P+ bulk contact, if bulk is biased with a switching ground.
  • FIG. 2 is a schematic, planar view of an integrated circuit chip 10 with a seal ring structure 12 in accordance with one embodiment of this invention.
  • FIG. 3 is a perspective, enlarged top view showing layout of the second portion of the seal ring according to this invention.
  • FIG. 4 is a schematic, cross-sectional view taken along line I-I′ of FIG. 2 .
  • the integrated circuit chip 10 comprises at least one analog and/or RF circuit block 14 , a digital circuit 16 and a seal ring structure 12 surrounding and protecting the analog and/or RF circuit block 14 and digital circuit 16 .
  • the integrated circuit chip 10 further comprises a plurality of input/output (I/O) pads 20 .
  • I/O input/output
  • noises such as those originated from a digital power V DD signal line or a signal output pad 20 a of the digital circuit 16 can propagates through the seal ring and adversely affects the performance of the sensitive analog and/or RF circuit 14 .
  • the noise propagation path 30 is specifically indicated in FIG. 2 .
  • the noise may also propagate through the substrate and adversely affects the sensitive analog and/or RF circuit 14 .
  • the present invention aims to tackle this problem.
  • the seal ring structure 12 which is disposed along the periphery of the chip, includes a continuous outer seal ring 122 and a discontinuous inner seal ring 124 .
  • a double seal ring structure 12 is shown in this embodiment, the number of seal ring(s) in the seal ring structure depends on requirements and is not limited to what is illustrated herein.
  • the outer seal ring 122 is continuous and the inner seal ring 124 is discontinuous in this embodiment, the outer one could be either continuous or discontinuous, and the inner one could be either continuous or discontinuous as well.
  • the inner seal ring 124 is divided into at least two portions including a first portion 124 a and a second portion 124 b spaced apart from the first portion 124 a. Between the first portion 124 a and the second portion 124 b, there is provided a chipped region 125 .
  • the first portion 124 a and the second portion 124 b are different from each other mainly underneath the main surface 100 a of the P substrate 100 .
  • the first portion 124 a comprises a conductive rampart 201 that is made of a stack of metal layers such as M 1 and M 2 and contact/via layers such as C and V 1 and is manufactured step by step as sequential depositions of insulators and metals in conjunction together with the fabrication of the integrated circuit elements.
  • the first portion 124 a further comprises a P+ region 202 situated under the conductive rampart 201 . There may not be P well under the P+ region 202 according to this invention.
  • the second portion 124 b may be positioned directly facing the analog and/or RF circuit block 14 for shielding the noise propagating through the continuous outer seal ring 122 .
  • the length of the second portion 124 b is equal to or greater than the span of the shielded analog and/or RF circuit block 14 .
  • the second portion 124 b comprises a conductive rampart 301 that is made of a stack of an annular polysilicon layer 300 , metal layers such as M 1 and M 2 and contact/via layers such as C and V 1 and is manufactured step by step as sequential depositions of insulators and metals in conjunction together with the fabrication of the integrated circuit elements.
  • FIG. 3 schematically shows the layout of the second portion 124 b of the inner seal ring 124 according to this invention.
  • the annular polysilicon layer 300 which is indicated by shadow region, is situated under the conductive rampart 301 and surrounds the small P+ region 302 .
  • the polysilicon layer 300 is provided on the STI structure 360 in order to support contact mechanical strength and to prevent die saw problem.
  • the STI structure 360 extends laterally underneath the conductive rampart 301 to increase the resistance, thereby reducing the substrate noise coupling.
  • the present invention features the seal ring structure underneath the main surface 100 a of the P substrate 100 .
  • the second portion 124 b further comprises a small P+ region 302 surrounded by shallow trench isolation (STI) structure 360 .
  • the small P+ region 302 has a minimized surface area and may be fabricated by using critical dimension design rules.
  • the small P+ region 302 allows the passage of moisture or ions in the fabrication processes. In another case, however, the P+ region 302 may be omitted or removed from underneath the conductive rampart 301 .
  • the removal of the P+ region 302 can increase the resistance thus suppressing the substrate resistive coupling noise.
  • FIG. 5 is a schematic, cross-sectional view illustrating another embodiment of this invention.
  • the seal ring structure 124 is divided into two portions including a first portion 124 a and a second portion 124 b spaced apart from the first portion 124 a. Between the first portion 124 a and the second portion 124 b, there is provided a chipped region 125 .
  • the second portion 124 b comprises a conductive rampart 301 that is made of a stack of metal layers (M 1 and M 2 ) and contact/via layers (C and V 1 ).
  • the second portion 124 b further comprises a P+ region 302 situated under the conductive rampart 301 .
  • the P+ region 302 are isolated from the P+ region 202 under the conductive rampart 201 of the first portion 124 a by STI structure 360 ′ that does not extend laterally underneath the conductive rampart 301 .
  • the P well is removed from the seal ring structure to increase the substrate resistance.
  • FIG. 6 is a schematic, cross-sectional view illustrating yet another embodiment of this invention.
  • the deep N well 310 may have a junction depth of about 19000-21000 angstroms.
  • the deep N well 310 may be grounded or coupled to a supply voltage, such as V DD . It is advantageous to use the present invention because the deep N well 310 situated under the second portion 124 b can suppress capacitive coupling.
  • FIG. 7 is a schematic, planar view of an integrated circuit chip 10 a with a seal ring structure 12 in accordance with another preferred embodiment of this invention, wherein like numeral numbers designate like regions, layers or elements.
  • the integrated circuit chip 10 a comprises at least one analog and/or RF circuit block 14 , a digital circuit 16 and a seal ring structure 12 surrounding and protecting the analog and/or RF circuit block 14 and digital circuit 16 .
  • the integrated circuit chip 10 a further comprises a plurality of I/O pads 20 . Noises such as those originated from a digital power V DD signal line or a signal output pad 20 a of the digital circuit 16 may propagate through the seal ring and adversely affects the performance of the sensitive analog and/or RF circuit block 14 .
  • the seal ring structure 12 includes a continuous outer seal ring 122 and a discontinuous inner seal ring 124 .
  • a double seal ring structure 12 is shown in this embodiment, the number of seal ring(s) in the seal ring structure depends on requirements and is not limited to what is illustrated herein.
  • the outer seal ring 122 is continuous and the inner seal ring 124 is discontinuous in this embodiment, the outer one could be either continuous or discontinuous, and the inner one could be either continuous or discontinuous as well.
  • the inner seal ring 124 is divided into two portions including a first portion 124 a and a second portion 124 b.
  • the second portion 124 b serves to shield the noise propagating through the outer seal ring 122 .
  • the length of the second portion 124 b is equal to or greater than the span of the shielded analog and/or RF circuit block 14 .
  • the ring structure of the second portion 124 b may be similar to that as set forth in FIG. 3 and FIG. 4 .
  • the second portion 124 b may be coupled to an independent ground or an independent supply voltage.
  • the second portion 124 b may be coupled to the independent ground through an independent pad and an interconnection trace.
  • independent used herein means that the ground, pad or supply voltage is not commonly used by the analog circuit, RF circuit or digital circuit.
  • the second portion 124 b may be coupled to an independent pad 20 b through an interconnection trace 124 c.
  • the interconnection trace 124 c may be comprised of a topmost metal layer of the integrated circuit chip 10 a and an aluminum layer (not shown).
  • the second portion 124 b could be coupled to an independent ground (not shown) or an independent supply voltage, such as V SS , and the noise coupling can be significantly reduced.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

A seal ring structure for an integrated circuit includes a seal ring disposed along a periphery of the integrated circuit, wherein the seal ring is divided into at least a first portion and a second portion, and wherein the second portion is positioned facing and shielding an analog and/or RF circuit block from a noise. A P+ region is provided in a P substrate and positioned under the second portion. A shallow trench isolation (STI) structure surrounds the P+ region and laterally extends underneath a conductive rampart of the second portion.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application claims the benefit of U.S. provisional application No. 61/057,185, filed May 29, 2008.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention related to semiconductor devices and, more particularly, to a seal ring structure for an integrated circuit that is capable of reducing substrate noise coupling.
  • 2. Description of the Prior Art
  • Advances in fabrication technology have enabled entire functional blocks, which previously had been implemented as plural chips on a circuit board, to be integrated onto a single IC. One particularly significant development is mixed-signal circuits, which combine analog circuitry and digital logic circuitry onto a single IC.
  • However, a major technical hurdle to implementing mixed-signal circuits has been the coupling of noise between different portions of the IC, for example, from the digital to the analog portions. Ordinarily, an integrated circuit chip includes a seal ring used to protect it from moisture degradation or ionic contamination. Typically, the seal ring is made of a stack of metal and contact/via layers and is manufactured step by step as sequential depositions of insulators and metals in conjunction together with the fabrication of the integrated circuit elements.
  • It has been found that the noise, such as digital noise, which, for example, may be originated from a digital power signal line such as VDD or signal pad of a digital circuit, propagates through the seal ring and adversely affects the performance of the sensitive analog and/or RF circuit.
  • FIG. 1 is a schematic, cross-sectional diagram showing a seal ring structure 524 according to the related art. As shown in FIG. 1, the seal ring structure 524 is divided into two portions including a first portion 524 a and a second portion 524 b spaced apart from the first portion 524 a. Between the first portion 524 a and the second portion 524 b, there is provided a chipped region 525. The second portion 524 b comprises a conductive rampart 701 that is made of a stack of metal layers (M1 and M2) and contact/via layers (C and V1). The second portion 524 b further comprises a P+ region 702 situated under the conductive rampart 701 and a P well 704 under the P+ region 702. The P+ region 702 and the P well 704 are isolated from the P+ region 602 and the P well 604 under the conductive rampart 601 of the first portion 524 a by a shallow trench isolation (STI) structure 760.
    • SUMMARY OF THE INVENTION
  • It is one object of the present invention to provide an improved seal ring structure of an integrated circuit chip, which is capable of reducing the digital noise coupling from a digital circuit.
  • The above object will be achieved by the seal ring structure in the present invention which comprises a seal ring structure for an integrated circuit, comprising: a seal ring disposed along a periphery of the integrated circuit, wherein the seal ring is divided into at least a first portion and a second portion, and wherein the second portion is positioned facing and shielding an analog and/or RF circuit block from a noise; a P+ region in a P substrate and positioned under the second portion; and a shallow trench isolation (STI) structure surrounding the P+ region and laterally extending underneath a conductive rampart of the second portion.
  • In one aspect, the present invention provides a seal ring structure for an integrated circuit comprising: a seal ring disposed along a periphery of the integrated circuit, wherein the seal ring is divided into at least a first portion and a second portion, and wherein the second portion is positioned facing and shielding an analog and/or RF circuit block from a noise; a deep N well in a P substrate and positioned under the second portion; a P+ region within the deep N well; and a shallow trench isolation (STI) structure surrounding the P+ region.
  • These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:
  • FIG. 1 is a schematic, cross-sectional diagram showing a seal ring structure according to the related art;
  • FIG. 2 is a schematic, planar view of an integrated circuit chip with a seal ring structure in accordance with one embodiment of this invention;
  • FIG. 3 is a perspective, enlarged top view showing layout of the second portion of the seal ring according to this invention;
  • FIG. 4 is a schematic, cross-sectional view taken along line I-I′ of FIG. 2;
  • FIG. 5 is a schematic, cross-sectional view illustrating another embodiment of this invention;
  • FIG. 6 is a schematic, cross-sectional view illustrating yet another embodiment of this invention; and
  • FIG. 7 is a schematic, planar view of an integrated circuit chip with a seal ring structure in accordance with another preferred embodiment of this invention.
    •  DETAILED DESCRIPTION
  • The present invention pertains to a seal ring structure for an integrated circuit chip. The number of seal ring(s) in the seal ring structure depends on requirements and is not limited to what is illustrated in the embodiments. If there is an outer seal ring, it may be a continuous ring, while an inner seal ring may be divided into at least two portions including a conductive rampart that is situated in front of a sensitive analog and/or RF circuit block of the integrated circuit chip.
  • A deep N well under the conductive rampart shields the analog and/or RF circuit from substrate noise, which, for example, propagates through the outer seal ring, thereby reducing the noise-coupling effects. The continuous outer seal ring keeps the moisture and corrosive substances from entering the IC. The present invention is capable of mitigating or eliminating resistive coupling noise by extending underneath a separated metal rampart portion of an inner seal ring and/or removing a P well from underneath the separated metal rampart portion of the inner seal ring. The resistive coupling is switching transients coupled resistively into bulk through P+ bulk contact, if bulk is biased with a switching ground.
  • Please refer to FIG. 2 to FIG. 4. FIG. 2 is a schematic, planar view of an integrated circuit chip 10 with a seal ring structure 12 in accordance with one embodiment of this invention. FIG. 3 is a perspective, enlarged top view showing layout of the second portion of the seal ring according to this invention. FIG. 4 is a schematic, cross-sectional view taken along line I-I′ of FIG. 2. As shown in FIG. 2, the integrated circuit chip 10 comprises at least one analog and/or RF circuit block 14, a digital circuit 16 and a seal ring structure 12 surrounding and protecting the analog and/or RF circuit block 14 and digital circuit 16.
  • The integrated circuit chip 10 further comprises a plurality of input/output (I/O) pads 20. As previously described, noises such as those originated from a digital power VDD signal line or a signal output pad 20 a of the digital circuit 16 can propagates through the seal ring and adversely affects the performance of the sensitive analog and/or RF circuit 14. The noise propagation path 30 is specifically indicated in FIG. 2. The noise may also propagate through the substrate and adversely affects the sensitive analog and/or RF circuit 14. The present invention aims to tackle this problem.
  • According to the present invention, the seal ring structure 12, which is disposed along the periphery of the chip, includes a continuous outer seal ring 122 and a discontinuous inner seal ring 124. Though a double seal ring structure 12 is shown in this embodiment, the number of seal ring(s) in the seal ring structure depends on requirements and is not limited to what is illustrated herein. Besides, though the outer seal ring 122 is continuous and the inner seal ring 124 is discontinuous in this embodiment, the outer one could be either continuous or discontinuous, and the inner one could be either continuous or discontinuous as well. The inner seal ring 124 is divided into at least two portions including a first portion 124 a and a second portion 124 b spaced apart from the first portion 124 a. Between the first portion 124 a and the second portion 124 b, there is provided a chipped region 125.
  • As shown in FIG. 4, the first portion 124 a and the second portion 124 b are different from each other mainly underneath the main surface 100 a of the P substrate 100. The first portion 124 a comprises a conductive rampart 201 that is made of a stack of metal layers such as M1 and M2 and contact/via layers such as C and V1 and is manufactured step by step as sequential depositions of insulators and metals in conjunction together with the fabrication of the integrated circuit elements. The first portion 124 a further comprises a P+ region 202 situated under the conductive rampart 201. There may not be P well under the P+ region 202 according to this invention.
  • The second portion 124 b may be positioned directly facing the analog and/or RF circuit block 14 for shielding the noise propagating through the continuous outer seal ring 122. Preferably, the length of the second portion 124 b is equal to or greater than the span of the shielded analog and/or RF circuit block 14. Above the main surface 100 a of the P substrate 100, likewise, the second portion 124 b comprises a conductive rampart 301 that is made of a stack of an annular polysilicon layer 300, metal layers such as M1 and M2 and contact/via layers such as C and V1 and is manufactured step by step as sequential depositions of insulators and metals in conjunction together with the fabrication of the integrated circuit elements.
  • FIG. 3 schematically shows the layout of the second portion 124 b of the inner seal ring 124 according to this invention. As shown in FIG. 3, the annular polysilicon layer 300, which is indicated by shadow region, is situated under the conductive rampart 301 and surrounds the small P+ region 302. The polysilicon layer 300 is provided on the STI structure 360 in order to support contact mechanical strength and to prevent die saw problem. The STI structure 360 extends laterally underneath the conductive rampart 301 to increase the resistance, thereby reducing the substrate noise coupling.
  • The present invention features the seal ring structure underneath the main surface 100 a of the P substrate 100. Under the conductive rampart 301, the second portion 124 b further comprises a small P+ region 302 surrounded by shallow trench isolation (STI) structure 360. According to this invention, the small P+ region 302 has a minimized surface area and may be fabricated by using critical dimension design rules. The small P+ region 302 allows the passage of moisture or ions in the fabrication processes. In another case, however, the P+ region 302 may be omitted or removed from underneath the conductive rampart 301. The removal of the P+ region 302 can increase the resistance thus suppressing the substrate resistive coupling noise. By extending the STI into underneath the conductive rampart 301 and by removing the P well from the inner seal ring 124, the resistive coupling effect can be mitigated or eliminated.
  • FIG. 5 is a schematic, cross-sectional view illustrating another embodiment of this invention. As shown in FIG. 5, the seal ring structure 124 is divided into two portions including a first portion 124 a and a second portion 124 b spaced apart from the first portion 124 a. Between the first portion 124 a and the second portion 124 b, there is provided a chipped region 125. The second portion 124 b comprises a conductive rampart 301 that is made of a stack of metal layers (M1 and M2) and contact/via layers (C and V1). The second portion 124 b further comprises a P+ region 302 situated under the conductive rampart 301. The P+ region 302 are isolated from the P+ region 202 under the conductive rampart 201 of the first portion 124 a by STI structure 360′ that does not extend laterally underneath the conductive rampart 301. The P well is removed from the seal ring structure to increase the substrate resistance.
  • FIG. 6 is a schematic, cross-sectional view illustrating yet another embodiment of this invention. As shown in FIG. 6, under the conductive rampart 301 of the second portion 124 b of the inner seal ring 124, P+ region 302, STI structure 360 and a deep N well 310 are provided. According to this invention, the deep N well 310 may have a junction depth of about 19000-21000 angstroms. The deep N well 310 may be grounded or coupled to a supply voltage, such as VDD. It is advantageous to use the present invention because the deep N well 310 situated under the second portion 124 b can suppress capacitive coupling.
  • FIG. 7 is a schematic, planar view of an integrated circuit chip 10 a with a seal ring structure 12 in accordance with another preferred embodiment of this invention, wherein like numeral numbers designate like regions, layers or elements. As shown in FIG. 7, likewise, the integrated circuit chip 10 a comprises at least one analog and/or RF circuit block 14, a digital circuit 16 and a seal ring structure 12 surrounding and protecting the analog and/or RF circuit block 14 and digital circuit 16. The integrated circuit chip 10 a further comprises a plurality of I/O pads 20. Noises such as those originated from a digital power VDD signal line or a signal output pad 20 a of the digital circuit 16 may propagate through the seal ring and adversely affects the performance of the sensitive analog and/or RF circuit block 14.
  • The seal ring structure 12 includes a continuous outer seal ring 122 and a discontinuous inner seal ring 124. Though a double seal ring structure 12 is shown in this embodiment, the number of seal ring(s) in the seal ring structure depends on requirements and is not limited to what is illustrated herein. Besides, though the outer seal ring 122 is continuous and the inner seal ring 124 is discontinuous in this embodiment, the outer one could be either continuous or discontinuous, and the inner one could be either continuous or discontinuous as well. The inner seal ring 124 is divided into two portions including a first portion 124 a and a second portion 124 b. The second portion 124 b serves to shield the noise propagating through the outer seal ring 122. Preferably, the length of the second portion 124 b is equal to or greater than the span of the shielded analog and/or RF circuit block 14.
  • The ring structure of the second portion 124 b may be similar to that as set forth in FIG. 3 and FIG. 4. According to this invention, the second portion 124 b may be coupled to an independent ground or an independent supply voltage. According to this invention, the second portion 124 b may be coupled to the independent ground through an independent pad and an interconnection trace. The term “independent” used herein means that the ground, pad or supply voltage is not commonly used by the analog circuit, RF circuit or digital circuit.
  • In this embodiment, the second portion 124 b may be coupled to an independent pad 20 b through an interconnection trace 124 c. The interconnection trace 124 c may be comprised of a topmost metal layer of the integrated circuit chip 10 a and an aluminum layer (not shown). By doing this, the second portion 124 b could be coupled to an independent ground (not shown) or an independent supply voltage, such as VSS, and the noise coupling can be significantly reduced.
  • Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (14)

1. A seal ring structure for an integrated circuit, comprising:
a seal ring disposed along a periphery of the integrated circuit, wherein the seal ring is divided into at least a first portion and a second portion, and wherein the second portion is positioned facing and shielding an analog and/or RF circuit block from a noise;
a P+ region in a P substrate and positioned under the second portion; and
a shallow trench isolation (STI) structure surrounding the P+ region and laterally extending underneath a conductive rampart of the second portion.
2. The seal ring structure according to claim 1 wherein the seal ring is discontinuous, the second portion is spaced apart from the first portion.
3. The seal ring structure according to claim 1 further comprising a continuous outer seal ring outside the seal ring.
4. The seal ring structure according to claim 1 wherein a length of the second portion is equal to or greater than a span of the shielded analog and/or RF circuit block.
5. The seal ring structure according to claim 1 wherein the second portion comprises a conductive rampart that is a stack comprising a polysilicon layer, a metal layer, a contact/via layer, or a combination thereof and is manufactured together with the fabrication of the integrated circuit.
6. The seal ring structure according to claim 1 wherein no P well is formed under the P+ region.
7. A seal ring structure for an integrated circuit, comprising:
a seal ring disposed along a periphery of the integrated circuit, wherein the seal ring is divided into at least a first portion and a second portion, and wherein the second portion is positioned facing and shielding an analog and/or RF circuit block from a noise;
a deep N well in a P substrate and positioned under the second portion;
a P+ region within the deep N well; and
a shallow trench isolation (STI) structure surrounding the P+ region.
8. The seal ring structure according to claim 7 wherein the seal ring is discontinuous, the second portion is spaced apart from the first portion.
9. The seal ring structure according to claim 7 further comprising a continuous outer seal ring outside the seal ring.
10. The seal ring structure according to claim 7 wherein a length of the second portion is equal to or greater than a span of the shielded analog and/or RF circuit block.
11. The seal ring structure according to claim 7 wherein the deep N well has a junction depth of about 19000-21000 angstroms.
12. The seal ring structure according to claim 7 wherein the deep N well is grounded or coupled to a supply voltage.
13. The seal ring structure according to claim 7 wherein the second portion comprises a conductive rampart that is a stack comprising a polysilicon layer, a metal layer, a contact/via layer, or a combination thereof and is manufactured together with the fabrication of the integrated circuit.
14. The seal ring structure according to claim 7 wherein no P well is formed under the P+ region.
US12/340,737 2008-05-29 2008-12-21 Seal ring structure for integrated circuits Abandoned US20090294897A1 (en)

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CN2009101362916A CN101593737B (en) 2008-05-29 2009-05-05 Seal ring structure for integrated circuits
TW098115691A TWI396255B (en) 2008-05-29 2009-05-12 Seal ring structure for integrated circuits
US12/850,640 US8212323B2 (en) 2008-05-29 2010-08-05 Seal ring structure for integrated circuits

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US8212323B2 (en) 2012-07-03
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US20090294929A1 (en) 2009-12-03
JP2009290197A (en) 2009-12-10

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