US20070190760A1 - Integrated parallel plate capacitors - Google Patents

Integrated parallel plate capacitors Download PDF

Info

Publication number
US20070190760A1
US20070190760A1 US11/275,544 US27554406A US2007190760A1 US 20070190760 A1 US20070190760 A1 US 20070190760A1 US 27554406 A US27554406 A US 27554406A US 2007190760 A1 US2007190760 A1 US 2007190760A1
Authority
US
United States
Prior art keywords
capacitor
perforations
plates
capacitor plates
sets
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US11/275,544
Other versions
US7645675B2 (en
Inventor
Douglas Coolbaugh
Hanyi Ding
Ebenezer Eshun
Michael Gordon
Zhong-Xiang He
Anthony Stamper
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US11/275,544 priority Critical patent/US7645675B2/en
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GORDON, MICHAEL D., HE, ZHONG-XIANG, COOLBAUGH, DOUGLAS D., DING, HANYI, ESHUN, EBENEZER E., STAMPER, ANTHONY K.
Publication of US20070190760A1 publication Critical patent/US20070190760A1/en
Application granted granted Critical
Publication of US7645675B2 publication Critical patent/US7645675B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the field of the invention is that of forming a plate capacitor having a set of horizontal conductive plates separated by a dielectric (MIM-CAP).
  • High performance (high Q-value) metal-insulator-metal capacitor is one of the essential passive devices in RF/Analog circuitry.
  • low resistance metal plates are typically used.
  • the bottom plate of a metal-insulator-metal (MIM) capacitor is typically made of back end of the line (BEOL) aluminum metal wire on the xth level of the back end (zero-cost).
  • BEOL back end of the line
  • An additional photolithography mask is used for MIM cap top plate formation. This additional top plate mask leads to extra wafer processing cost of about $25/wafer.
  • up to three masks are employed to create high-Q MIM capacitors.
  • VPP vertical parallel plate capacitors
  • BEOL Mx wire fingers and vias Due to scaling of BEOL wiring width and spacing, the capacitance density of VPP becomes appreciable for technologies with minimum features smaller than 0.25 um.
  • the performance of a VPP capacitor is limited because of the high resistance associated with metal fingers/vias, which is particularly troublesome for high frequency application.
  • the present invention utilizes BEOL wide Cu planes as MIM capacitor electrodes and the existing inter-level dielectric layers as MIM dielectric films; i.e. the thickness of the capacitor plates and of the dielectric is the same in the capacitor as in the rest of the circuit.
  • the Mx electrodes are tied together to create a parallel plate capacitor.
  • the resistance of MIM plates according to the present invention is extremely low, which leads to a high performance MIM capacitor.
  • the capacitance density for the invented MIM increases as the inter-level dielectric films become thinner for more advanced technologies. Moreover, more BEOL metal wiring levels are employed for advanced technologies, which can lead to higher capacitance density for the present invention because more metal levels can be connected together.
  • Vx vias are added through Mx perforation holes (through-vias).
  • through-vias increases capacitive coupling and reduces/eliminates additional wiring area needed for MIM cap plate connection, which again leads to cap density enhancement.
  • An Ansoft Q3D simulation indicates that capacitance density improvement of greater than 30% is possible compared with through-via practice.
  • FIG. 1 shows a cross sectional view of a MIM-Cap with solid plates in the capacitor.
  • FIG. 2 shows cross sectional view of the same set of plates having perforations.
  • FIG. 3 shows the plates of FIG. 2 with the holes offset.
  • FIG. 4 shows the plates with the plates of one polarity being connected by vertical conductors.
  • FIG. 5 shows the plates with vertical connectors connecting all the plates of each polarity.
  • FIG. 6 shows a detail of the connection between vertical connectors on adjacent levels.
  • FIG. 1 shows a set of solid plates 50 connected alternately by vertical connection bars 56 .
  • An important feature of this structure compared with prior MIM capacitors is that the thickness 12 of the dielectric between the plates is greater than before because the thickness 12 is the thickness 16 of the back end levels minus the thickness 14 of the interconnects on that back end level; e.g. if the total thickness of the level is 0.5 microns and the thickness of the interconnect on that level is 0.25 microns, then the thickness 12 of the dielectric is also 0.25 microns.
  • Dashed line 10 indicates the top surface of a layer in the back end. A level in the back end containing a capacitor plate will be referred to as a capacitor level.
  • the foregoing means that the capacitance per unit area (capacitance density) is reduced, but that is more than compensated for by the improved reliability provided by the invention.
  • Box 5 represents schematically interconnections on the levels of the BEOL and the remainder of the integrated circuit.
  • Fabrication of the invented high-Q MIM is fully compatible with Cu BEOL processing.
  • the plates are deposited in apertures in the interlevel dielectric simultaneously with the other interconnects on that level.
  • the blocks labeled 56 that connect the plates of each polarity are schematic representations. They may be vertical bars of metal, vertically aligned damascene conductors, regular interconnects, or any other structure. Preferably, they are vertically aligned dual damascene structures, so that no additional masks or processing steps are needed. No additional processing steps are added in this invented high-Q MIM.
  • An estimate of the capacitance density for six levels of thin metal wire BEOL in 65 nm technology results in cap density of 0.88 fF/ ⁇ m 2 when no perforation is assumed.
  • the capacitance density loss due to perforation is limited. Based on an Ansoft Q3D simulation using design information for a known process using 90 nm ground rules, the loss of capacitance density from perforation is only about 1 ⁇ 3 of the perforation density (for example, the capacitance reduction comparing 38% perforation to no perforation is only 11.5%).
  • FIG. 2 shows the same plates, illustratively having an area 30 micron 2 while the overlap area is 25 micron 2 , with the addition of a set of holes 51 that are aligned vertically in each plate, regardless of polarity.
  • the holes 51 are separated by solid portions 52 of the plates.
  • the overlap area of the plates of the two polarities is 25 microns 2 and the 30 holes are 0.42 microns by 0.42 microns.
  • the local hole density is 17.6%.
  • FIG. 3 shows an alternative version in which the holes on alternate plates are staggered, so that a hole 51 on a plate of one polarity is aligned vertically with a solid portion 52 of the plate immediately above and below.
  • FIG. 4 shows the same hole arrangement as FIG. 3 , but with the addition of 0.14 ⁇ 0.14 micron vertical conductive members (vias) 53 connecting vertically one polarity of plates, whether positive or negative.
  • FIG. 5 shows the addition of another set of vias 53 to the opposite polarity of plates, so that all plates are connected to plates of the same polarity.
  • FIG. 6 illustrates a detail of the vertical connectors 53 .
  • Plates 50 -A belong to one of the first and second sets of plates.
  • Plate 50 -B belongs to the other set of plates.
  • Plates 50 are formed by the same damascene technique, well known to those skilled in the art, that forms the other interconnects on this level.
  • Vertical members 53 -A are formed using the dual damascene technique simultaneously with plates 50 -A.
  • plate 50 -B is formed using the same damascene technique and simultaneously member 53 -B is formed in aperture 51 and isolated from plate 50 -B.
  • the top of member 53 -B is widened, so that alignment tolerance is provided for the connection with upper member 53 -A.
  • FIG. Structure Description ⁇ m 2 (fF) (fF/ ⁇ m 2 ) 1 1 No Perforations 30 16.9779 0.566 N/A 2 18% perf., holes aligned 30 16.2798 0.543 0.959 3 18% perf., holes 30 15.9160 0.531 0.938 staggered 4 18% perf., w/vert. vias, 30 19.3063 0.644 1.138 half plates staggered 5 18% perf., w/vert. vias, 30 22.4531 0.748 1.322 all plates connected 6 38% perf., holes aligned 30 15.0257 0.501 0.885
  • the overlap area of the plates is 25 micron 2 .
  • the perforated but unconnected version of FIG. 2 has 4.1% less capacitance density than the version of FIG. 1 .
  • the perforated and unconnected version of FIG. 3 also has less capacitance density than the embodiment of FIG. 1 .
  • the aligned version of FIG. 1 benefits from the edge capacitance of the holes.
  • Connecting the vias improves the capacitance ratio substantially, as well as taking up less area after the removal of the vertical connection bars 56 .

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A parallel plate capacitor formed in the back end of an integrated circuit employs conductive capacitor plates that are formed simultaneously with the other interconnects on that level of the back end (having the same material, thickness, etc). The capacitor plates are set into the interlevel dielectric using the same process as the other interconnects on that level of the back end (preferably dual damascene). Some versions of the capacitors have perforations in the plates and vertical conductive members connecting all plates of the same polarity, thereby increasing reliability, saving space and increasing the capacitive density compared with solid plates.

Description

    TECHNICAL FIELD
  • The field of the invention is that of forming a plate capacitor having a set of horizontal conductive plates separated by a dielectric (MIM-CAP).
    • BACKGROUND OF THE INVENTION
  • High performance (high Q-value) metal-insulator-metal capacitor (MIM cap) is one of the essential passive devices in RF/Analog circuitry. In order to achieve high-Q value, low resistance metal plates are typically used. In prior work, the bottom plate of a metal-insulator-metal (MIM) capacitor is typically made of back end of the line (BEOL) aluminum metal wire on the xth level of the back end (zero-cost). An additional photolithography mask is used for MIM cap top plate formation. This additional top plate mask leads to extra wafer processing cost of about $25/wafer. In the advanced CMOS technologies with Cu BEOL, up to three masks are employed to create high-Q MIM capacitors.
  • In an effort to reduce cost, vertical parallel plate capacitors (VPP) have been recently developed/introduced in the advanced Analog/RF CMOS technologies. VPPs capacitor plates are made of BEOL Mx wire fingers and vias. Due to scaling of BEOL wiring width and spacing, the capacitance density of VPP becomes appreciable for technologies with minimum features smaller than 0.25 um. However, the performance of a VPP capacitor is limited because of the high resistance associated with metal fingers/vias, which is particularly troublesome for high frequency application.
  • As a result, a high performance MIM capacitor is still desirable & needed for Analog/RF CMOS technologies.
    • SUMMARY OF THE INVENTION
  • The present invention utilizes BEOL wide Cu planes as MIM capacitor electrodes and the existing inter-level dielectric layers as MIM dielectric films; i.e. the thickness of the capacitor plates and of the dielectric is the same in the capacitor as in the rest of the circuit.
  • The Mx electrodes are tied together to create a parallel plate capacitor. As a result, the resistance of MIM plates according to the present invention is extremely low, which leads to a high performance MIM capacitor.
  • The capacitance density for the invented MIM increases as the inter-level dielectric films become thinner for more advanced technologies. Moreover, more BEOL metal wiring levels are employed for advanced technologies, which can lead to higher capacitance density for the present invention because more metal levels can be connected together.
  • To further enhance capacitance density of this zero-cost high-Q MIM capacitor, Vx vias are added through Mx perforation holes (through-vias). The use of through-vias increases capacitive coupling and reduces/eliminates additional wiring area needed for MIM cap plate connection, which again leads to cap density enhancement.
  • An Ansoft Q3D simulation indicates that capacitance density improvement of greater than 30% is possible compared with through-via practice.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 shows a cross sectional view of a MIM-Cap with solid plates in the capacitor.
  • FIG. 2 shows cross sectional view of the same set of plates having perforations.
  • FIG. 3 shows the plates of FIG. 2 with the holes offset.
  • FIG. 4 shows the plates with the plates of one polarity being connected by vertical conductors.
  • FIG. 5 shows the plates with vertical connectors connecting all the plates of each polarity.
  • FIG. 6 shows a detail of the connection between vertical connectors on adjacent levels.
    • DETAILED DESCRIPTION
  • FIG. 1 shows a set of solid plates 50 connected alternately by vertical connection bars 56. An important feature of this structure compared with prior MIM capacitors is that the thickness 12 of the dielectric between the plates is greater than before because the thickness 12 is the thickness 16 of the back end levels minus the thickness 14 of the interconnects on that back end level; e.g. if the total thickness of the level is 0.5 microns and the thickness of the interconnect on that level is 0.25 microns, then the thickness 12 of the dielectric is also 0.25 microns. Dashed line 10 indicates the top surface of a layer in the back end. A level in the back end containing a capacitor plate will be referred to as a capacitor level. The foregoing means that the capacitance per unit area (capacitance density) is reduced, but that is more than compensated for by the improved reliability provided by the invention. Box 5 represents schematically interconnections on the levels of the BEOL and the remainder of the integrated circuit.
  • Fabrication of the invented high-Q MIM is fully compatible with Cu BEOL processing. The plates are deposited in apertures in the interlevel dielectric simultaneously with the other interconnects on that level. The blocks labeled 56 that connect the plates of each polarity are schematic representations. They may be vertical bars of metal, vertically aligned damascene conductors, regular interconnects, or any other structure. Preferably, they are vertically aligned dual damascene structures, so that no additional masks or processing steps are needed. No additional processing steps are added in this invented high-Q MIM. An estimate of the capacitance density for six levels of thin metal wire BEOL in 65 nm technology results in cap density of 0.88 fF/μm2 when no perforation is assumed.
  • This no perforation assumption is valid for MIMs that require small plates. When MIM plates become large (approximately 20 microns on edge), perforating of copper plates is necessary in order to achieve uniform copper plate thickness. Significant copper plate thinning is expected when large non-perforated Cu plates are used due to the fast Cu polish rate associated with large plates during CMP processing.
  • However, the capacitance density loss due to perforation is limited. Based on an Ansoft Q3D simulation using design information for a known process using 90 nm ground rules, the loss of capacitance density from perforation is only about ⅓ of the perforation density (for example, the capacitance reduction comparing 38% perforation to no perforation is only 11.5%).
  • FIG. 2 shows the same plates, illustratively having an area 30 micron2 while the overlap area is 25 micron2, with the addition of a set of holes 51 that are aligned vertically in each plate, regardless of polarity. The holes 51 are separated by solid portions 52 of the plates. Illustratively, the overlap area of the plates of the two polarities is 25 microns2 and the 30 holes are 0.42 microns by 0.42 microns. The local hole density is 17.6%.
  • FIG. 3 shows an alternative version in which the holes on alternate plates are staggered, so that a hole 51 on a plate of one polarity is aligned vertically with a solid portion 52 of the plate immediately above and below.
  • FIG. 4 shows the same hole arrangement as FIG. 3, but with the addition of 0.14×0.14 micron vertical conductive members (vias) 53 connecting vertically one polarity of plates, whether positive or negative.
  • FIG. 5 shows the addition of another set of vias 53 to the opposite polarity of plates, so that all plates are connected to plates of the same polarity.
  • FIG. 6 illustrates a detail of the vertical connectors 53. Plates 50-A belong to one of the first and second sets of plates. Plate 50-B belongs to the other set of plates. Plates 50 are formed by the same damascene technique, well known to those skilled in the art, that forms the other interconnects on this level. Vertical members 53-A are formed using the dual damascene technique simultaneously with plates 50-A. At the center of the Figure, plate 50-B is formed using the same damascene technique and simultaneously member 53-B is formed in aperture 51 and isolated from plate 50-B. Optionally, the top of member 53-B is widened, so that alignment tolerance is provided for the connection with upper member 53-A. The width of the widened member will be determined by the width of aperture 51 and the ground rules for the gap between 53-B and the walls of plate 50-B.
    TABLE
    Comparison of Capacitance Density
    Total Density
    Capaci- Cap. Ratio to
    Area tance Density Structure
    FIG. Structure Description μm2 (fF) (fF/μm2) 1
    1 No Perforations 30 16.9779 0.566 N/A
    2 18% perf., holes aligned 30 16.2798 0.543 0.959
    3 18% perf., holes 30 15.9160 0.531 0.938
    staggered
    4 18% perf., w/vert. vias, 30 19.3063 0.644 1.138
    half plates staggered
    5 18% perf., w/vert. vias, 30 22.4531 0.748 1.322
    all plates connected
    6 38% perf., holes aligned 30 15.0257 0.501 0.885
  • In all cases in Table I, the overlap area of the plates is 25 micron2.
  • As can be seen in Table I, the perforated but unconnected version of FIG. 2 has 4.1% less capacitance density than the version of FIG. 1.
  • Similarly, the perforated and unconnected version of FIG. 3 also has less capacitance density than the embodiment of FIG. 1. The aligned version of FIG. 1 benefits from the edge capacitance of the holes.
  • Connecting the vias improves the capacitance ratio substantially, as well as taking up less area after the removal of the vertical connection bars 56.
  • As can be seen from example 6 from table I, more perforation in copper plates results in lower capacitance. However, the loss in capacitance is much smaller than one skilled in the art would expect. When copper plates are perforated at 38%, the capacitance loss is approximately 11.5%.
  • The Figures show an even number of plates in the capacitor. Those skilled in the art will understand that an odd number of plates may also be used, so that the top and bottom plates will have the same polarity, e.g. ground.
  • While the invention has been described in terms of a single preferred embodiment, those skilled in the art will recognize that the invention can be practiced in various versions within the spirit and scope of the following claims.

Claims (20)

1. A parallel plate capacitor for use in an integrated circuit comprising a set of capacitor plates disposed on consecutive levels in the back end of an integrated circuit, alternate ones of the capacitor plates overlapping with vertically adjacent capacitor plates and being adapted to connect to electrical sources of opposite polarity, thereby forming a first set of a first polarity and a second set of a second polarity, said capacitor plates being formed simultaneously with other interconnections in the remaining portion of the integrated circuit; whereby said capacitor plates have the same thickness as said other interconnections and are separated vertically by the same amount of interlevel dielectric, in which:
each of said capacitor plates is a solid continuous layer, wherein at least one of said capacitor plates comprises a set of perforations formed within said solid continuous layer.
2. (canceled)
3. A capacitor according to claim 1, in which said perforations in said first set and in said second set are aligned vertically.
4. A capacitor according to claim 1, in which said perforations in said first set and in said second set are displaced horizontally, such that perforations in said first set are aligned vertically and perforations in said second set are aligned vertically at a different transverse location.
5. A capacitor according to claim 4, in which at least one pair of capacitor plates in one of said first and second sets are connected by vertical conductors passing through said aligned perforations of the other of said first and second sets, whereby said one pair of capacitor plates are connected.
6. A capacitor according to claim 5, in which all of the capacitor plates in one of said first and second sets are connected by vertical conductors.
7. A capacitor according to claim 5, in which at least one pair of capacitor plates in each of said first and second sets are connected by vertical conductors passing through said aligned perforations of the other of said first and second sets.
8. A capacitor according to claim 5, in which all pairs of capacitor plates in each of said first and second sets are connected by vertical conductors passing through said aligned perforations of the other of said first and second sets.
9. A method of forming a parallel plate capacitor comprising a set of capacitor plates disposed on consecutive levels in the back end of an integrated circuit, alternate ones of the capacitor plates overlapping with vertically adjacent capacitor plates and being adapted to connect to electrical sources of opposite polarity, thereby forming a first set of plates of a first polarity and a second set of plates of a second polarity, comprising the steps of:
depositing successively a set of capacitor levels of conductive interconnects in the back end of an integrated circuit, each of said capacitor levels including at least one conductive plate having the same thickness as other interconnect members on said capacitor levels and deposited simultaneously with said other interconnections.
10. A method according to claim 9, in which said capacitor plates are solid.
11. A method according to claim 9, in which said capacitor plates are perforated with a set of perforations having together a perforation area.
12. A method according to claim 9, in which each of said capacitor plates is perforated with a set of perforations having together a perforation area and at least one plate other than a top or bottom plate has vertical connection members passing through the apertures thereof and connecting to an upper plate above said at least one and to a lower plate below said at least one plate.
13. A method according to claim 11, in which said perforations in said first set and in said second set are aligned vertically.
14. A method according to claim 11, in which said perforations in said first set and in said second set are displaced horizontally, whereby perforations in said first set are aligned vertically and perforations in said second set are aligned vertically at a different transverse location.
15. A method according to claim 12, in which at least one pair of capacitor plates of said first and second sets are connected by vertical conductors passing through said perforations of an intermediate plate of the other of said first and second sets, an upper part of said vertical connector being formed simultaneously with the upper plate of said pair of capacitor plates and a lower part of said vertical connector being formed simultaneously with said intermediate plate, whereby said pair of capacitor plates are connected.
16. A method according to claim 15, in which all of the capacitor plates in one of said first and second sets are connected by vertical conductors
17. A method according to claim 15, in which at least one pair of capacitor plates In each of said first and second sets are connected by vertical conductors passing through said aligned perforations of the other of said first and second sets.
18. A method according to claim 15, in which all pairs of capacitor plates In each of said first and second sets are connected by vertical conductors passing through said aligned perforations of the other of said first and second sets.
19. A method according to claim 15, in which all pairs of said first set are connected and all pairs of said second set are connected.
20. A capacitor according to claim 1, wherein said set of perforations is formed in a portion of said solid continuous layer which substantially overlaps at least one of a vertically adjacent capacitor plate.
US11/275,544 2006-01-13 2006-01-13 Integrated parallel plate capacitors Active US7645675B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/275,544 US7645675B2 (en) 2006-01-13 2006-01-13 Integrated parallel plate capacitors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/275,544 US7645675B2 (en) 2006-01-13 2006-01-13 Integrated parallel plate capacitors

Publications (2)

Publication Number Publication Date
US20070190760A1 true US20070190760A1 (en) 2007-08-16
US7645675B2 US7645675B2 (en) 2010-01-12

Family

ID=38369159

Family Applications (1)

Application Number Title Priority Date Filing Date
US11/275,544 Active US7645675B2 (en) 2006-01-13 2006-01-13 Integrated parallel plate capacitors

Country Status (1)

Country Link
US (1) US7645675B2 (en)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010042483A1 (en) * 2008-10-08 2010-04-15 Delphi Technologies, Inc. Integrated radar-camera sensor
US20100127351A1 (en) * 2008-11-21 2010-05-27 Xilinx, Inc. Integrated capacitor with interlinked lateral fins
WO2010059336A1 (en) * 2008-11-21 2010-05-27 Xilinx, Inc. Integrated capacitor with grid plates
US20100127347A1 (en) * 2008-11-21 2010-05-27 Xilinx, Inc. Shielding for integrated capacitors
US20100127309A1 (en) * 2008-11-21 2010-05-27 Xilinx, Inc. Integrated capacitor with alternating layered segments
US7994610B1 (en) 2008-11-21 2011-08-09 Xilinx, Inc. Integrated capacitor with tartan cross section
US8207592B2 (en) 2008-11-21 2012-06-26 Xilinx, Inc. Integrated capacitor with array of crosses
US8653844B2 (en) 2011-03-07 2014-02-18 Xilinx, Inc. Calibrating device performance within an integrated circuit
US8941974B2 (en) 2011-09-09 2015-01-27 Xilinx, Inc. Interdigitated capacitor having digits of varying width
US9063230B2 (en) 2008-10-08 2015-06-23 Delphi Technologies, Inc. Radar sensor module
US9270247B2 (en) 2013-11-27 2016-02-23 Xilinx, Inc. High quality factor inductive and capacitive circuit structure
US9293812B2 (en) 2013-11-06 2016-03-22 Delphi Technologies, Inc. Radar antenna assembly
US9524964B2 (en) 2014-08-14 2016-12-20 Xilinx, Inc. Capacitor structure in an integrated circuit
US10218054B2 (en) 2015-08-04 2019-02-26 Samsung Electronics Co., Ltd. Antenna for device

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008235498A (en) * 2007-03-20 2008-10-02 Renesas Technology Corp Semiconductor device
US20090296310A1 (en) * 2008-06-03 2009-12-03 Azuma Chikara Chip capacitor precursors, packaged semiconductors, and assembly method for converting the precursors to capacitors
KR101337075B1 (en) * 2008-11-21 2013-12-05 자일링크스 인코포레이티드 Shielding for integrated capacitors
US8242579B2 (en) * 2009-05-25 2012-08-14 Infineon Technologies Ag Capacitor structure
US8482048B2 (en) * 2009-07-31 2013-07-09 Alpha & Omega Semiconductor, Inc. Metal oxide semiconductor field effect transistor integrating a capacitor
US8901710B2 (en) * 2013-02-27 2014-12-02 International Business Machines Corporation Interdigitated capacitors with a zero quadratic voltage coefficient of capacitance or zero linear temperature coefficient of capacitance
US9331013B2 (en) 2013-03-14 2016-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated capacitor

Citations (75)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4409608A (en) * 1981-04-28 1983-10-11 The United States Of America As Represented By The Secretary Of The Navy Recessed interdigitated integrated capacitor
US4430690A (en) * 1982-10-07 1984-02-07 International Business Machines Corporation Low inductance MLC capacitor with metal impregnation and solder bar contact
US4825280A (en) * 1986-10-01 1989-04-25 Texas Instruments Incorporated Electrostatic discharge protection for semiconductor devices
US5351163A (en) * 1992-12-30 1994-09-27 Westinghouse Electric Corporation High Q monolithic MIM capacitor
US5446337A (en) * 1993-07-28 1995-08-29 Matsushita Electric Industrial Co., Ltd. Image display apparatus and method of making the same
US5477407A (en) * 1993-12-17 1995-12-19 Fujitsu Limited Protection circuit for protecting a semiconductor device from a voltage surge
US5583359A (en) * 1995-03-03 1996-12-10 Northern Telecom Limited Capacitor structure for an integrated circuit
US5789791A (en) * 1996-08-27 1998-08-04 National Semiconductor Corporation Multi-finger MOS transistor with reduced gate resistance
US5834332A (en) * 1995-03-17 1998-11-10 Siemens Aktiengesellschaft Micromechanical semiconductor components and manufacturing method therefor
US5841579A (en) * 1995-06-07 1998-11-24 Silicon Light Machines Flat diffraction grating light valve
US5872695A (en) * 1997-02-26 1999-02-16 International Business Machines Corporation Integrated electronic components having conductive filled through holes
US5933725A (en) * 1998-05-27 1999-08-03 Vanguard International Semiconductor Corporation Word line resistance reduction method and design for high density memory with relaxed metal pitch
US5939766A (en) * 1996-07-24 1999-08-17 Advanced Micro Devices, Inc. High quality capacitor for sub-micrometer integrated circuits
US5982018A (en) * 1997-05-23 1999-11-09 Micron Technology, Inc. Thin film capacitor coupons for memory modules and multi-chip modules
US6066537A (en) * 1998-02-02 2000-05-23 Tritech Microelectronics, Ltd. Method for fabricating a shielded multilevel integrated circuit capacitor
US6088215A (en) * 1997-11-03 2000-07-11 Motorola, Inc. Capacitor and method of manufacture
US6094335A (en) * 1998-10-09 2000-07-25 Advanced Micro Devices, Inc. Vertical parallel plate capacitor
US6100591A (en) * 1998-05-25 2000-08-08 Nec Corporation Semiconductor device and method of fabricating the same
US6297524B1 (en) * 2000-04-04 2001-10-02 Philips Electronics North America Corporation Multilayer capacitor structure having an array of concentric ring-shaped plates for deep sub-micron CMOS
US20020022331A1 (en) * 2000-08-18 2002-02-21 Mukul Saran High capacitance damascene capacitors
US6385033B1 (en) * 2000-09-29 2002-05-07 Intel Corporation Fingered capacitor in an integrated circuit
US20020063272A1 (en) * 2000-11-28 2002-05-30 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having a test element, and method of manufacturing the same
US6410954B1 (en) * 2000-04-10 2002-06-25 Koninklijke Philips Electronics N.V. Multilayered capacitor structure with alternately connected concentric lines for deep sub-micron CMOS
US6430028B1 (en) * 2000-11-22 2002-08-06 Newport Fab, Llc Method for fabrication of an MIM capacitor and related structure
US6445056B2 (en) * 2000-01-05 2002-09-03 Nec Corporation Semiconductor capacitor device
US6451664B1 (en) * 2001-01-30 2002-09-17 Infineon Technologies Ag Method of making a MIM capacitor with self-passivating plates
US6459561B1 (en) * 2001-06-12 2002-10-01 Avx Corporation Low inductance grid array capacitor
US6465832B1 (en) * 1999-10-27 2002-10-15 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6542352B1 (en) * 1997-12-09 2003-04-01 Daniel Devoe Ceramic chip capacitor of conventional volume and external form having increased capacitance from use of closely spaced interior conductive planes reliably connecting to positionally tolerant exterior pads through multiple redundant vias
US6563191B1 (en) * 2000-10-16 2003-05-13 Agilent Technologies, Inc. Interdigitated capacitor with dielectric overlay
US20040004241A1 (en) * 2000-08-31 2004-01-08 Texas Instruments Incorporated On-chip capacitor
US6690570B2 (en) * 2000-09-14 2004-02-10 California Institute Of Technology Highly efficient capacitor structures with enhanced matching properties
US20040031982A1 (en) * 2002-08-12 2004-02-19 Devries Christopher Andrew Interdigitated integrated circuit capacitor
US20040061177A1 (en) * 2002-09-30 2004-04-01 Merchant Sailesh M. Capacitor structure and fabrication method therefor in a dual damascene process
US20040061112A1 (en) * 2002-09-30 2004-04-01 Andreas Felber Test structure for determining a short circuit between trench capacitors in a memory cell array
US6743671B2 (en) * 2002-08-09 2004-06-01 Ali Corporation Metal-on-metal capacitor with conductive plate for preventing parasitic capacitance and method of making the same
US20040145056A1 (en) * 2003-01-23 2004-07-29 Gabriel Kaigham J. Multi-metal layer MEMS structure and process for making the same
US6791175B2 (en) * 2001-09-29 2004-09-14 Kabushiki Kaisha Toshiba Stacked type semiconductor device
US20040222494A1 (en) * 2003-02-06 2004-11-11 Laws Peter Graham Electrical component structure
US6819542B2 (en) * 2003-03-04 2004-11-16 Taiwan Semiconductor Manufacturing Co., Ltd. Interdigitated capacitor structure for an integrated circuit
US6822312B2 (en) * 2000-04-07 2004-11-23 Koninklijke Philips Electronics N.V. Interdigitated multilayer capacitor structure for deep sub-micron CMOS
US6906905B1 (en) * 2004-06-30 2005-06-14 International Business Machines Corporation Micro electro-mechanical variable capacitor
US6909591B2 (en) * 2003-10-22 2005-06-21 Lsi Logic Corporation Complimentary metal oxide semiconductor capacitor and method for making same
US6917509B1 (en) * 2002-11-21 2005-07-12 Daniel F. Devoe Single layer capacitor with dissimilar metallizations
US20050162236A1 (en) * 2001-09-21 2005-07-28 Casper Michael D. Lange coupler system and method
US6942901B1 (en) * 1999-01-07 2005-09-13 The Penn State Research Foundation Fabrication of particulate tapes by electrophoretic deposition
US20050207093A1 (en) * 2004-03-19 2005-09-22 Tdk Corporation Multilayer capacitor
US20050219927A1 (en) * 2001-04-19 2005-10-06 Micron Technology, Inc. Method for stabilizing or offsetting voltage in an integrated circuit
US6964908B2 (en) * 2003-08-19 2005-11-15 International Business Machines Corporation Metal-insulator-metal capacitor and method of fabricating same
US20050266652A1 (en) * 2004-05-27 2005-12-01 International Business Machines Corporation High density mimcap with a unit repeatable structure
US20060003482A1 (en) * 2004-06-30 2006-01-05 International Business Machines Corporation Elastomeric cmos based micro electromechanical varactor
US20060061935A1 (en) * 2004-09-20 2006-03-23 Richard Schultz Fully shielded capacitor cell structure
US20060086965A1 (en) * 2004-10-26 2006-04-27 Nec Electronics Corporation Semiconductor device
US20060132148A1 (en) * 2004-10-11 2006-06-22 Cheah Chin B Via etch monitoring
US7071565B2 (en) * 2000-12-22 2006-07-04 Sandisk 3D Llc Patterning three dimensional structures
US20060157770A1 (en) * 2004-12-23 2006-07-20 Dongbuanam Semiconductor Inc. Metal-to-metal capacitor
US20060180895A1 (en) * 2005-02-11 2006-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitor device with vertically arranged capacitor regions of various kinds
US20060205106A1 (en) * 2005-02-25 2006-09-14 Hiroshi Fukuda Integrated micro electro-mechanical system and manufacturing method thereof
US20060203424A1 (en) * 2005-03-14 2006-09-14 Broadcom Corporation High density maze capacitor
US7116544B1 (en) * 2004-06-16 2006-10-03 Marvell International, Ltd. Capacitor structure in a semiconductor device
US7133294B2 (en) * 2001-12-03 2006-11-07 Intel Corporation Integrated circuit packages with sandwiched capacitors
US20060256502A1 (en) * 2001-12-03 2006-11-16 Intel Corporation Capacitor having separate terminals on three or more sides and methods of fabrication
US20060283007A1 (en) * 2005-06-21 2006-12-21 Cardiomems, Inc. Method of manufacturing implantable wireless sensor for in vivo pressure measurement
US7160761B2 (en) * 1998-11-16 2007-01-09 Sandisk 3D Llc Vertically stacked field programmable nonvolatile memory and method of fabrication
US7161228B1 (en) * 2005-12-28 2007-01-09 Analog Devices, Inc. Three-dimensional integrated capacitance structure
US20070042542A1 (en) * 2004-08-17 2007-02-22 Hans-Joachim Barth Method for fabricating an interconnect arrangement with increased capacitive coupling and associated interconnect arrangement
US7202548B2 (en) * 2005-09-13 2007-04-10 Via Technologies, Inc. Embedded capacitor with interdigitated structure
US20070090986A1 (en) * 2005-10-21 2007-04-26 Shigeyuki Komatsu Analog-digital converter
US20070123015A1 (en) * 2005-11-30 2007-05-31 International Business Machines Corporation Passive components in the back end of integrated circuits
US20070181924A1 (en) * 2005-10-04 2007-08-09 Infineon Technologies Ag Integrated capacitor structure
US7259956B2 (en) * 2003-12-19 2007-08-21 Broadcom Corporation Scalable integrated circuit high density capacitors
US20070210442A1 (en) * 2005-01-11 2007-09-13 Freescale Semiconductor, Inc. Method and apparatus for providing structural support for interconnect pad while allowing signal conductance
US7274085B1 (en) * 2006-03-09 2007-09-25 United Microelectronics Corp. Capacitor structure
US20070279835A1 (en) * 2006-06-06 2007-12-06 International Business Machines Corporation High capacitance density vertical natural capacitors
US20080142861A1 (en) * 2006-06-02 2008-06-19 Collins David S Symmetric capacitor structure

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6709918B1 (en) 2002-12-02 2004-03-23 Chartered Semiconductor Manufacturing Ltd. Method for making a metal-insulator-metal (MIM) capacitor and metal resistor for a copper back-end-of-line (BEOL) technology

Patent Citations (82)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4409608A (en) * 1981-04-28 1983-10-11 The United States Of America As Represented By The Secretary Of The Navy Recessed interdigitated integrated capacitor
US4430690A (en) * 1982-10-07 1984-02-07 International Business Machines Corporation Low inductance MLC capacitor with metal impregnation and solder bar contact
US4825280A (en) * 1986-10-01 1989-04-25 Texas Instruments Incorporated Electrostatic discharge protection for semiconductor devices
US5351163A (en) * 1992-12-30 1994-09-27 Westinghouse Electric Corporation High Q monolithic MIM capacitor
US5446337A (en) * 1993-07-28 1995-08-29 Matsushita Electric Industrial Co., Ltd. Image display apparatus and method of making the same
US5477407A (en) * 1993-12-17 1995-12-19 Fujitsu Limited Protection circuit for protecting a semiconductor device from a voltage surge
US5583359A (en) * 1995-03-03 1996-12-10 Northern Telecom Limited Capacitor structure for an integrated circuit
US5834332A (en) * 1995-03-17 1998-11-10 Siemens Aktiengesellschaft Micromechanical semiconductor components and manufacturing method therefor
US5841579A (en) * 1995-06-07 1998-11-24 Silicon Light Machines Flat diffraction grating light valve
US5939766A (en) * 1996-07-24 1999-08-17 Advanced Micro Devices, Inc. High quality capacitor for sub-micrometer integrated circuits
US5789791A (en) * 1996-08-27 1998-08-04 National Semiconductor Corporation Multi-finger MOS transistor with reduced gate resistance
US5872695A (en) * 1997-02-26 1999-02-16 International Business Machines Corporation Integrated electronic components having conductive filled through holes
US5982018A (en) * 1997-05-23 1999-11-09 Micron Technology, Inc. Thin film capacitor coupons for memory modules and multi-chip modules
US6088215A (en) * 1997-11-03 2000-07-11 Motorola, Inc. Capacitor and method of manufacture
US6753218B2 (en) * 1997-12-09 2004-06-22 Daniel Devoe Ceramic chip capacitor of conventional volume and external form having increased capacitance from use of closely spaced interior conductive planes reliably connecting to positionally tolerant exterior pads through multiple redundant vias
US6542352B1 (en) * 1997-12-09 2003-04-01 Daniel Devoe Ceramic chip capacitor of conventional volume and external form having increased capacitance from use of closely spaced interior conductive planes reliably connecting to positionally tolerant exterior pads through multiple redundant vias
US20030161090A1 (en) * 1997-12-09 2003-08-28 Daniel Devoe Ceramic chip capacitor of conventional volume and external form having increased capacitance from use of closely spaced interior conductive planes reliably connecting to positionally tolerant exterior pads through multiple redundant vias
US6066537A (en) * 1998-02-02 2000-05-23 Tritech Microelectronics, Ltd. Method for fabricating a shielded multilevel integrated circuit capacitor
US6100591A (en) * 1998-05-25 2000-08-08 Nec Corporation Semiconductor device and method of fabricating the same
US5933725A (en) * 1998-05-27 1999-08-03 Vanguard International Semiconductor Corporation Word line resistance reduction method and design for high density memory with relaxed metal pitch
US6094335A (en) * 1998-10-09 2000-07-25 Advanced Micro Devices, Inc. Vertical parallel plate capacitor
US7160761B2 (en) * 1998-11-16 2007-01-09 Sandisk 3D Llc Vertically stacked field programmable nonvolatile memory and method of fabrication
US6942901B1 (en) * 1999-01-07 2005-09-13 The Penn State Research Foundation Fabrication of particulate tapes by electrophoretic deposition
US6465832B1 (en) * 1999-10-27 2002-10-15 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6445056B2 (en) * 2000-01-05 2002-09-03 Nec Corporation Semiconductor capacitor device
US6297524B1 (en) * 2000-04-04 2001-10-02 Philips Electronics North America Corporation Multilayer capacitor structure having an array of concentric ring-shaped plates for deep sub-micron CMOS
US6822312B2 (en) * 2000-04-07 2004-11-23 Koninklijke Philips Electronics N.V. Interdigitated multilayer capacitor structure for deep sub-micron CMOS
US6410954B1 (en) * 2000-04-10 2002-06-25 Koninklijke Philips Electronics N.V. Multilayered capacitor structure with alternately connected concentric lines for deep sub-micron CMOS
US20020022331A1 (en) * 2000-08-18 2002-02-21 Mukul Saran High capacitance damascene capacitors
US20040004241A1 (en) * 2000-08-31 2004-01-08 Texas Instruments Incorporated On-chip capacitor
US6690570B2 (en) * 2000-09-14 2004-02-10 California Institute Of Technology Highly efficient capacitor structures with enhanced matching properties
US6385033B1 (en) * 2000-09-29 2002-05-07 Intel Corporation Fingered capacitor in an integrated circuit
US6563191B1 (en) * 2000-10-16 2003-05-13 Agilent Technologies, Inc. Interdigitated capacitor with dielectric overlay
US6430028B1 (en) * 2000-11-22 2002-08-06 Newport Fab, Llc Method for fabrication of an MIM capacitor and related structure
US20020063272A1 (en) * 2000-11-28 2002-05-30 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having a test element, and method of manufacturing the same
US7071565B2 (en) * 2000-12-22 2006-07-04 Sandisk 3D Llc Patterning three dimensional structures
US6451664B1 (en) * 2001-01-30 2002-09-17 Infineon Technologies Ag Method of making a MIM capacitor with self-passivating plates
US20050219927A1 (en) * 2001-04-19 2005-10-06 Micron Technology, Inc. Method for stabilizing or offsetting voltage in an integrated circuit
US6459561B1 (en) * 2001-06-12 2002-10-01 Avx Corporation Low inductance grid array capacitor
US20050162236A1 (en) * 2001-09-21 2005-07-28 Casper Michael D. Lange coupler system and method
US6791175B2 (en) * 2001-09-29 2004-09-14 Kabushiki Kaisha Toshiba Stacked type semiconductor device
US20060256502A1 (en) * 2001-12-03 2006-11-16 Intel Corporation Capacitor having separate terminals on three or more sides and methods of fabrication
US7133294B2 (en) * 2001-12-03 2006-11-07 Intel Corporation Integrated circuit packages with sandwiched capacitors
US6743671B2 (en) * 2002-08-09 2004-06-01 Ali Corporation Metal-on-metal capacitor with conductive plate for preventing parasitic capacitance and method of making the same
US20040031982A1 (en) * 2002-08-12 2004-02-19 Devries Christopher Andrew Interdigitated integrated circuit capacitor
US6897077B2 (en) * 2002-09-30 2005-05-24 Infineon Technologies Ag Test structure for determining a short circuit between trench capacitors in a memory cell array
US20040061112A1 (en) * 2002-09-30 2004-04-01 Andreas Felber Test structure for determining a short circuit between trench capacitors in a memory cell array
US20040061177A1 (en) * 2002-09-30 2004-04-01 Merchant Sailesh M. Capacitor structure and fabrication method therefor in a dual damascene process
US6917509B1 (en) * 2002-11-21 2005-07-12 Daniel F. Devoe Single layer capacitor with dissimilar metallizations
US20040145056A1 (en) * 2003-01-23 2004-07-29 Gabriel Kaigham J. Multi-metal layer MEMS structure and process for making the same
US20040222494A1 (en) * 2003-02-06 2004-11-11 Laws Peter Graham Electrical component structure
US7038296B2 (en) * 2003-02-06 2006-05-02 Zarlink Semiconductor Limited Electrical component structure
US6819542B2 (en) * 2003-03-04 2004-11-16 Taiwan Semiconductor Manufacturing Co., Ltd. Interdigitated capacitor structure for an integrated circuit
US6964908B2 (en) * 2003-08-19 2005-11-15 International Business Machines Corporation Metal-insulator-metal capacitor and method of fabricating same
US6909591B2 (en) * 2003-10-22 2005-06-21 Lsi Logic Corporation Complimentary metal oxide semiconductor capacitor and method for making same
US7259956B2 (en) * 2003-12-19 2007-08-21 Broadcom Corporation Scalable integrated circuit high density capacitors
US20050207093A1 (en) * 2004-03-19 2005-09-22 Tdk Corporation Multilayer capacitor
US20050266652A1 (en) * 2004-05-27 2005-12-01 International Business Machines Corporation High density mimcap with a unit repeatable structure
US7116544B1 (en) * 2004-06-16 2006-10-03 Marvell International, Ltd. Capacitor structure in a semiconductor device
US6906905B1 (en) * 2004-06-30 2005-06-14 International Business Machines Corporation Micro electro-mechanical variable capacitor
US20060003482A1 (en) * 2004-06-30 2006-01-05 International Business Machines Corporation Elastomeric cmos based micro electromechanical varactor
US20070042542A1 (en) * 2004-08-17 2007-02-22 Hans-Joachim Barth Method for fabricating an interconnect arrangement with increased capacitive coupling and associated interconnect arrangement
US7154734B2 (en) * 2004-09-20 2006-12-26 Lsi Logic Corporation Fully shielded capacitor cell structure
US20060061935A1 (en) * 2004-09-20 2006-03-23 Richard Schultz Fully shielded capacitor cell structure
US7262608B2 (en) * 2004-10-11 2007-08-28 Silterra Malaysia Sdn. Bhd. Via etch monitoring
US20060132148A1 (en) * 2004-10-11 2006-06-22 Cheah Chin B Via etch monitoring
US20060086965A1 (en) * 2004-10-26 2006-04-27 Nec Electronics Corporation Semiconductor device
US20060157770A1 (en) * 2004-12-23 2006-07-20 Dongbuanam Semiconductor Inc. Metal-to-metal capacitor
US20070210442A1 (en) * 2005-01-11 2007-09-13 Freescale Semiconductor, Inc. Method and apparatus for providing structural support for interconnect pad while allowing signal conductance
US20060180895A1 (en) * 2005-02-11 2006-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitor device with vertically arranged capacitor regions of various kinds
US20060205106A1 (en) * 2005-02-25 2006-09-14 Hiroshi Fukuda Integrated micro electro-mechanical system and manufacturing method thereof
US7402449B2 (en) * 2005-02-25 2008-07-22 Hitachi, Ltd. Integrated micro electro-mechanical system and manufacturing method thereof
US20060203424A1 (en) * 2005-03-14 2006-09-14 Broadcom Corporation High density maze capacitor
US20060283007A1 (en) * 2005-06-21 2006-12-21 Cardiomems, Inc. Method of manufacturing implantable wireless sensor for in vivo pressure measurement
US7202548B2 (en) * 2005-09-13 2007-04-10 Via Technologies, Inc. Embedded capacitor with interdigitated structure
US20070181924A1 (en) * 2005-10-04 2007-08-09 Infineon Technologies Ag Integrated capacitor structure
US20070090986A1 (en) * 2005-10-21 2007-04-26 Shigeyuki Komatsu Analog-digital converter
US20070123015A1 (en) * 2005-11-30 2007-05-31 International Business Machines Corporation Passive components in the back end of integrated circuits
US7161228B1 (en) * 2005-12-28 2007-01-09 Analog Devices, Inc. Three-dimensional integrated capacitance structure
US7274085B1 (en) * 2006-03-09 2007-09-25 United Microelectronics Corp. Capacitor structure
US20080142861A1 (en) * 2006-06-02 2008-06-19 Collins David S Symmetric capacitor structure
US20070279835A1 (en) * 2006-06-06 2007-12-06 International Business Machines Corporation High capacitance density vertical natural capacitors

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110163904A1 (en) * 2008-10-08 2011-07-07 Delphi Technologies, Inc. Integrated radar-camera sensor
US9063230B2 (en) 2008-10-08 2015-06-23 Delphi Technologies, Inc. Radar sensor module
US8604968B2 (en) 2008-10-08 2013-12-10 Delphi Technologies, Inc. Integrated radar-camera sensor
WO2010042483A1 (en) * 2008-10-08 2010-04-15 Delphi Technologies, Inc. Integrated radar-camera sensor
US7994610B1 (en) 2008-11-21 2011-08-09 Xilinx, Inc. Integrated capacitor with tartan cross section
KR101252989B1 (en) * 2008-11-21 2013-04-15 자일링크스 인코포레이티드 Integrated capacitor with grid plates
US7944732B2 (en) 2008-11-21 2011-05-17 Xilinx, Inc. Integrated capacitor with alternating layered segments
US7956438B2 (en) 2008-11-21 2011-06-07 Xilinx, Inc. Integrated capacitor with interlinked lateral fins
US20100127309A1 (en) * 2008-11-21 2010-05-27 Xilinx, Inc. Integrated capacitor with alternating layered segments
US7994609B2 (en) 2008-11-21 2011-08-09 Xilinx, Inc. Shielding for integrated capacitors
US20100127347A1 (en) * 2008-11-21 2010-05-27 Xilinx, Inc. Shielding for integrated capacitors
US8207592B2 (en) 2008-11-21 2012-06-26 Xilinx, Inc. Integrated capacitor with array of crosses
US8362589B2 (en) 2008-11-21 2013-01-29 Xilinx, Inc. Integrated capacitor with cabled plates
US20100127348A1 (en) * 2008-11-21 2010-05-27 Xilinx, Inc. Integrated capicitor with cabled plates
WO2010059336A1 (en) * 2008-11-21 2010-05-27 Xilinx, Inc. Integrated capacitor with grid plates
US20100127351A1 (en) * 2008-11-21 2010-05-27 Xilinx, Inc. Integrated capacitor with interlinked lateral fins
US8653844B2 (en) 2011-03-07 2014-02-18 Xilinx, Inc. Calibrating device performance within an integrated circuit
US8941974B2 (en) 2011-09-09 2015-01-27 Xilinx, Inc. Interdigitated capacitor having digits of varying width
US9293812B2 (en) 2013-11-06 2016-03-22 Delphi Technologies, Inc. Radar antenna assembly
US9270247B2 (en) 2013-11-27 2016-02-23 Xilinx, Inc. High quality factor inductive and capacitive circuit structure
US9524964B2 (en) 2014-08-14 2016-12-20 Xilinx, Inc. Capacitor structure in an integrated circuit
US10218054B2 (en) 2015-08-04 2019-02-26 Samsung Electronics Co., Ltd. Antenna for device

Also Published As

Publication number Publication date
US7645675B2 (en) 2010-01-12

Similar Documents

Publication Publication Date Title
US7645675B2 (en) Integrated parallel plate capacitors
EP1806783B1 (en) Improved interdigitated capacitive structure for an integrated circuit
US7259956B2 (en) Scalable integrated circuit high density capacitors
US5978206A (en) Stacked-fringe integrated circuit capacitors
US20140159200A1 (en) High-density stacked planar metal-insulator-metal capacitor structure and method for manufacturing same
US9524963B2 (en) Semiconductor device
JP2016527700A (en) Metal insulator metal capacitor structure
JP2009194397A (en) Multilayer capacitor, wiring board incorporating multilayer capacitor, decoupling circuit and high frequency circuit
JP3522144B2 (en) Capacitance circuit and semiconductor integrated circuit device
CN111029327B (en) Semiconductor structure and manufacturing method
EP2680308B1 (en) Metal-oxide-metal capacitor
CA2395900A1 (en) Matched vertical capacitors
US9177908B2 (en) Stacked semiconductor capacitor structure
US20100177457A1 (en) Interdigital capacitor with Self-Canceling Inductance
US6934143B2 (en) Metal-insulator-metal capacitor structure
US7109088B2 (en) Multilayer analog interconnecting line layout for a mixed-signal integrated circuit
US20030234415A1 (en) Scalable three-dimensional fringe capacitor with stacked via
US9147654B2 (en) Integrated circuit system employing alternating conductive layers
KR100902503B1 (en) High capacitance capacitor having multi vertical structure
US7327011B2 (en) Multi-surfaced plate-to-plate capacitor and method of forming same
US20070267720A1 (en) Semiconductor device including capacitor connected between two conductive strip groups
KR100641536B1 (en) method of fabricating the MIM capacitor having high capacitance
WO2020056705A1 (en) Integrated circuit
US7342766B2 (en) On-chip capacitor
JP2003124329A (en) Capacitive element

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:COOLBAUGH, DOUGLAS D.;DING, HANYI;ESHUN, EBENEZER E.;AND OTHERS;REEL/FRAME:017013/0502;SIGNING DATES FROM 20051208 TO 20051222

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 12