US20060180907A1 - Packaged microelectronic devices with pressure release elements and methods for manufacturing and using such packaged microelectonic devices - Google Patents

Packaged microelectronic devices with pressure release elements and methods for manufacturing and using such packaged microelectonic devices Download PDF

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US20060180907A1
US20060180907A1 US11/401,514 US40151406A US2006180907A1 US 20060180907 A1 US20060180907 A1 US 20060180907A1 US 40151406 A US40151406 A US 40151406A US 2006180907 A1 US2006180907 A1 US 2006180907A1
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Prior art keywords
substrate
die
pressure relief
cover
relief element
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US11/401,514
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Stephen James
Chad Cobbley
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Micron Technology Inc
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Micron Technology Inc
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Priority to US11/401,514 priority Critical patent/US20060180907A1/en
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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/564—Details not otherwise provided for, e.g. protection against moisture
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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Definitions

  • the present invention relates to packaging microelectronic devices having a microelectronic die including an integrated circuit. More particularly, several aspects of the invention are related to releasing pressure within packaged microelectronic devices during high temperature processes, such as reflow processing and burn-in testing.
  • Microelectronic devices such as memory devices and microprocessors, typically include a microelectronic die encased in a protective covering.
  • the die can include memory cells, processor circuits, interconnecting circuitry and/or other functional features.
  • the die also typically includes an array of very small bond-pads electrically coupled to the functional features. When the die is packaged, the bond-pads are coupled to leads, solder ball-pads or other types of terminals for operatively coupling the microelectronic dies to buses, circuits and/or other microelectronic devices.
  • the dies can be incorporated into individual packages, mounted with other components in hybrid or multiple chip modules, or connected directly to a printed circuit board or other types of substrates.
  • the bond-pads on the die are typically coupled to a lead frame, and the die is covered or otherwise sealed from the environment.
  • the bond-pads on the die are typically coupled to corresponding contact elements on the substrate using wire-bond lines, ball grid arrays and other techniques.
  • the dies that are mounted directly to the substrates are generally Chip Scale Package devices (CSP) or Flip Chip Bare Die devices (Flip-Chip).
  • CSP and Flip-Chip devices generally have one or more protective casings that encapsulate the dies and any exposed contact elements, bond-pads or wire-bond lines.
  • the protective casings should shield the die and the other components on the substrate from environmental factors (e.g., moisture), electrical interference, and mechanical shocks.
  • the protective casings are accordingly robust elements that protect the sensitive components of a microelectronic device.
  • the protective casings are generally composed of plastics, ceramics, or thermosetting materials.
  • thermosetting material flows over the die on one side of the substrate until it fills the cavity, and then the thermosetting material is cured so that it hardens into a suitable protective casing for protecting the die.
  • the protective casing should not have any voids over the die because contaminants from the molding process or environmental factors outside of the mold could damage the die.
  • the thermosetting material moreover, should not cover a ball-pad array on the substrate or damage any electrical connections between the die and the substrate.
  • thermosetting material should be molded in a manner that avoids (a) producing voids in the protective casing, (b) covering certain portions of the substrate with the thermosetting material, and (c) displacing or otherwise damaging any wire-bond lines or solder joints between the die and the substrate.
  • One drawback of packaging microelectronic devices is that during high-temperature processing cracks or voids can form in the protective casing, or the protective casing can delaminate from the substrate. Such cracking or delamination, for example, may occur during a solder reflow procedure in which the packaged microelectronic devices are quickly heated to reflow solder balls and/or or solder paste pads. This problem is particularly noticeable in procedures that quickly heat the packaged devices to an elevated temperature. When the casing of a packaged microelectronic device cracks or delaminates from the substrate, the device is often rejected because such cracks or voids can expose very delicate components (e.g., bond-pads or wire-bond lines) to external environmental factors.
  • very delicate components e.g., bond-pads or wire-bond lines
  • a packaged microelectronic device includes a microelectronic die, an interconnecting unit coupled to the die, and a protective casing over the die.
  • the microelectronic die may have an integrated circuit and a bond-pad array having a plurality of bond-pads operatively coupled to the integrated circuit.
  • the interconnecting unit has a substrate with a first side and a second side to which the die is attached, a plurality of contact elements operatively coupled to corresponding bond-pads on the die, and a plurality of ball-pads on the first side of the substrate.
  • the interconnecting unit can also include a plurality of conductive elements extending from selected contact elements to corresponding ball-pads to electrically couple the contact elements to the ball-pads.
  • the protective casing can have at least a first cover encapsulating the die on the first side of the substrate.
  • the packaged microelectronic device can also include a pressure relief element through at least a portion of the first cover and/or the substrate.
  • the pressure relief element can have an opening to an external environment and a passageway to an internal location or interior point within the packaged microelectronic device.
  • the pressure relief element for example, can be a hole or opening through the substrate to an adhesive strip on the bottom side of the die.
  • the pressure relief element is a hole through the first cover to either the substrate or the microelectronic die.
  • the pressure relief element is a depression that extends only part way through the cover or the substrate such that the passageway forms a thin section of the first cover or the substrate. In operation, the pressure relief element releases gases or other forms of moisture entrapped by the casing and/or the substrate during high temperature processing of the packaged microelectronic device.
  • FIG. 1 is a top cut-away isometric view illustrating a portion of a microelectronic device in accordance with an embodiment of the invention.
  • FIG. 2A is a top isometric view of the microelectronic device of FIG. 1 .
  • FIG. 2B is a front cross-sectional view of the microelectronic device of FIG. 2A .
  • FIG. 3 is a front cross-sectional view of a microelectronic device in accordance with another embodiment of the invention.
  • FIG. 4A is a bottom isometric view and FIG. 4B is a front cross-sectional view of a microelectronic device in accordance with another embodiment of the invention.
  • FIGS. 5A and 5B are front cross-sectional views of a microelectronic device in accordance with another embodiment of the invention.
  • FIGS. 6A and 6B are front cross-sectional views of a microelectronic device in accordance with still another embodiment of the invention.
  • FIG. 7 is a side cross-sectional view of a microelectronic device and a mold assembly used to form a protective casing with pressure relief elements in accordance with an embodiment of the invention.
  • the following disclosure is directed toward packaged microelectronic devices, interconnecting units for packaged microelectronic devices, and methods for manufacturing and using packaged microelectronic devices.
  • Several embodiments of the invention are described with reference to memory devices, but the methods and apparatuses are also applicable to microprocessors and other types of devices.
  • One skilled in the art will accordingly understand that the present invention may have additional embodiments, or that the invention may be practiced without several of the details described below.
  • FIG. 1 is a top cut-away isometric view of a microelectronic device 10 in accordance with one embodiment of the invention.
  • the microelectronic device 10 can include a substrate 20 and a microelectronic die 40 attached to the substrate 20 by an adhesive strip 60 .
  • the following description is directed toward encapsulating a microelectronic die on a flexible substrate, but it is expected that several embodiments of the methods and apparatuses in accordance with the present invention may be practiced to encapsulate a large variety of electrical and/or non-electrical articles. Therefore, the following description with respect to encapsulating the microelectronic die 20 shown in FIGS. 1-7B is for purpose of illustration only, and it is not intended to limit the scope of the invention.
  • the embodiment of the substrate 20 shown in FIG. 1 can have a first end 21 , a second end 22 opposite the first end 21 , a first surface 23 , and a second surface 24 opposite the first surface 23 .
  • the substrate 20 can also include an elongated slot 25 between the first and second surfaces 23 and 24 that extends lengthwise along a medial portion of the substrate 20 .
  • an aperture 26 through the substrate 20 can be located at a secondary gate location generally proximate to the second end 22 of the substrate 20 .
  • the substrate 20 is one component of an interconnecting unit that provides an array of ball-pads for coupling very small bond-pads on the microelectronic die 40 to voltage sources, signal sources, and/or other input/output sources. In the embodiment shown in FIG.
  • the substrate 20 includes an array of ball-pads 27 , an array of contact elements 28 proximate to the slot 25 , and a trace 29 or another type of conductive line between each ball-pad 27 and a corresponding contact element 28 .
  • the substrate 20 can be a flexible material or a substantially rigid material, and the traces 29 can be conductive lines that are printed on the substrate in a manner similar to printed circuit boards.
  • the embodiment of the microelectronic die 40 shown in FIG. 1 includes a front side 41 , a plurality of bond-pads 42 on the front side 41 , and an integrated circuit 44 (shown schematically).
  • the front side 41 of the die 40 is attached to the second surface 24 of the substrate 20 by an adhesive strip 60 .
  • the bond-pads 42 are coupled to the integrated circuit 44 , and the bond-pads 42 are also arranged in an array along the front side 41 of the microelectronic die 40 so that the bond-pads 42 are aligned with or otherwise accessible through the slot 25 in the substrate 20 .
  • a plurality of wire-bond lines 50 or other types of connectors couple the bond-pads 42 on the die 40 to corresponding contact elements 28 on the substrate 20 .
  • the substrate 20 distributes the very small bond-pads 42 to the larger array of ball-pads 27 .
  • the die 40 projects away from the second surface 24 of the substrate 20 such that a backside 45 of the die 40 is spaced apart from the second surface 24 of the substrate 20 .
  • the microelectronic device 10 can further include a protective casing having a first cover 70 a over the die 40 and a second cover 70 b over the slot 25 .
  • the first and second covers 70 a and 70 b can be formed from a thermosetting material, ceramics, or other suitable materials.
  • the first and second protective covers 70 a and 70 b can be molded as explained in U.S. patent application Ser. No. 09/255,554, which is herein incorporated by reference.
  • the embodiment of the microelectronic device 10 shown in FIG. 1 also includes a plurality of pressure relief elements 80 that are configured to release a gas entrapped in the microelectronic device 10 .
  • the substrate 20 and/or the adhesive strip 60 can absorb moisture, and the first and second covers 70 a and 70 b can entrap this moisture in the area around the die 40 .
  • the microelectronic device 10 is quickly heated in a solder reflow process or another high-temperature procedure, the entrapped moisture expands and creates a pressure gradient in the microelectronic device 10 .
  • the pressure relief elements 80 provide a path through which the expanding gas can escape without cracking the covers 70 a or 70 b , delaminating the substrate 20 and/or the covers 70 a or 70 b , or otherwise damaging the microelectronic device 10 .
  • FIG. 2A is a top isometric view and FIG. 2B is a front cross-sectional view that illustrate various embodiments of the pressure relief elements 80 in further detail.
  • the pressure relief elements 80 can be a series of passageways completely through the substrate 20 at an area outside of the ball-pads 27 .
  • the pressure relief elements 80 can be of elongated channels (shown on one side of the cover 70 b ), or the pressure relief elements 80 can be holes (shown on the other side of the second cover 70 b ).
  • the pressure relief elements 80 can also be shorter elongated channels or slots that fit between the ball-pads 27 and the traces 29 (shown in broken lines).
  • the pressure relief elements 80 will be either elongated channels on both sides of the second cover 70 b , or a series of holes on both sides of the second cover 70 b (as shown in FIG. 1 ).
  • the pressure relief elements 80 include a passageway 82 having a first end defined by an opening 84 at an external location and a second end at an interior point 86 of the microelectronic device 10 .
  • the opening 84 is at the first surface 23 of the substrate 20 and the interior point 86 is at the second surface 24 of the substrate 20 .
  • the pressure relief elements 80 of the embodiment shown in FIG. 2B are also positioned over the adhesive strip 60 to expose a portion of the adhesive 60 to the external environment.
  • the location of the pressure relief elements 80 is generally selected to provide a passageway to internal locations within the substrate where moisture is likely to be entrapped.
  • the pressure relief elements 80 can be configured to allow moisture to escape from the substrate 20 , the adhesive 60 , the covers 70 a and 70 b , and/or any combination of these components.
  • the pressure relief elements 80 shown in FIGS. 1-2B can be formed by etching or laser cutting the substrate 20 before attaching the adhesive 60 to the second surface 24 of the substrate 20 .
  • the pressure relief elements 80 for example, can be etched by masking the substrate 20 with a photo resist and etching through the substrate 20 with a suitable etchant. Similarly, a laser can cut through the substrate 20 using techniques that are known in the art.
  • the pressure relief elements 80 can also be formed by mechanically drilling (e.g., gang drilling), punching, stamping, or molding the holes or slots in the substrate 20 .
  • the microelectronic device 10 is particularly well suited for use in high temperature post-encapsulation processes, such as solder reflow processing and burn-in testing.
  • the microelectronic device 10 is subject to a process that rapidly increases the temperature, the expansion of the moisture entrapped in the substrate 20 , the adhesive 60 , and/or the first and second covers 70 a and 70 b generates a pressure gradient in the internal region of the microelectronic device 10 .
  • the adhesive tape 60 for example, is particularly subject to absorbing moisture, and thus a pressure gradient typically forms in the region of the adhesive 60 during high temperature processing.
  • the pressure relief elements 80 allow the moisture in the tape 60 and the other components of the device 10 to diffuse out of the device 10 before large pressure gradients are created in the substrate 20 or the first and second covers 70 a and 70 b .
  • the pressure relief elements 80 are accordingly expected to inhibit or completely prevent cracking or delaminating of the covers 70 a and 70 b during high temperature processing.
  • FIG. 3 is a front cross-sectional view of a microelectronic device 10 a in accordance with another embodiment of the invention.
  • the microelectronic device 10 a includes a substrate 20 , a die 40 attached to the substrate 20 by an adhesive 60 , and the first and second covers 70 a and 70 b .
  • the microelectronic device 10 a can also include a plurality of pressure relief elements 80 that are defined by passageways 82 extending through the substrate 20 .
  • the pressure relief elements 80 of the microelectronic device 10 are defined by passageways 82 that extend from the first surface 23 of the substrate 20 to the second surface 24 of the substrate 20 at a location over the first cover 70 a and spaced apart from the adhesive 60 .
  • the microelectronic device 10 a accordingly provides pressure relief elements 80 for allowing moisture to diffuse out of the substrate 20 and the first cover 70 a during high temperature processing.
  • the pressure relief elements 80 shown in FIGS. 2B and 3 are combined in a single microelectronic device having a first plurality of pressure relief elements 80 that expose the adhesive 60 to the external environment ( FIG. 2A ) and a second plurality of pressure relief elements 80 expose the interior of the first cover 70 a to an external environment ( FIG. 3 ).
  • FIG. 4A is a bottom isometric view and FIG. 4B is a front cross-sectional view of a microelectronic device 10 c in accordance with another embodiment of the invention.
  • the microelectronic device 10 c has a plurality of pressure relief elements 80 extending through the first cover 70 a .
  • the pressure relief elements 80 can be a series of passageways 82 extending through a top portion of the first cover 70 a .
  • Each passageway 82 can have an opening 84 exposed to external environment and an interior point 86 at the backside 45 of the die 40 .
  • the pressure relief elements 80 shown in FIG. 4B allow moisture to escape from the first cover 70 a during high temperature processing.
  • FIGS. 5A and 5B are front cross-sectional views of a microelectronic device 500 in accordance with another embodiment of the invention.
  • the microelectronic device 500 includes a substrate 520 having a first surface 523 and a second surface 524 .
  • the die 40 is attached to the second surface 524 of the substrate 520 , the first cover 70 a encases the die 40 , and the second cover 70 b encases the bond-pads 42 and the wire-bond lines 50 at the first surface 523 of the substrate 520 .
  • Several components of the microelectronic device 500 can be similar to the components of the microelectronic device 10 shown in FIG. 2B , and thus like reference numbers refer to like components in FIGS.
  • the substrate 520 can also have a slot 25 , a plurality of contact elements 28 adjacent to the slot 25 , a plurality of ball-pads 27 spaced apart from the contact elements 28 , and a plurality of conductive elements electrically coupling selected contact elements to corresponding ball-pads 27 .
  • the microelectronic device 500 can also include a plurality of pressure relief elements 580 through a portion of the substrate 520 .
  • the pressure relief elements 580 are depressions 582 that have an opening 584 at the first surface 523 on the substrate 520 and an interior point 586 proximate to the second surface 524 of the substrate 520 .
  • the depressions 582 do not extend completely through the substrate 520 such that the interior point 586 of the pressure relief elements 580 is at an intermediate depth in the substrate 520 .
  • the pressure relief elements 580 can be superimposed over the adhesive strips 60 (shown in FIG. 5A ), or the pressure relief 580 can be located over the first cover 70 a in a manner similar to the pressure relief elements 80 shown in FIG. 3 .
  • FIG. 5B illustrates the operation of the pressure relief elements 580 in the microelectronic device 500 .
  • the expanding moisture in the adhesive 60 , the substrate 520 , and/or the covers 70 a and 70 b can rupture the thin section of the substrate 520 at the interior point 586 of a passageway 582 to form a via 588 through which the expanding gas can escape.
  • the pressure relief elements 580 accordingly act as pressure relief valves that rupture to prevent the pressure gradient from becoming so large that it cracks or otherwise delaminates the first or second covers 70 a or 70 b .
  • the thickness “t” of the thin section of the substrate 520 between the interior point 586 and the second surface 524 can accordingly be selected to rupture and form the via 588 at a pressure that is less than the failure pressure of the first and second covers 70 a and 70 b.
  • the pressure relief elements 580 can also be fabricated by laser cutting, etching, drilling, stamping, embossing, or molding the substrate 520 .
  • a laser for example, can have a residence time that does not penetrate through the substrate 520 but rather only forms the depression 582 without passing through the second surface 524 .
  • Suitable laser and etching techniques that can form a controlled depression are known in the art.
  • FIGS. 6A and 6B are front cross-sectional views of a microelectronic device 600 in accordance with yet another embodiment of the invention.
  • the microelectronic device 600 can also include a plurality of pressure relief elements 680 through a portion of the first cover 70 a .
  • the pressure relief elements 680 can be a plurality of depressions 682 having an opening 684 and an interior point 686 .
  • the opening 684 is exposed to external environment, and the interior point 686 is at an intermediate depth in the first cover 70 a .
  • the thin section of the first cover 70 a between the interior point 686 and the backside 45 of the die 40 can rupture during a high temperature process to relieve pressure in the first cover 70 a .
  • the left-most pressure relief element 680 a in FIG. 6B illustrates a ruptured pressure relief element 680 that forms a via 688 through which high pressure gas can escape from the microelectronic device 600 .
  • the thickness t of the first cover 70 a between the back side 45 of the die 40 and the interior point 686 of the pressure relief element 680 can be selected to rupture at a predetermined pressure that is less than the failure pressure of the thicker portion of the cover 70 a .
  • the pressure relief elements 680 can act as pressure relief valves that are positioned at predetermined failure sites to relieve pressure within the microelectronic device 600 before the first cover 70 a or the second cover 70 b cracks or has another type of catastrophic failure.
  • FIG. 7 is a side cross-sectional view of a mold assembly and a method for forming the first cover 70 a for the microelectronic device 600 shown in FIGS. 6A and 6B .
  • the mold assembly can include a first mold section 200 and a second mold section 300 .
  • the first mold section 200 has a bearing surface 220 and a wire-side cavity 224
  • the second mold section 300 has a bearing surface 320 , a die-side cavity 324 , and a plurality of posts 329 in the die-side cavity 324 .
  • the wire-side cavity 224 is configured to form the second cover 70 b over the slot 25 of the substrate 20
  • the die-side cavity 324 is configured to form the first cover 70 a over the die 40 .
  • the second mold section 300 can also include a gate 326 and an injection chamber 328 through which a flow F of mold compound (e.g., thermosetting material) is injected into the die-side cavity 324 .
  • the substrate 20 is positioned between the first and second mold sections 200 and 300 to align the die 40 with the die-side cavity 324 and to align the slot 25 with the wire-side cavity 224 .
  • the bearing surface 320 of the second mold section 300 presses against the second surface 24 of the substrate 20
  • the bearing surface 220 of the first mold section 200 can press against the first surface 23 of the substrate 20 .
  • the bearing surface 220 of the first mold section 200 can engage the first surface 23 of the substrate 20 by injecting a mold compound into the die-side cavity 324 , as explained in U.S. patent application Ser. No. 09/255,554.
  • the flow of mold compound F initially passes through the gate 326 of the second mold section 300 and continues into the die-side cavity 324 to create a first flow A 1 of mold compound heading in a first direction toward the second end 22 of the substrate 20 .
  • the first flow A 1 of mold compound passes through the aperture 26 in the substrate 20 to generate a second flow B 1 of mold compound that flows through the wire-side cavity 224 of the first mold section 200 .
  • the second flow B 1 of mold compound fills the slot 25 of the substrate 20 and flows in a second direction until it reaches a terminal end 227 of the wire-side cavity 224 .
  • the post 329 in the die-side cavity 324 form the pressure relief elements 680 in the first cover 70 a shown in FIGS. 6A and 6B .
  • the posts 329 can be lengthened so that they engage the back side 45 of the substrate 40 when the bearing surface 320 of the second mold section 300 engages the second surface 24 of the substrate 20 .
  • certain embodiments of the pressure relief elements 80 shown in FIGS. 2A-3 or the pressure relief elements 580 shown in FIGS. 5A and 5B can also relieve pressures caused by mechanical stresses as a result of the different coefficients of thermal expansion for the different components of the microelectronic device 10 .
  • the substrate 20 generally has a different coefficient of thermal expansion than the molding compound of the first and second covers 70 a and 70 b .
  • the microelectronic device 10 generally has a low level of internal mechanical stress at room temperature because the first and second covers 70 a and 70 b shrink after cooling from the molding process. During high temperature processing, however, the microelectronic substrate 10 can have high internal mechanical stresses because the first and second covers 70 a and 70 b can expand much more than the substrate 20 .
  • the elongated pressure relief elements 80 shown on the one side of the cover 70 b in FIG. 2A are expected to reduce the internal mechanical stresses caused by different thermal expansion/contraction characteristics of the different components in the microelectronic device 10 because the elongated pressure relief elements 80 act as expansion joints.
  • pressure relief element can include structures that provide a path through which gas can escape from the microelectronic device, that relieve internal mechanical stresses caused by different thermal expansion/contraction characteristics, and/or that control or otherwise dissipate other internal stresses in microelectronic devices. Accordingly, the invention is not limited except by the appended claims.

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Abstract

Packaged microelectronic devices, interconnecting units for packaged microelectronic devices, and methods and apparatuses for packaging microelectronic devices with pressure release elements. In one aspect of the invention, a packaged microelectronic device includes a microelectronic die, an interconnecting unit coupled to the die, and a protective casing over the die. The interconnecting unit can have a substrate with a first side and a second side to which the die is attached, a plurality of contact elements operatively coupled to corresponding bond-pads on the die, and a plurality of ball-pads on the first side of the substrate electrically coupled to the contact elements. The protective casing can have at least a first cover encapsulating the die on the first side of the substrate. The packaged microelectronic device can also include a pressure relief element through at least a portion of the first cover and/or the substrate. The pressure relief element can have an opening to an external environment and a passageway to an internal location within the packaged microelectronic device. In operation, the pressure relief element releases gases or other forms of moisture entrapped by the casing and/or the substrate during high temperature processing of the packaged microelectronic device.

Description

    TECHNICAL FIELD
  • The present invention relates to packaging microelectronic devices having a microelectronic die including an integrated circuit. More particularly, several aspects of the invention are related to releasing pressure within packaged microelectronic devices during high temperature processes, such as reflow processing and burn-in testing.
    • BACKGROUND
  • Microelectronic devices, such as memory devices and microprocessors, typically include a microelectronic die encased in a protective covering. The die can include memory cells, processor circuits, interconnecting circuitry and/or other functional features. The die also typically includes an array of very small bond-pads electrically coupled to the functional features. When the die is packaged, the bond-pads are coupled to leads, solder ball-pads or other types of terminals for operatively coupling the microelectronic dies to buses, circuits and/or other microelectronic devices.
  • Several different techniques have been developed for packaging microelectronic dies. The dies, for example, can be incorporated into individual packages, mounted with other components in hybrid or multiple chip modules, or connected directly to a printed circuit board or other types of substrates. When a die is incorporated into an individual package, the bond-pads on the die are typically coupled to a lead frame, and the die is covered or otherwise sealed from the environment. When the die is attached directly to a printed circuit board or another type of substrate, the bond-pads on the die are typically coupled to corresponding contact elements on the substrate using wire-bond lines, ball grid arrays and other techniques. The dies that are mounted directly to the substrates are generally Chip Scale Package devices (CSP) or Flip Chip Bare Die devices (Flip-Chip).
  • CSP and Flip-Chip devices generally have one or more protective casings that encapsulate the dies and any exposed contact elements, bond-pads or wire-bond lines. The protective casings should shield the die and the other components on the substrate from environmental factors (e.g., moisture), electrical interference, and mechanical shocks. The protective casings are accordingly robust elements that protect the sensitive components of a microelectronic device. The protective casings are generally composed of plastics, ceramics, or thermosetting materials.
  • One conventional technique for fabricating the protective casings involves placing the die in a cavity of a mold, and then injecting a thermosetting material into the cavity. The thermosetting material flows over the die on one side of the substrate until it fills the cavity, and then the thermosetting material is cured so that it hardens into a suitable protective casing for protecting the die. According to conventional practices, the protective casing should not have any voids over the die because contaminants from the molding process or environmental factors outside of the mold could damage the die. The thermosetting material, moreover, should not cover a ball-pad array on the substrate or damage any electrical connections between the die and the substrate. Therefore, according to conventional practices, the thermosetting material should be molded in a manner that avoids (a) producing voids in the protective casing, (b) covering certain portions of the substrate with the thermosetting material, and (c) displacing or otherwise damaging any wire-bond lines or solder joints between the die and the substrate.
  • One drawback of packaging microelectronic devices is that during high-temperature processing cracks or voids can form in the protective casing, or the protective casing can delaminate from the substrate. Such cracking or delamination, for example, may occur during a solder reflow procedure in which the packaged microelectronic devices are quickly heated to reflow solder balls and/or or solder paste pads. This problem is particularly noticeable in procedures that quickly heat the packaged devices to an elevated temperature. When the casing of a packaged microelectronic device cracks or delaminates from the substrate, the device is often rejected because such cracks or voids can expose very delicate components (e.g., bond-pads or wire-bond lines) to external environmental factors. It will be appreciated that such cracking of the casing results in extremely expensive losses because it occurs at the end of the fabrication process after a significant amount of money has been expended to manufacture each packaged microelectronic device. Therefore, it would be desirable to develop an apparatus and method for reducing or completely preventing the casing from cracking or delaminating from the substrate during high temperature processing.
    • SUMMARY
  • The present invention is directed toward packaged microelectronic devices and methods for making and using such packaged microelectronic devices. In one aspect of the invention, a packaged microelectronic device includes a microelectronic die, an interconnecting unit coupled to the die, and a protective casing over the die. The microelectronic die, for example, may have an integrated circuit and a bond-pad array having a plurality of bond-pads operatively coupled to the integrated circuit. The interconnecting unit has a substrate with a first side and a second side to which the die is attached, a plurality of contact elements operatively coupled to corresponding bond-pads on the die, and a plurality of ball-pads on the first side of the substrate. The interconnecting unit can also include a plurality of conductive elements extending from selected contact elements to corresponding ball-pads to electrically couple the contact elements to the ball-pads. The protective casing can have at least a first cover encapsulating the die on the first side of the substrate.
  • The packaged microelectronic device can also include a pressure relief element through at least a portion of the first cover and/or the substrate. The pressure relief element can have an opening to an external environment and a passageway to an internal location or interior point within the packaged microelectronic device. The pressure relief element, for example, can be a hole or opening through the substrate to an adhesive strip on the bottom side of the die. In another embodiment, the pressure relief element is a hole through the first cover to either the substrate or the microelectronic die. In still another embodiment, the pressure relief element is a depression that extends only part way through the cover or the substrate such that the passageway forms a thin section of the first cover or the substrate. In operation, the pressure relief element releases gases or other forms of moisture entrapped by the casing and/or the substrate during high temperature processing of the packaged microelectronic device.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a top cut-away isometric view illustrating a portion of a microelectronic device in accordance with an embodiment of the invention.
  • FIG. 2A is a top isometric view of the microelectronic device of FIG. 1.
  • FIG. 2B is a front cross-sectional view of the microelectronic device of FIG. 2A.
  • FIG. 3 is a front cross-sectional view of a microelectronic device in accordance with another embodiment of the invention.
  • FIG. 4A is a bottom isometric view and FIG. 4B is a front cross-sectional view of a microelectronic device in accordance with another embodiment of the invention.
  • FIGS. 5A and 5B are front cross-sectional views of a microelectronic device in accordance with another embodiment of the invention.
  • FIGS. 6A and 6B are front cross-sectional views of a microelectronic device in accordance with still another embodiment of the invention.
  • FIG. 7 is a side cross-sectional view of a microelectronic device and a mold assembly used to form a protective casing with pressure relief elements in accordance with an embodiment of the invention.
    • DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS
  • The following disclosure is directed toward packaged microelectronic devices, interconnecting units for packaged microelectronic devices, and methods for manufacturing and using packaged microelectronic devices. Several embodiments of the invention are described with reference to memory devices, but the methods and apparatuses are also applicable to microprocessors and other types of devices. One skilled in the art will accordingly understand that the present invention may have additional embodiments, or that the invention may be practiced without several of the details described below.
  • FIG. 1 is a top cut-away isometric view of a microelectronic device 10 in accordance with one embodiment of the invention. The microelectronic device 10 can include a substrate 20 and a microelectronic die 40 attached to the substrate 20 by an adhesive strip 60. The following description is directed toward encapsulating a microelectronic die on a flexible substrate, but it is expected that several embodiments of the methods and apparatuses in accordance with the present invention may be practiced to encapsulate a large variety of electrical and/or non-electrical articles. Therefore, the following description with respect to encapsulating the microelectronic die 20 shown in FIGS. 1-7B is for purpose of illustration only, and it is not intended to limit the scope of the invention.
  • The embodiment of the substrate 20 shown in FIG. 1 can have a first end 21, a second end 22 opposite the first end 21, a first surface 23, and a second surface 24 opposite the first surface 23. The substrate 20 can also include an elongated slot 25 between the first and second surfaces 23 and 24 that extends lengthwise along a medial portion of the substrate 20. Additionally, an aperture 26 through the substrate 20 can be located at a secondary gate location generally proximate to the second end 22 of the substrate 20. The substrate 20 is one component of an interconnecting unit that provides an array of ball-pads for coupling very small bond-pads on the microelectronic die 40 to voltage sources, signal sources, and/or other input/output sources. In the embodiment shown in FIG. 1, the substrate 20 includes an array of ball-pads 27, an array of contact elements 28 proximate to the slot 25, and a trace 29 or another type of conductive line between each ball-pad 27 and a corresponding contact element 28. The substrate 20 can be a flexible material or a substantially rigid material, and the traces 29 can be conductive lines that are printed on the substrate in a manner similar to printed circuit boards.
  • The embodiment of the microelectronic die 40 shown in FIG. 1 includes a front side 41, a plurality of bond-pads 42 on the front side 41, and an integrated circuit 44 (shown schematically). The front side 41 of the die 40 is attached to the second surface 24 of the substrate 20 by an adhesive strip 60. The bond-pads 42 are coupled to the integrated circuit 44, and the bond-pads 42 are also arranged in an array along the front side 41 of the microelectronic die 40 so that the bond-pads 42 are aligned with or otherwise accessible through the slot 25 in the substrate 20. A plurality of wire-bond lines 50 or other types of connectors couple the bond-pads 42 on the die 40 to corresponding contact elements 28 on the substrate 20. As such, the substrate 20 distributes the very small bond-pads 42 to the larger array of ball-pads 27. The die 40 projects away from the second surface 24 of the substrate 20 such that a backside 45 of the die 40 is spaced apart from the second surface 24 of the substrate 20.
  • The microelectronic device 10 can further include a protective casing having a first cover 70 a over the die 40 and a second cover 70 b over the slot 25. The first and second covers 70 a and 70 b can be formed from a thermosetting material, ceramics, or other suitable materials. The first and second protective covers 70 a and 70 b can be molded as explained in U.S. patent application Ser. No. 09/255,554, which is herein incorporated by reference.
  • The embodiment of the microelectronic device 10 shown in FIG. 1 also includes a plurality of pressure relief elements 80 that are configured to release a gas entrapped in the microelectronic device 10. The substrate 20 and/or the adhesive strip 60 can absorb moisture, and the first and second covers 70 a and 70 b can entrap this moisture in the area around the die 40. When the microelectronic device 10 is quickly heated in a solder reflow process or another high-temperature procedure, the entrapped moisture expands and creates a pressure gradient in the microelectronic device 10. The pressure relief elements 80 provide a path through which the expanding gas can escape without cracking the covers 70 a or 70 b, delaminating the substrate 20 and/or the covers 70 a or 70 b, or otherwise damaging the microelectronic device 10.
  • FIG. 2A is a top isometric view and FIG. 2B is a front cross-sectional view that illustrate various embodiments of the pressure relief elements 80 in further detail. Referring to FIG. 2A, the pressure relief elements 80 can be a series of passageways completely through the substrate 20 at an area outside of the ball-pads 27. The pressure relief elements 80 can be of elongated channels (shown on one side of the cover 70 b), or the pressure relief elements 80 can be holes (shown on the other side of the second cover 70 b). The pressure relief elements 80 can also be shorter elongated channels or slots that fit between the ball-pads 27 and the traces 29 (shown in broken lines). In a typical application, the pressure relief elements 80 will be either elongated channels on both sides of the second cover 70 b, or a series of holes on both sides of the second cover 70 b (as shown in FIG. 1). Referring to FIG. 2B, the pressure relief elements 80 include a passageway 82 having a first end defined by an opening 84 at an external location and a second end at an interior point 86 of the microelectronic device 10. In the particular embodiment shown in FIG. 2B, the opening 84 is at the first surface 23 of the substrate 20 and the interior point 86 is at the second surface 24 of the substrate 20.
  • The pressure relief elements 80 of the embodiment shown in FIG. 2B are also positioned over the adhesive strip 60 to expose a portion of the adhesive 60 to the external environment. The location of the pressure relief elements 80 is generally selected to provide a passageway to internal locations within the substrate where moisture is likely to be entrapped. Thus, as explained in more detail below, the pressure relief elements 80 can be configured to allow moisture to escape from the substrate 20, the adhesive 60, the covers 70 a and 70 b, and/or any combination of these components.
  • The pressure relief elements 80 shown in FIGS. 1-2B can be formed by etching or laser cutting the substrate 20 before attaching the adhesive 60 to the second surface 24 of the substrate 20. The pressure relief elements 80, for example, can be etched by masking the substrate 20 with a photo resist and etching through the substrate 20 with a suitable etchant. Similarly, a laser can cut through the substrate 20 using techniques that are known in the art. The pressure relief elements 80 can also be formed by mechanically drilling (e.g., gang drilling), punching, stamping, or molding the holes or slots in the substrate 20.
  • The microelectronic device 10 is particularly well suited for use in high temperature post-encapsulation processes, such as solder reflow processing and burn-in testing. When the microelectronic device 10 is subject to a process that rapidly increases the temperature, the expansion of the moisture entrapped in the substrate 20, the adhesive 60, and/or the first and second covers 70 a and 70 b generates a pressure gradient in the internal region of the microelectronic device 10. The adhesive tape 60, for example, is particularly subject to absorbing moisture, and thus a pressure gradient typically forms in the region of the adhesive 60 during high temperature processing. The pressure relief elements 80 allow the moisture in the tape 60 and the other components of the device 10 to diffuse out of the device 10 before large pressure gradients are created in the substrate 20 or the first and second covers 70 a and 70 b. The pressure relief elements 80 are accordingly expected to inhibit or completely prevent cracking or delaminating of the covers 70 a and 70 b during high temperature processing.
  • FIG. 3 is a front cross-sectional view of a microelectronic device 10 a in accordance with another embodiment of the invention. In this embodiment, the microelectronic device 10 a includes a substrate 20, a die 40 attached to the substrate 20 by an adhesive 60, and the first and second covers 70 a and 70 b. The microelectronic device 10 a can also include a plurality of pressure relief elements 80 that are defined by passageways 82 extending through the substrate 20. Unlike the microelectronic device 10 in which the passageways 82 extend to the adhesive 60, the pressure relief elements 80 of the microelectronic device 10 are defined by passageways 82 that extend from the first surface 23 of the substrate 20 to the second surface 24 of the substrate 20 at a location over the first cover 70 a and spaced apart from the adhesive 60. The microelectronic device 10 a accordingly provides pressure relief elements 80 for allowing moisture to diffuse out of the substrate 20 and the first cover 70 a during high temperature processing. In another embodiment, the pressure relief elements 80 shown in FIGS. 2B and 3 are combined in a single microelectronic device having a first plurality of pressure relief elements 80 that expose the adhesive 60 to the external environment (FIG. 2A) and a second plurality of pressure relief elements 80 expose the interior of the first cover 70 a to an external environment (FIG. 3).
  • FIG. 4A is a bottom isometric view and FIG. 4B is a front cross-sectional view of a microelectronic device 10 c in accordance with another embodiment of the invention. Referring to FIG. 4A, the microelectronic device 10 c has a plurality of pressure relief elements 80 extending through the first cover 70 a. Referring to FIG. 4B, the pressure relief elements 80 can be a series of passageways 82 extending through a top portion of the first cover 70 a. Each passageway 82 can have an opening 84 exposed to external environment and an interior point 86 at the backside 45 of the die 40. In operation, the pressure relief elements 80 shown in FIG. 4B allow moisture to escape from the first cover 70 a during high temperature processing.
  • FIGS. 5A and 5B are front cross-sectional views of a microelectronic device 500 in accordance with another embodiment of the invention. Referring to FIG. 5A, the microelectronic device 500 includes a substrate 520 having a first surface 523 and a second surface 524. The die 40 is attached to the second surface 524 of the substrate 520, the first cover 70 a encases the die 40, and the second cover 70 b encases the bond-pads 42 and the wire-bond lines 50 at the first surface 523 of the substrate 520. Several components of the microelectronic device 500 can be similar to the components of the microelectronic device 10 shown in FIG. 2B, and thus like reference numbers refer to like components in FIGS. 2B, 5A and 5B. The substrate 520, for example, can also have a slot 25, a plurality of contact elements 28 adjacent to the slot 25, a plurality of ball-pads 27 spaced apart from the contact elements 28, and a plurality of conductive elements electrically coupling selected contact elements to corresponding ball-pads 27.
  • The microelectronic device 500 can also include a plurality of pressure relief elements 580 through a portion of the substrate 520. In the embodiment illustrated in FIG. 5A, the pressure relief elements 580 are depressions 582 that have an opening 584 at the first surface 523 on the substrate 520 and an interior point 586 proximate to the second surface 524 of the substrate 520. The depressions 582 do not extend completely through the substrate 520 such that the interior point 586 of the pressure relief elements 580 is at an intermediate depth in the substrate 520. The pressure relief elements 580 can be superimposed over the adhesive strips 60 (shown in FIG. 5A), or the pressure relief 580 can be located over the first cover 70 a in a manner similar to the pressure relief elements 80 shown in FIG. 3.
  • FIG. 5B illustrates the operation of the pressure relief elements 580 in the microelectronic device 500. As the microelectronic device 500 is heated during a high temperature process, the expanding moisture in the adhesive 60, the substrate 520, and/or the covers 70 a and 70 b can rupture the thin section of the substrate 520 at the interior point 586 of a passageway 582 to form a via 588 through which the expanding gas can escape. The pressure relief elements 580 accordingly act as pressure relief valves that rupture to prevent the pressure gradient from becoming so large that it cracks or otherwise delaminates the first or second covers 70 a or 70 b. The thickness “t” of the thin section of the substrate 520 between the interior point 586 and the second surface 524 can accordingly be selected to rupture and form the via 588 at a pressure that is less than the failure pressure of the first and second covers 70 a and 70 b.
  • The pressure relief elements 580 can also be fabricated by laser cutting, etching, drilling, stamping, embossing, or molding the substrate 520. A laser, for example, can have a residence time that does not penetrate through the substrate 520 but rather only forms the depression 582 without passing through the second surface 524. Suitable laser and etching techniques that can form a controlled depression are known in the art.
  • FIGS. 6A and 6B are front cross-sectional views of a microelectronic device 600 in accordance with yet another embodiment of the invention. Several components of the microelectronic device 600 can be similar to the components of the microelectronic device 10 shown in FIG. 2B, and thus like reference numbers refer to like parts in FIGS. 2B, 6A and 6B. The microelectronic device 600 can also include a plurality of pressure relief elements 680 through a portion of the first cover 70 a. The pressure relief elements 680, for example, can be a plurality of depressions 682 having an opening 684 and an interior point 686. The opening 684 is exposed to external environment, and the interior point 686 is at an intermediate depth in the first cover 70 a. Referring to FIG. 6B, the thin section of the first cover 70 a between the interior point 686 and the backside 45 of the die 40 can rupture during a high temperature process to relieve pressure in the first cover 70 a. The left-most pressure relief element 680 a in FIG. 6B, for example, illustrates a ruptured pressure relief element 680 that forms a via 688 through which high pressure gas can escape from the microelectronic device 600. As set forth above, the thickness t of the first cover 70 a between the back side 45 of the die 40 and the interior point 686 of the pressure relief element 680 can be selected to rupture at a predetermined pressure that is less than the failure pressure of the thicker portion of the cover 70 a. As such, the pressure relief elements 680 can act as pressure relief valves that are positioned at predetermined failure sites to relieve pressure within the microelectronic device 600 before the first cover 70 a or the second cover 70 b cracks or has another type of catastrophic failure.
  • FIG. 7 is a side cross-sectional view of a mold assembly and a method for forming the first cover 70 a for the microelectronic device 600 shown in FIGS. 6A and 6B. The mold assembly can include a first mold section 200 and a second mold section 300. The first mold section 200 has a bearing surface 220 and a wire-side cavity 224, and the second mold section 300 has a bearing surface 320, a die-side cavity 324, and a plurality of posts 329 in the die-side cavity 324. The wire-side cavity 224 is configured to form the second cover 70 b over the slot 25 of the substrate 20, and the die-side cavity 324 is configured to form the first cover 70 a over the die 40. The second mold section 300 can also include a gate 326 and an injection chamber 328 through which a flow F of mold compound (e.g., thermosetting material) is injected into the die-side cavity 324.
  • During the molding process, the substrate 20 is positioned between the first and second mold sections 200 and 300 to align the die 40 with the die-side cavity 324 and to align the slot 25 with the wire-side cavity 224. The bearing surface 320 of the second mold section 300 presses against the second surface 24 of the substrate 20, and the bearing surface 220 of the first mold section 200 can press against the first surface 23 of the substrate 20. The bearing surface 220 of the first mold section 200 can engage the first surface 23 of the substrate 20 by injecting a mold compound into the die-side cavity 324, as explained in U.S. patent application Ser. No. 09/255,554. The flow of mold compound F initially passes through the gate 326 of the second mold section 300 and continues into the die-side cavity 324 to create a first flow A1 of mold compound heading in a first direction toward the second end 22 of the substrate 20. The first flow A1 of mold compound passes through the aperture 26 in the substrate 20 to generate a second flow B1 of mold compound that flows through the wire-side cavity 224 of the first mold section 200. The second flow B1 of mold compound fills the slot 25 of the substrate 20 and flows in a second direction until it reaches a terminal end 227 of the wire-side cavity 224. When the mold compound sufficiently fills the die-side cavity 324 and the wire-side cavity 224, the post 329 in the die-side cavity 324 form the pressure relief elements 680 in the first cover 70 a shown in FIGS. 6A and 6B. Similarly, to form the pressure relief elements 80 in the first cover 70 a shown in FIG. 4B, the posts 329 can be lengthened so that they engage the back side 45 of the substrate 40 when the bearing surface 320 of the second mold section 300 engages the second surface 24 of the substrate 20.
  • From the foregoing it will be appreciated that specific embodiments of the invention have been disclosed for purposes of enablement and illustration, but that various modifications may be made without deviating from the spirit and scope of the invention. For example, certain embodiments of the pressure relief elements 80 shown in FIGS. 2A-3 or the pressure relief elements 580 shown in FIGS. 5A and 5B can also relieve pressures caused by mechanical stresses as a result of the different coefficients of thermal expansion for the different components of the microelectronic device 10. The substrate 20 generally has a different coefficient of thermal expansion than the molding compound of the first and second covers 70 a and 70 b. The microelectronic device 10 generally has a low level of internal mechanical stress at room temperature because the first and second covers 70 a and 70 b shrink after cooling from the molding process. During high temperature processing, however, the microelectronic substrate 10 can have high internal mechanical stresses because the first and second covers 70 a and 70 b can expand much more than the substrate 20. The elongated pressure relief elements 80 shown on the one side of the cover 70 b in FIG. 2A are expected to reduce the internal mechanical stresses caused by different thermal expansion/contraction characteristics of the different components in the microelectronic device 10 because the elongated pressure relief elements 80 act as expansion joints. Thus, the term pressure relief element can include structures that provide a path through which gas can escape from the microelectronic device, that relieve internal mechanical stresses caused by different thermal expansion/contraction characteristics, and/or that control or otherwise dissipate other internal stresses in microelectronic devices. Accordingly, the invention is not limited except by the appended claims.

Claims (21)

1. A packaged microelectronic device, comprising:
a microelectronic die having an integrated circuit and a bond-pad array having a plurality of bond-pads operatively coupled to the integrated circuit;
an interconnecting unit having a substrate with a first side and a second side to which the die is attached, a plurality of contact elements operatively coupled to corresponding bond-pads on the die, a plurality of ball-pads on the first side, and a plurality of conductive elements extending from selected contact elements to corresponding ball-pads;
a protective casing having at least a first cover encapsulating the die on the second side of the substrate; and
a pressure relief element through at least a portion of the first cover and/or the substrate, the pressure relief element having an opening to an external environment and a passageway to an internal location.
2. The device of claim 1 wherein the pressure relief element is a hole completely through the substrate such that the opening is at the first side of the substrate and the internal location is at the second side of the substrate.
3. The device of claim 2 wherein:
the microelectronic die is attached to the second side of the substrate by an adhesive; and
the pressure relief element is over the adhesive such that the adhesive is exposed to the external environment through the passageway.
4. The device of claim 1 wherein the pressure relief element is an elongated channel completely through the substrate such that the opening is at the first side of the substrate and the internal location is at the second side of the substrate.
5. The device of claim 4 wherein:
the microelectronic die is attached to the second side of the substrate by an adhesive; and
the pressure relief element is over the adhesive such that the adhesive is exposed to the external environment through the passageway.
6. The device of claim 1 wherein the pressure relief element is a depression in the substrate that does not pass completely through the substrate such that the opening is at the first side of the substrate and the internal location is at an intermediate depth within the substrate, the substrate having a thickness between the internal location and the second side that is configured to rupture at a predetermined pressure.
7. The device of claim 6 wherein:
the microelectronic die is attached to the second side of the substrate by an adhesive; and
the depression is over the adhesive.
8. The device of claim 1 wherein the pressure relief element is a hole completely through the first cover such that the internal location is at a backside of the die.
9. The device of claim 1 wherein the pressure relief element is a depression in the first cover that does not pass completely through the first cover such that the internal location is at an intermediate depth within the first cover, the first cover having a thickness between the internal location and a backside of the die that is configured to rupture at a predetermined pressure.
10. A packaged microelectronic device, comprising:
a microelectronic die having an integrated circuit and a bond-pad array having a plurality of bond-pads operatively coupled to the integrated circuit;
an interconnecting unit having a substrate with a first side and a second side to which the die is attached, a plurality of contact elements operatively coupled to corresponding bond-pads on the die, a plurality of ball-pads on the first side, and a plurality of conductive elements extending from selected contact elements to corresponding ball-pads;
a protective casing having at least a first cover encapsulating the die on the second side of the substrate; and
a pressure relief element through at least a portion of the first cover and/or the substrate, the pressure relief element being configured to release a gas entrapped by the casing and/or the substrate.
11. The device of claim 10 wherein the pressure relief element is a hole completely through the substrate such that the opening is at the first side of the substrate and the internal location is at the second side of the substrate.
12. The device of claim 11 wherein:
the microelectronic die is attached to the second side of the substrate by an adhesive; and
the pressure relief element is over the adhesive such that the adhesive is exposed to the external environment through the passageway.
13. The device of claim 10 wherein the pressure relief element is an elongated channel completely through the substrate such that the opening is at the first side of the substrate and the internal location is at the second side of the substrate.
14. The device of claim 13 wherein:
the microelectronic die is attached to the second side of the substrate by an adhesive; and
the pressure relief element is over the adhesive such that the adhesive is exposed to the external environment through the passageway.
15. The device of claim 10 wherein the pressure relief element is a depression in the substrate that does not pass completely through the substrate such that the opening is at the first side of the substrate and the internal location is at an intermediate depth within the substrate, the substrate having a thickness between the internal location and the second side that is configured to rupture at a predetermined pressure.
16. The device of claim 15 wherein:
the microelectronic die is attached to the second side of the substrate by an adhesive; and
the depression is over the adhesive.
17. The device of claim 10 wherein the pressure relief element is a hole completely through the first cover such that the internal location is at a backside of the die.
18. The device of claim 10 wherein the pressure relief element is a depression in the first cover that does not pass completely through the first cover such that the internal location is at an intermediate depth within the first cover, the first cover having a thickness between the internal location and a backside of the die that is configured to rupture at a predetermined pressure.
19. A packaged microelectronic device, comprising:
an interconnecting unit having a substrate with a first side and a second side, a slot defining an open region between the first and second sides, a plurality of contact elements on the first side and adjacent to the slot, a plurality of ball-pads on the first side, and a plurality of conductive elements on the first side extending from selected contact elements to corresponding ball-pads;
a microelectronic die having an integrated circuit and a plurality of bond-pads operatively coupled to the integrated circuit, the die being attached to the second side of the substrates, and the bond-pads being aligned with the slot;
a plurality of wire-bond lines in the slot extending between selected bond-pads on the die and corresponding contact elements on the substrate;
a protective casing having a first cover encapsulating the die on the second side of the substrate and a second cover encapsulating the bond-pads, the wire-bond lines and the contact elements; and
a first pressure relief element through at least a portion of the first cover and/or the substrate, the pressure relief element being configured to release a gas entrapped by the casing and/or the substrate.
20. The device of claim 19 wherein the pressure relief element is a hole completely through the substrate such that the opening is at the first side of the substrate and the internal location is at the second side of the substrate.
21-49. (canceled)
US11/401,514 2000-08-24 2006-04-11 Packaged microelectronic devices with pressure release elements and methods for manufacturing and using such packaged microelectonic devices Abandoned US20060180907A1 (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070007637A1 (en) * 2004-08-12 2007-01-11 Marinov Valery R Multi-layered substrate assembly with vialess electrical interconnect scheme
US20070045807A1 (en) * 2005-09-01 2007-03-01 Micron Technology, Inc. Microelectronic devices and methods for manufacturing microelectronic devices
US20080128900A1 (en) * 2006-12-04 2008-06-05 Micron Technology, Inc. Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
US7833456B2 (en) 2007-02-23 2010-11-16 Micron Technology, Inc. Systems and methods for compressing an encapsulant adjacent a semiconductor workpiece

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6589820B1 (en) 2000-06-16 2003-07-08 Micron Technology, Inc. Method and apparatus for packaging a microelectronic die
US7273769B1 (en) * 2000-08-16 2007-09-25 Micron Technology, Inc. Method and apparatus for removing encapsulating material from a packaged microelectronic device
US6483044B1 (en) * 2000-08-23 2002-11-19 Micron Technology, Inc. Interconnecting substrates for electrical coupling of microelectronic components
US6979595B1 (en) * 2000-08-24 2005-12-27 Micron Technology, Inc. Packaged microelectronic devices with pressure release elements and methods for manufacturing and using such packaged microelectronic devices
US6838760B1 (en) * 2000-08-28 2005-01-04 Micron Technology, Inc. Packaged microelectronic devices with interconnecting units
US7262074B2 (en) * 2002-07-08 2007-08-28 Micron Technology, Inc. Methods of fabricating underfilled, encapsulated semiconductor die assemblies
US20040113240A1 (en) * 2002-10-11 2004-06-17 Wolfgang Hauser An electronic component with a leadframe
DE112004002527T5 (en) * 2004-01-06 2008-03-06 Infineon Technologies Ag Method for encapsulating circuit chips
KR100652395B1 (en) * 2005-01-12 2006-12-01 삼성전자주식회사 Semiconductor device having reduced die-warpage and method of manufacturing the same
US7492044B2 (en) * 2005-10-06 2009-02-17 Lenovo (Singapore) Pte. Ltd. System and method for decreasing stress on solder holding BGA module to computer motherboard
US20070200253A1 (en) * 2006-02-28 2007-08-30 Gogoi Bishnu P Electronic assembly and method for forming the same
US7521297B2 (en) * 2006-03-17 2009-04-21 Stats Chippac Ltd. Multichip package system
JP5247626B2 (en) * 2008-08-22 2013-07-24 住友化学株式会社 Lead frame, resin package, semiconductor device, and resin package manufacturing method
US8264091B2 (en) * 2009-09-21 2012-09-11 Stats Chippac Ltd. Integrated circuit packaging system with encapsulated via and method of manufacture thereof
JP5885690B2 (en) 2012-04-27 2016-03-15 キヤノン株式会社 Electronic components and equipment
JP6296687B2 (en) * 2012-04-27 2018-03-20 キヤノン株式会社 Electronic components, electronic modules, and methods for manufacturing them.
JP2013243340A (en) * 2012-04-27 2013-12-05 Canon Inc Electronic component, mounting member, electronic apparatus, and manufacturing method of these
JP5918797B2 (en) * 2014-03-31 2016-05-18 株式会社加藤電器製作所 Electronic device and method for manufacturing electronic device
US9905515B2 (en) * 2014-08-08 2018-02-27 Mediatek Inc. Integrated circuit stress releasing structure
USD1044751S1 (en) * 2021-01-19 2024-10-01 Johnstech International Corporation Compliant ground block and testing system for testing integrated circuits

Citations (92)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3672046A (en) * 1970-01-14 1972-06-27 Technitrol Inc The method of making an electrical component
US4285780A (en) * 1978-11-02 1981-08-25 Schachter Herbert I Method of making a multi-level circuit board
US4855807A (en) * 1986-12-26 1989-08-08 Kabushiki Kaisha Toshiba Semiconductor device
US5105259A (en) * 1990-09-28 1992-04-14 Motorola, Inc. Thermally enhanced semiconductor device utilizing a vacuum to ultimately enhance thermal dissipation
US5107328A (en) * 1991-02-13 1992-04-21 Micron Technology, Inc. Packaging means for a semiconductor die having particular shelf structure
US5122858A (en) * 1990-09-10 1992-06-16 Olin Corporation Lead frame having polymer coated surface portions
US5128831A (en) * 1991-10-31 1992-07-07 Micron Technology, Inc. High-density electronic package comprising stacked sub-modules which are electrically interconnected by solder-filled vias
US5138434A (en) * 1991-01-22 1992-08-11 Micron Technology, Inc. Packaging for semiconductor logic devices
US5191174A (en) * 1990-08-01 1993-03-02 International Business Machines Corporation High density circuit board and method of making same
US5195023A (en) * 1991-12-23 1993-03-16 At&T Bell Laboratories Integrated circuit package with strain relief grooves
US5197183A (en) * 1991-11-05 1993-03-30 Lsi Logic Corporation Modified lead frame for reducing wire wash in transfer molding of IC packages
US5208467A (en) * 1988-07-28 1993-05-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a film-covered packaged component
US5294835A (en) * 1992-07-28 1994-03-15 Nitto Denko Corporation Epoxy resin composition for semiconductor encapsulation and semiconductor device using the same
US5296738A (en) * 1991-07-08 1994-03-22 Motorola, Inc. Moisture relief for chip carrier
US5309026A (en) * 1991-11-19 1994-05-03 Nippon Precision Circuits Ltd. Integrated circuit package having stress reducing recesses
US5314842A (en) * 1988-09-30 1994-05-24 Kabushiki Kaisha Toshiba Resin-sealed type semiconductor device and method for manufacturing the same
US5328079A (en) * 1993-03-19 1994-07-12 National Semiconductor Corporation Method of and arrangement for bond wire connecting together certain integrated circuit components
US5420460A (en) * 1993-08-05 1995-05-30 Vlsi Technology, Inc. Thin cavity down ball grid array package based on wirebond technology
US5527743A (en) * 1993-08-18 1996-06-18 Lsi Logic Corporation Method for encapsulating an integrated circuit package
US5593927A (en) * 1993-10-14 1997-01-14 Micron Technology, Inc. Method for packaging semiconductor dice
US5596231A (en) * 1991-08-05 1997-01-21 Asat, Limited High power dissipation plastic encapsulated package for integrated circuit die
US5606204A (en) * 1994-06-23 1997-02-25 Nec Corporation Resin-sealed semiconductor device
US5609889A (en) * 1995-05-26 1997-03-11 Hestia Technologies, Inc. Apparatus for encapsulating electronic packages
US5612576A (en) * 1992-10-13 1997-03-18 Motorola Self-opening vent hole in an overmolded semiconductor device
US5635220A (en) * 1994-09-22 1997-06-03 Nec Corporation Molding die for sealing semiconductor device with reduced resin burrs
US5639695A (en) * 1994-11-02 1997-06-17 Motorola, Inc. Low-profile ball-grid array semiconductor package and method
US5710071A (en) * 1995-12-04 1998-01-20 Motorola, Inc. Process for underfilling a flip-chip semiconductor device
US5721450A (en) * 1995-06-12 1998-02-24 Motorola, Inc. Moisture relief for chip carriers
US5728600A (en) * 1994-11-15 1998-03-17 Vlt Corporation Circuit encapsulation process
US5739585A (en) * 1995-11-27 1998-04-14 Micron Technology, Inc. Single piece package for semiconductor die
US5750423A (en) * 1995-08-25 1998-05-12 Dai-Ichi Seiko Co., Ltd. Method for encapsulation of semiconductor devices with resin and leadframe therefor
USD394844S (en) * 1997-04-25 1998-06-02 Micron Technology, Inc. Temporary package for semiconductor dice
US5767568A (en) * 1994-12-09 1998-06-16 Sony Corporation Semiconductor device
US5767446A (en) * 1995-10-27 1998-06-16 Anam Industrial Co., Ltd. Printed circuit board having epoxy barrier around a throughout slot and ball grid array semiconductor package
US5766649A (en) * 1995-12-15 1998-06-16 Nec Corporation Resin sealing mold die set with less resin remainder for semiconductor device
US5773322A (en) * 1995-05-01 1998-06-30 Lucent Technologies Inc. Molded encapsulated electronic component
US5793613A (en) * 1995-12-29 1998-08-11 Sgs-Thomson Microelectronics S.R.1. Heat-dissipating and supporting structure for a plastic package with a fully insulated heat sink for an electronic device
US5796159A (en) * 1995-11-30 1998-08-18 Analog Devices, Inc. Thermally efficient integrated circuit package
US5866953A (en) * 1996-05-24 1999-02-02 Micron Technology, Inc. Packaged die on PCB with heat sink encapsulant
US5891753A (en) * 1997-01-24 1999-04-06 Micron Technology, Inc. Method and apparatus for packaging flip chip bare die on printed circuit boards
US5893726A (en) * 1997-12-15 1999-04-13 Micron Technology, Inc. Semiconductor package with pre-fabricated cover and method of fabrication
US5920768A (en) * 1996-12-19 1999-07-06 Denso Corporation Manufacturing method for a resin sealed semiconductor device
US5928595A (en) * 1995-05-01 1999-07-27 Motorola, Inc. Method of manufacturing a semiconductor component
US5933713A (en) * 1998-04-06 1999-08-03 Micron Technology, Inc. Method of forming overmolded chip scale package and resulting product
US5938956A (en) * 1996-09-10 1999-08-17 Micron Technology, Inc. Circuit and method for heating an adhesive to package or rework a semiconductor die
US5942908A (en) * 1993-05-12 1999-08-24 Tribotech Apparatus for testing a nonpackaged die
US6013946A (en) * 1996-09-11 2000-01-11 Samsung Electronics Co., Ltd. Wire bond packages for semiconductor chips and related methods and assemblies
US6020629A (en) * 1998-06-05 2000-02-01 Micron Technology, Inc. Stacked semiconductor package and method of fabrication
US6020626A (en) * 1997-09-19 2000-02-01 Sony Corporation Semiconductor device
US6025728A (en) * 1997-04-25 2000-02-15 Micron Technology, Inc. Semiconductor package with wire bond protective member
US6028365A (en) * 1998-03-30 2000-02-22 Micron Technology, Inc. Integrated circuit package and method of fabrication
US6046496A (en) * 1997-11-04 2000-04-04 Micron Technology Inc Chip package
US6048744A (en) * 1997-09-15 2000-04-11 Micron Technology, Inc. Integrated circuit package alignment feature
US6048755A (en) * 1998-11-12 2000-04-11 Micron Technology, Inc. Method for fabricating BGA package using substrate with patterned solder mask open in die attach area
US6049125A (en) * 1997-12-29 2000-04-11 Micron Technology, Inc. Semiconductor package with heat sink and method of fabrication
US6054755A (en) * 1997-10-14 2000-04-25 Sumitomo Metal (Smi) Electronics Devices Inc. Semiconductor package with improved moisture vapor relief function and method of fabricating the same
US6066514A (en) * 1996-10-18 2000-05-23 Micron Technology, Inc. Adhesion enhanced semiconductor die for mold compound packaging
US6072236A (en) * 1996-03-07 2000-06-06 Micron Technology, Inc. Micromachined chip scale package
US6071758A (en) * 1995-11-14 2000-06-06 Sgs-Thomson Microelectronics S.A. Process for manufacturing a chip card micromodule with protection barriers
US6074897A (en) * 1996-05-01 2000-06-13 Lucent Technologies Inc. Integrated circuit bonding method and apparatus
US6075288A (en) * 1998-06-08 2000-06-13 Micron Technology, Inc. Semiconductor package having interlocking heat sinks and method of fabrication
US6089920A (en) * 1998-05-04 2000-07-18 Micron Technology, Inc. Modular die sockets with flexible interconnects for packaging bare semiconductor die
US6094058A (en) * 1991-06-04 2000-07-25 Micron Technology, Inc. Temporary semiconductor package having dense array external contacts
US6168970B1 (en) * 1990-08-01 2001-01-02 Staktek Group L.P. Ultra high density integrated circuit packages
US6172419B1 (en) * 1998-02-24 2001-01-09 Micron Technology, Inc. Low profile ball grid array package
US6175159B1 (en) * 1997-07-16 2001-01-16 Oki Electric Industry Co., Ltd. Semiconductor package
US6184465B1 (en) * 1998-11-12 2001-02-06 Micron Technology, Inc. Semiconductor package
US6191472B1 (en) * 1999-01-05 2001-02-20 Intel Corporation Hole geometry of a semiconductor package substrate
US6194778B1 (en) * 1996-08-16 2001-02-27 Sony Corporation Semiconductor package with improved cross talk and grounding, and method of manufacturing same
US6198172B1 (en) * 1997-02-20 2001-03-06 Micron Technology, Inc. Semiconductor chip package
US6208519B1 (en) * 1999-08-31 2001-03-27 Micron Technology, Inc. Thermally enhanced semiconductor package
US6210992B1 (en) * 1999-08-31 2001-04-03 Micron Technology, Inc. Controlling packaging encapsulant leakage
US6215175B1 (en) * 1998-07-06 2001-04-10 Micron Technology, Inc. Semiconductor package having metal foil die mounting plate
US6225687B1 (en) * 1999-09-02 2001-05-01 Intel Corporation Chip package with degassing holes
US6228687B1 (en) * 1999-06-28 2001-05-08 Micron Technology, Inc. Wafer-level package and methods of fabricating
US6229202B1 (en) * 2000-01-10 2001-05-08 Micron Technology, Inc. Semiconductor package having downset leadframe for reducing package bow
US6228548B1 (en) * 1998-02-27 2001-05-08 Micron Technology, Inc. Method of making a multichip semiconductor package
US6235994B1 (en) * 1998-06-29 2001-05-22 International Business Machines Corporation Thermal/electrical break for printed circuit boards
US6242802B1 (en) * 1995-07-17 2001-06-05 Motorola, Inc. Moisture enhanced ball grid array package
US6252298B1 (en) * 1997-06-18 2001-06-26 Samsung Electronics Co., Ltd. Semiconductor chip package using flexible circuit board with central opening
US6258623B1 (en) * 1998-08-21 2001-07-10 Micron Technology, Inc. Low profile multi-IC chip package connector
US6259153B1 (en) * 1998-08-20 2001-07-10 Micron Technology, Inc. Transverse hybrid LOC package
US6262480B1 (en) * 1996-06-28 2001-07-17 Sgs-Thomson Microelectronics S.R.L. Package for electronic device having a fully insulated dissipator
US6338813B1 (en) * 1999-10-15 2002-01-15 Advanced Semiconductor Engineering, Inc. Molding method for BGA semiconductor chip package
US6403009B1 (en) * 1994-11-15 2002-06-11 Vlt Corporation Circuit encapsulation
US6410981B2 (en) * 1997-10-24 2002-06-25 Nec Corporation Vented semiconductor device package having separate substrate, strengthening ring and cap structures
US6413801B1 (en) * 2000-05-02 2002-07-02 Advanced Semiconductor Engineering, Inc. Method of molding semiconductor device and molding die for use therein
US6559536B1 (en) * 1999-12-13 2003-05-06 Fujitsu Limited Semiconductor device having a heat spreading plate
US6589820B1 (en) * 2000-06-16 2003-07-08 Micron Technology, Inc. Method and apparatus for packaging a microelectronic die
US6838760B1 (en) * 2000-08-28 2005-01-04 Micron Technology, Inc. Packaged microelectronic devices with interconnecting units
US6982386B2 (en) * 2000-08-23 2006-01-03 Micron Technology, Inc. Interconnecting substrates for electrical coupling of microelectronic components
US7049685B2 (en) * 2000-08-24 2006-05-23 Micron Technology, Inc. Packaged microelectronic devices with pressure release elements and methods for manufacturing and using such packaged microelectronic devices

Family Cites Families (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US402638A (en) * 1889-05-07 Whiffletree
US36469A (en) * 1862-09-16 Improved sugar-evaporator
JPS60208847A (en) * 1984-04-02 1985-10-21 Oki Electric Ind Co Ltd Heat resisting plastic ic
JPS60257546A (en) 1984-06-04 1985-12-19 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
US4777520A (en) * 1986-03-27 1988-10-11 Oki Electric Industry Co. Ltd. Heat-resistant plastic semiconductor device
JPS62229949A (en) * 1986-03-31 1987-10-08 Oki Electric Ind Co Ltd Manufacture of resin-sealed semiconductor
IT1201836B (en) * 1986-07-17 1989-02-02 Sgs Microelettronica Spa SEMICONDUCTOR DEVICE MOUNTED IN A HIGHLY FLEXIBLE SEGMENTED CONTAINER AND PROVIDED WITH A THERMAL DISSIPATOR
US4882212A (en) 1986-10-30 1989-11-21 Olin Corporation Electronic packaging of components incorporating a ceramic-glass-metal composite
USRE36469E (en) 1988-09-30 1999-12-28 Micron Technology, Inc. Packaging for semiconductor logic devices
US5147821A (en) * 1990-09-28 1992-09-15 Motorola, Inc. Method for making a thermally enhanced semiconductor device by holding a leadframe against a heatsink through vacuum suction in a molding operation
FR2673017A1 (en) 1991-02-18 1992-08-21 Schlumberger Ind Sa METHOD FOR MANUFACTURING AN ELECTRONIC MODULE FOR A MEMORY CARD AND ELECTRONIC MODULE THUS OBTAINED.
US5946553A (en) 1991-06-04 1999-08-31 Micron Technology, Inc. Process for manufacturing a semiconductor package with bi-substrate die
US5815000A (en) 1991-06-04 1998-09-29 Micron Technology, Inc. Method for testing semiconductor dice with conventionally sized temporary packages
JPH05299536A (en) * 1992-04-17 1993-11-12 Oki Electric Ind Co Ltd Resin sealed semiconductor device
US5363280A (en) 1993-04-22 1994-11-08 International Business Machines Corporation Printed circuit board or card thermal mass design
US5474958A (en) * 1993-05-04 1995-12-12 Motorola, Inc. Method for making semiconductor device having no die supporting surface
TW222346B (en) 1993-05-17 1994-04-11 American Telephone & Telegraph Method for packaging an electronic device substrate in a plastic encapsulant
US5958100A (en) 1993-06-03 1999-09-28 Micron Technology, Inc. Process of making a glass semiconductor package
US5665281A (en) 1993-12-02 1997-09-09 Motorola, Inc. Method for molding using venting pin
US5665296A (en) 1994-03-24 1997-09-09 Intel Corporation Molding technique for molding plastic packages
US5964030A (en) 1994-06-10 1999-10-12 Vlsi Technology, Inc. Mold flow regulating dam ring
US6046076A (en) 1994-12-29 2000-04-04 Tessera, Inc. Vacuum dispense method for dispensing an encapsulant and machine therefor
US5976955A (en) 1995-01-04 1999-11-02 Micron Technology, Inc. Packaging for bare dice employing EMR-sensitive adhesives
US5677566A (en) 1995-05-08 1997-10-14 Micron Technology, Inc. Semiconductor chip package
US5696033A (en) 1995-08-16 1997-12-09 Micron Technology, Inc. Method for packaging a semiconductor die
US5842275A (en) 1995-09-05 1998-12-01 Ford Motor Company Reflow soldering to mounting pads with vent channels to avoid skewing
US5851845A (en) 1995-12-18 1998-12-22 Micron Technology, Inc. Process for packaging a semiconductor die using dicing and testing
US5817545A (en) 1996-01-24 1998-10-06 Cornell Research Foundation, Inc. Pressurized underfill encapsulation of integrated circuits
JPH1065043A (en) * 1996-08-13 1998-03-06 Sumitomo Kinzoku Electro Device:Kk Ball-grid array type package substrate and manufacture thereof
US6103547A (en) 1997-01-17 2000-08-15 Micron Technology, Inc. High speed IC package configuration
US6100598A (en) 1997-03-06 2000-08-08 Nippon Steel Semiconductor Corporation Sealed semiconductor device with positional deviation between upper and lower molds
USD402638S (en) 1997-04-25 1998-12-15 Micron Technology, Inc. Temporary package for semiconductor dice
US6159764A (en) 1997-07-02 2000-12-12 Micron Technology, Inc. Varied-thickness heat sink for integrated circuit (IC) packages and method of fabricating IC packages
US5986209A (en) 1997-07-09 1999-11-16 Micron Technology, Inc. Package stack via bottom leaded plastic (BLP) packaging
US6107122A (en) 1997-08-04 2000-08-22 Micron Technology, Inc. Direct die contact (DDC) semiconductor package
US6114189A (en) 1997-09-10 2000-09-05 Lsi Logic Corp. Molded array integrated circuit package
JPH11121488A (en) 1997-10-15 1999-04-30 Toshiba Corp Manufacture of semiconductor device and resin sealing device
US6097087A (en) 1997-10-31 2000-08-01 Micron Technology, Inc. Semiconductor package including flex circuit, interconnects and dense array external contacts
US5989941A (en) 1997-12-12 1999-11-23 Micron Technology, Inc. Encapsulated integrated circuit packaging
US5994784A (en) 1997-12-18 1999-11-30 Micron Technology, Inc. Die positioning in integrated circuit packaging
US6117382A (en) 1998-02-05 2000-09-12 Micron Technology, Inc. Method for encasing array packages
JP3481117B2 (en) * 1998-02-25 2003-12-22 富士通株式会社 Semiconductor device and manufacturing method thereof
US5938959A (en) * 1998-04-07 1999-08-17 Testrite Baparoma International Llc Oven with automatically movable shelf
US5990566A (en) 1998-05-20 1999-11-23 Micron Technology, Inc. High density semiconductor package
US6008070A (en) 1998-05-21 1999-12-28 Micron Technology, Inc. Wafer level fabrication and assembly of chip scale packages
US6277671B1 (en) 1998-10-20 2001-08-21 Micron Technology, Inc. Methods of forming integrated circuit packages
US6143581A (en) * 1999-02-22 2000-11-07 Micron Technology, Inc. Asymmetric transfer molding method and an asymmetric encapsulation made therefrom
US6189970B1 (en) * 1999-02-26 2001-02-20 Cosco Management, Inc. Harness for juvenile vehicle seat

Patent Citations (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3672046A (en) * 1970-01-14 1972-06-27 Technitrol Inc The method of making an electrical component
US4285780A (en) * 1978-11-02 1981-08-25 Schachter Herbert I Method of making a multi-level circuit board
US4855807A (en) * 1986-12-26 1989-08-08 Kabushiki Kaisha Toshiba Semiconductor device
US5208467A (en) * 1988-07-28 1993-05-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a film-covered packaged component
US5314842A (en) * 1988-09-30 1994-05-24 Kabushiki Kaisha Toshiba Resin-sealed type semiconductor device and method for manufacturing the same
US6168970B1 (en) * 1990-08-01 2001-01-02 Staktek Group L.P. Ultra high density integrated circuit packages
US5191174A (en) * 1990-08-01 1993-03-02 International Business Machines Corporation High density circuit board and method of making same
US5122858A (en) * 1990-09-10 1992-06-16 Olin Corporation Lead frame having polymer coated surface portions
US5105259A (en) * 1990-09-28 1992-04-14 Motorola, Inc. Thermally enhanced semiconductor device utilizing a vacuum to ultimately enhance thermal dissipation
US5138434A (en) * 1991-01-22 1992-08-11 Micron Technology, Inc. Packaging for semiconductor logic devices
US5107328A (en) * 1991-02-13 1992-04-21 Micron Technology, Inc. Packaging means for a semiconductor die having particular shelf structure
US6094058A (en) * 1991-06-04 2000-07-25 Micron Technology, Inc. Temporary semiconductor package having dense array external contacts
US5296738A (en) * 1991-07-08 1994-03-22 Motorola, Inc. Moisture relief for chip carrier
US5596231A (en) * 1991-08-05 1997-01-21 Asat, Limited High power dissipation plastic encapsulated package for integrated circuit die
US5128831A (en) * 1991-10-31 1992-07-07 Micron Technology, Inc. High-density electronic package comprising stacked sub-modules which are electrically interconnected by solder-filled vias
US5197183A (en) * 1991-11-05 1993-03-30 Lsi Logic Corporation Modified lead frame for reducing wire wash in transfer molding of IC packages
US5309026A (en) * 1991-11-19 1994-05-03 Nippon Precision Circuits Ltd. Integrated circuit package having stress reducing recesses
US5195023A (en) * 1991-12-23 1993-03-16 At&T Bell Laboratories Integrated circuit package with strain relief grooves
US5294835A (en) * 1992-07-28 1994-03-15 Nitto Denko Corporation Epoxy resin composition for semiconductor encapsulation and semiconductor device using the same
US5612576A (en) * 1992-10-13 1997-03-18 Motorola Self-opening vent hole in an overmolded semiconductor device
US5328079A (en) * 1993-03-19 1994-07-12 National Semiconductor Corporation Method of and arrangement for bond wire connecting together certain integrated circuit components
US5942908A (en) * 1993-05-12 1999-08-24 Tribotech Apparatus for testing a nonpackaged die
US5420460A (en) * 1993-08-05 1995-05-30 Vlsi Technology, Inc. Thin cavity down ball grid array package based on wirebond technology
US5527743A (en) * 1993-08-18 1996-06-18 Lsi Logic Corporation Method for encapsulating an integrated circuit package
US5593927A (en) * 1993-10-14 1997-01-14 Micron Technology, Inc. Method for packaging semiconductor dice
US5606204A (en) * 1994-06-23 1997-02-25 Nec Corporation Resin-sealed semiconductor device
US5635220A (en) * 1994-09-22 1997-06-03 Nec Corporation Molding die for sealing semiconductor device with reduced resin burrs
US5639695A (en) * 1994-11-02 1997-06-17 Motorola, Inc. Low-profile ball-grid array semiconductor package and method
US5728600A (en) * 1994-11-15 1998-03-17 Vlt Corporation Circuit encapsulation process
US6403009B1 (en) * 1994-11-15 2002-06-11 Vlt Corporation Circuit encapsulation
US5767568A (en) * 1994-12-09 1998-06-16 Sony Corporation Semiconductor device
US5917234A (en) * 1994-12-09 1999-06-29 Sony Corporation Semiconductor device
US5773322A (en) * 1995-05-01 1998-06-30 Lucent Technologies Inc. Molded encapsulated electronic component
US5928595A (en) * 1995-05-01 1999-07-27 Motorola, Inc. Method of manufacturing a semiconductor component
US5609889A (en) * 1995-05-26 1997-03-11 Hestia Technologies, Inc. Apparatus for encapsulating electronic packages
US5721450A (en) * 1995-06-12 1998-02-24 Motorola, Inc. Moisture relief for chip carriers
US6242802B1 (en) * 1995-07-17 2001-06-05 Motorola, Inc. Moisture enhanced ball grid array package
US5750423A (en) * 1995-08-25 1998-05-12 Dai-Ichi Seiko Co., Ltd. Method for encapsulation of semiconductor devices with resin and leadframe therefor
US5767446A (en) * 1995-10-27 1998-06-16 Anam Industrial Co., Ltd. Printed circuit board having epoxy barrier around a throughout slot and ball grid array semiconductor package
US6071758A (en) * 1995-11-14 2000-06-06 Sgs-Thomson Microelectronics S.A. Process for manufacturing a chip card micromodule with protection barriers
US5739585A (en) * 1995-11-27 1998-04-14 Micron Technology, Inc. Single piece package for semiconductor die
US5796159A (en) * 1995-11-30 1998-08-18 Analog Devices, Inc. Thermally efficient integrated circuit package
US5710071A (en) * 1995-12-04 1998-01-20 Motorola, Inc. Process for underfilling a flip-chip semiconductor device
US5766649A (en) * 1995-12-15 1998-06-16 Nec Corporation Resin sealing mold die set with less resin remainder for semiconductor device
US5793613A (en) * 1995-12-29 1998-08-11 Sgs-Thomson Microelectronics S.R.1. Heat-dissipating and supporting structure for a plastic package with a fully insulated heat sink for an electronic device
US6072236A (en) * 1996-03-07 2000-06-06 Micron Technology, Inc. Micromachined chip scale package
US6074897A (en) * 1996-05-01 2000-06-13 Lucent Technologies Inc. Integrated circuit bonding method and apparatus
US5866953A (en) * 1996-05-24 1999-02-02 Micron Technology, Inc. Packaged die on PCB with heat sink encapsulant
US6262480B1 (en) * 1996-06-28 2001-07-17 Sgs-Thomson Microelectronics S.R.L. Package for electronic device having a fully insulated dissipator
US6194778B1 (en) * 1996-08-16 2001-02-27 Sony Corporation Semiconductor package with improved cross talk and grounding, and method of manufacturing same
US5938956A (en) * 1996-09-10 1999-08-17 Micron Technology, Inc. Circuit and method for heating an adhesive to package or rework a semiconductor die
US6013946A (en) * 1996-09-11 2000-01-11 Samsung Electronics Co., Ltd. Wire bond packages for semiconductor chips and related methods and assemblies
US6066514A (en) * 1996-10-18 2000-05-23 Micron Technology, Inc. Adhesion enhanced semiconductor die for mold compound packaging
US5920768A (en) * 1996-12-19 1999-07-06 Denso Corporation Manufacturing method for a resin sealed semiconductor device
US5898224A (en) * 1997-01-24 1999-04-27 Micron Technology, Inc. Apparatus for packaging flip chip bare die on printed circuit boards
US5891753A (en) * 1997-01-24 1999-04-06 Micron Technology, Inc. Method and apparatus for packaging flip chip bare die on printed circuit boards
US6198172B1 (en) * 1997-02-20 2001-03-06 Micron Technology, Inc. Semiconductor chip package
US6025728A (en) * 1997-04-25 2000-02-15 Micron Technology, Inc. Semiconductor package with wire bond protective member
USD394844S (en) * 1997-04-25 1998-06-02 Micron Technology, Inc. Temporary package for semiconductor dice
US6252298B1 (en) * 1997-06-18 2001-06-26 Samsung Electronics Co., Ltd. Semiconductor chip package using flexible circuit board with central opening
US6175159B1 (en) * 1997-07-16 2001-01-16 Oki Electric Industry Co., Ltd. Semiconductor package
US6048744A (en) * 1997-09-15 2000-04-11 Micron Technology, Inc. Integrated circuit package alignment feature
US6246108B1 (en) * 1997-09-15 2001-06-12 Micron Technology, Inc. Integrated circuit package including lead frame with electrically isolated alignment feature
US6020626A (en) * 1997-09-19 2000-02-01 Sony Corporation Semiconductor device
US6054755A (en) * 1997-10-14 2000-04-25 Sumitomo Metal (Smi) Electronics Devices Inc. Semiconductor package with improved moisture vapor relief function and method of fabricating the same
US6410981B2 (en) * 1997-10-24 2002-06-25 Nec Corporation Vented semiconductor device package having separate substrate, strengthening ring and cap structures
US6046496A (en) * 1997-11-04 2000-04-04 Micron Technology Inc Chip package
US5893726A (en) * 1997-12-15 1999-04-13 Micron Technology, Inc. Semiconductor package with pre-fabricated cover and method of fabrication
US6049125A (en) * 1997-12-29 2000-04-11 Micron Technology, Inc. Semiconductor package with heat sink and method of fabrication
US6172419B1 (en) * 1998-02-24 2001-01-09 Micron Technology, Inc. Low profile ball grid array package
US6228548B1 (en) * 1998-02-27 2001-05-08 Micron Technology, Inc. Method of making a multichip semiconductor package
US6028365A (en) * 1998-03-30 2000-02-22 Micron Technology, Inc. Integrated circuit package and method of fabrication
US5933713A (en) * 1998-04-06 1999-08-03 Micron Technology, Inc. Method of forming overmolded chip scale package and resulting product
US6089920A (en) * 1998-05-04 2000-07-18 Micron Technology, Inc. Modular die sockets with flexible interconnects for packaging bare semiconductor die
US6020629A (en) * 1998-06-05 2000-02-01 Micron Technology, Inc. Stacked semiconductor package and method of fabrication
US6075288A (en) * 1998-06-08 2000-06-13 Micron Technology, Inc. Semiconductor package having interlocking heat sinks and method of fabrication
US6235994B1 (en) * 1998-06-29 2001-05-22 International Business Machines Corporation Thermal/electrical break for printed circuit boards
US6215175B1 (en) * 1998-07-06 2001-04-10 Micron Technology, Inc. Semiconductor package having metal foil die mounting plate
US6259153B1 (en) * 1998-08-20 2001-07-10 Micron Technology, Inc. Transverse hybrid LOC package
US6258623B1 (en) * 1998-08-21 2001-07-10 Micron Technology, Inc. Low profile multi-IC chip package connector
US6048755A (en) * 1998-11-12 2000-04-11 Micron Technology, Inc. Method for fabricating BGA package using substrate with patterned solder mask open in die attach area
US6184465B1 (en) * 1998-11-12 2001-02-06 Micron Technology, Inc. Semiconductor package
US6191472B1 (en) * 1999-01-05 2001-02-20 Intel Corporation Hole geometry of a semiconductor package substrate
US6228687B1 (en) * 1999-06-28 2001-05-08 Micron Technology, Inc. Wafer-level package and methods of fabricating
US6210992B1 (en) * 1999-08-31 2001-04-03 Micron Technology, Inc. Controlling packaging encapsulant leakage
US6208519B1 (en) * 1999-08-31 2001-03-27 Micron Technology, Inc. Thermally enhanced semiconductor package
US6225687B1 (en) * 1999-09-02 2001-05-01 Intel Corporation Chip package with degassing holes
US6338813B1 (en) * 1999-10-15 2002-01-15 Advanced Semiconductor Engineering, Inc. Molding method for BGA semiconductor chip package
US6559536B1 (en) * 1999-12-13 2003-05-06 Fujitsu Limited Semiconductor device having a heat spreading plate
US6258624B1 (en) * 2000-01-10 2001-07-10 Micron Technology, Inc. Semiconductor package having downset leadframe for reducing package bow
US6229202B1 (en) * 2000-01-10 2001-05-08 Micron Technology, Inc. Semiconductor package having downset leadframe for reducing package bow
US6413801B1 (en) * 2000-05-02 2002-07-02 Advanced Semiconductor Engineering, Inc. Method of molding semiconductor device and molding die for use therein
US6589820B1 (en) * 2000-06-16 2003-07-08 Micron Technology, Inc. Method and apparatus for packaging a microelectronic die
US6677675B2 (en) * 2000-06-16 2004-01-13 Micron Technology, Inc. Microelectronic devices and microelectronic die packages
US6683388B2 (en) * 2000-06-16 2004-01-27 Micron Technology, Inc. Method and apparatus for packaging a microelectronic die
US6982386B2 (en) * 2000-08-23 2006-01-03 Micron Technology, Inc. Interconnecting substrates for electrical coupling of microelectronic components
US6983551B2 (en) * 2000-08-23 2006-01-10 Micron Technology, Inc. Interconnecting substrates for electrical coupling of microelectronic components
US7049685B2 (en) * 2000-08-24 2006-05-23 Micron Technology, Inc. Packaged microelectronic devices with pressure release elements and methods for manufacturing and using such packaged microelectronic devices
US6838760B1 (en) * 2000-08-28 2005-01-04 Micron Technology, Inc. Packaged microelectronic devices with interconnecting units

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070007637A1 (en) * 2004-08-12 2007-01-11 Marinov Valery R Multi-layered substrate assembly with vialess electrical interconnect scheme
US20070045807A1 (en) * 2005-09-01 2007-03-01 Micron Technology, Inc. Microelectronic devices and methods for manufacturing microelectronic devices
US20080128900A1 (en) * 2006-12-04 2008-06-05 Micron Technology, Inc. Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
US7741150B2 (en) 2006-12-04 2010-06-22 Micron Technology, Inc. Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
US20100237510A1 (en) * 2006-12-04 2010-09-23 Micron Technology, Inc. Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
US8399971B2 (en) 2006-12-04 2013-03-19 Micron Technology, Inc. Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
US8900923B2 (en) 2006-12-04 2014-12-02 Micron Technology, Inc. Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
US9324676B2 (en) 2006-12-04 2016-04-26 Micron Technology, Inc. Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
US7833456B2 (en) 2007-02-23 2010-11-16 Micron Technology, Inc. Systems and methods for compressing an encapsulant adjacent a semiconductor workpiece

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