US20050122766A1 - Digital control logic circuit having a characteristic of time hysteresis - Google Patents

Digital control logic circuit having a characteristic of time hysteresis Download PDF

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Publication number
US20050122766A1
US20050122766A1 US11/032,201 US3220105A US2005122766A1 US 20050122766 A1 US20050122766 A1 US 20050122766A1 US 3220105 A US3220105 A US 3220105A US 2005122766 A1 US2005122766 A1 US 2005122766A1
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time hysteresis
time
input signal
transits
characteristic
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US11/032,201
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Sang Yoon
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SK Hynix Inc
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Hynix Semiconductor Inc
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation

Definitions

  • the present invention relates to a control logic circuit having a characteristic of time hysteresis in a semiconductor memory device, and more particularly to a control logic circuit having a characteristic of time hysteresis when the signals transit from “1” to “0” and from “0” to “1” by connecting two time hysteresis circuits in series.
  • a digital control logic circuit in a semiconductor memory device generates a glitch (short pulse) during delay time as it passes through a delay unit.
  • a time hysteresis circuit is used for eliminating such a glitch.
  • the time hysteresis circuit has a characteristic of time hysteresis, and the characteristic of time hysteresis controls transition of a digital control signal for a predetermined time when the digital control signal transits from “1” to “0” or from “0” to “1”. Such characteristic of time hysteresis may eliminate the glitch possibly generated in an output signal when the input signal transits.
  • FIG. 1 is a diagram showing a conventional time hysteresis circuit.
  • the conventional time hysteresis circuit comprises latch 1 , delay unit 2 and inverter I 1 .
  • the latch 1 comprising two NAND gates ND 1 and ND 2 receives an input signal A(t) and an output signal from the delay unit 2 , and outputs an output signal B(t) after latching for a predetermined time.
  • the inverter I 1 inverts the output signal B(t) and the delay unit 2 delays an inversion of the output signal B(t) from the inverter I 1 for a delay time “td”.
  • the conventional time hysteresis circuit outputs the output signal B(t) after eliminating the glitch generated when the input signal A(t) transits from “1” to “0”.
  • the delay unit 2 transmits the inversion of the output signal B(t) to the latch 1 after delaying it for the delay time “td”.
  • the latch 1 latches the input signal A(t) to “1”.
  • time hysteresis does not appear when input signal A(t) transits from “0” to “1”.
  • FIG. 2 is a diagram showing waveforms of signals in the conventional time hysteresis circuit.
  • the time hysteresis circuit in FIG. 2 outputs the output signal B(t) with the glitch eliminated when the input signal A(t) transits from “1” to “0”. However, if the input signal A(t) transits from “0” to “1”, it will output the output signal B(t) with the glitch not being eliminated.
  • the conventional time hysteresis circuit shows a problem to have only one-way characteristic of time hysteresis wherein the input signal A(t) transits from “1” to “0” or from “0” to “1”.
  • control logic circuit having a characteristic of time hysteresis when an input signal transits not only from “1” to “0” but also from “0” to “1” by comprising two time hysteresis circuits in series.
  • a digital control logic circuit having a characteristic of time hysteresis for controlling transition of a digital control signal for a predetermined period, the digital control logic circuit comprising a first time hysteresis unit, a second time hysteresis unit.
  • the first time has the characteristic of time hysteresis when an input signal transits from a first level to a second level.
  • the second time hysteresis unit connected in series to the first hysteresis has the characteristic of time hysteresis when the input signal transits from the second level to the first level.
  • FIG. 1 is a diagram showing a conventional time hysteresis circuit.
  • FIG. 2 is a diagram showing waveforms of signals in the conventional time hysteresis circuit.
  • FIG. 3 is a diagram showing the conventional time hysteresis circuit according to a first embodiment of the present invention.
  • FIG. 4 is a diagram showing waveforms of signals in time hysteresis circuit in FIG. 3 .
  • FIG. 5 is a simulation diagram according to time hysteresis circuit in FIG. 3 .
  • FIG. 6 is a diagram showing time hysteresis circuit according to a second embodiment of the present invention.
  • FIG. 7 illustrates the operation of a state machine in FIG. 6 .
  • FIG. 8 is a diagram showing waveforms of signals according to time hysteresis circuit in FIG. 6 .
  • FIG. 3 is a diagram illustrating time hysteresis circuit according to a first embodiment of the present invention.
  • the time hysteresis circuit in FIG. 3 comprises two time hysteresis units 30 , 31 connected in series and an inverter 12 to output terminal of the time hysteresis unit 31 .
  • the time hysteresis unit 30 which receives the input signal A(t) delays it for the delay time “td 1 ”, and then outputs the output signal B(t).
  • the time hysteresis unit 31 receives the output signal B(t) and delays it for the delay time “td 2 ”.
  • the inverter 12 inverts an output signal from the time hysteresis unit 31 and outputs an output signal C(t). According to the status of the output signal C(t), the inverter I 2 may be preferably incorporated into the time hysteresis circuit.
  • the internal configurations of the time hysteresis units 30 , 31 may be designed as shown in FIG. 1 . Accordingly, the operating relationship will be described in detail without explanation on the internal configurations.
  • the time hysteresis unit 30 outputs the output signal B(t) after eliminating the glitch generated when the input signal A(t) transits from “1” to “0”, and the time hysteresis unit 31 outputs the output signal C(t) after eliminating the glitch generated when the input signal A(t) transits from “0” to “1”.
  • the delay time “td 2 ” should be longer than delay time “td 1 ” such that the time hysteresis unit 31 may eliminate glitches delayed for the delay time “td 1 ” of the output signal B(t).
  • delay time “td 2 ” of the time hysteresis unit 31 be longer than the delay time “td 1 ” of time hysteresis unit 30 , and preferably, double the delay time “td 1 ”.
  • the present invention has a characteristic of bi-directional time hysteresis, wherein the time hysteresis unit 30 and the time hysteresis unit 31 are connected in series such that the time hysteresis unit 30 eliminates the glitch generated when the input signal A(t) transits from “1” to “0”, and the time hysteresis unit 31 eliminates the glitch generated when the input signal A(t) transits from “0” to “1”.
  • FIG. 4 is a diagram illustrating waveforms of signals in FIG. 3 .
  • the output signal B(t) is output after the glitch is eliminated by time hysteresis unit 30 .
  • the time hysteresis unit 31 When the input signal A(t) transits from “0” to “1”, the time hysteresis unit 31 outputs the output signal C(t) wherein the glitch is eliminated.
  • FIG. 5 is a graph illustrating the result of simulation of time hysteresis circuits in FIG. 3 . It can be seen that the result of the real simulation is the same as that of FIG. 4 .
  • FIG. 6 is a diagram illustrating time hysteresis circuit according a second embodiment of the present invention.
  • the time hysteresis circuit comprising delay unit 60 and state machine 61 receives the input signal A(t) and outputs an output signal D(t).
  • the delay unit 60 delays the input signal A(t) for the delay time “td 3 ”, and outputs the delayed signal A(t-td 3 ).
  • the state machine 61 receives the input signal A(t) and the delayed signal A(t-td 3 ) from the delay unit 60 , and output the out put signal D(t). At this time, the state machine 61 changes the state according to the transition of the input signal A(t) and the delayed signal A(t-td 3 ).
  • the state machine 61 is desirable to be configured with two SR-latches (not shown) or to be embodied with two D-flip flops (not shown).
  • FIG. 7 is a diagram for illustrating the operation of the state machine 61 In FIG. 6 .
  • the state machine 61 uses two input signals A(t), A(t-td 3 ) and has four states S0, S1, S3, S3.
  • the State machine 61 transits from an initial state S3 to state S0 outputting T0 value when the input signal A(t) transits from “1” to “0”. Then, the state machine 61 transits from state S0 to state S1 outputting T1 value at the moment when the delayed signal A(t-td 3 ) becomes “0” from “1”.
  • state machine 61 transits from state S1 to state S2 outputting T2 value when the input signal A(t) transits from “0” to “1”. Finally, the state machine 61 transits to from state S2 to state S3 outputting T3 value when the delayed signal A(t-td 3 ) transits from “0” to “1”.
  • the state machine 61 may adjust the values T0-T3 to output any desired the output D(t). That is to say, a circuit may be embodied which has various characteristic of hysteresis by changing the output values of the state machine 61 .
  • the output signal D(t) has an opposite status to the input signal A(t) and is output without glitches generated when the input signal A(t) transits from “1” to “0” of from “0” to “1”.
  • a digital control logic circuit having a characteristic of time hysteresis has an advantage of minimizing glitches generated from both transitional periods when the digital control signal transits from “1” to “0” and when it transits from “0” to “1”.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

The present invention discloses a digital control logic circuit having a characteristic of time hysteresis for controlling transition of a digital control signal for a predetermined period, comprising a first time hysteresis unit, a second time hysteresis unit and an inverter. The first time has the characteristic of time hysteresis when an input signal transits from a first level to a second level. The second time hysteresis unit has the characteristic of time hysteresis connected to the first hysteresis in series when the input signal transits from the second level to the first level.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a control logic circuit having a characteristic of time hysteresis in a semiconductor memory device, and more particularly to a control logic circuit having a characteristic of time hysteresis when the signals transit from “1” to “0” and from “0” to “1” by connecting two time hysteresis circuits in series.
  • 2. Description of the Prior Art
  • In general, a digital control logic circuit in a semiconductor memory device generates a glitch (short pulse) during delay time as it passes through a delay unit. A time hysteresis circuit is used for eliminating such a glitch.
  • The time hysteresis circuit has a characteristic of time hysteresis, and the characteristic of time hysteresis controls transition of a digital control signal for a predetermined time when the digital control signal transits from “1” to “0” or from “0” to “1”. Such characteristic of time hysteresis may eliminate the glitch possibly generated in an output signal when the input signal transits.
  • FIG. 1 is a diagram showing a conventional time hysteresis circuit.
  • The conventional time hysteresis circuit comprises latch 1, delay unit 2 and inverter I1.
  • The latch 1 comprising two NAND gates ND1 and ND2 receives an input signal A(t) and an output signal from the delay unit 2, and outputs an output signal B(t) after latching for a predetermined time. The inverter I1 inverts the output signal B(t) and the delay unit 2 delays an inversion of the output signal B(t) from the inverter I1 for a delay time “td”.
  • The conventional time hysteresis circuit outputs the output signal B(t) after eliminating the glitch generated when the input signal A(t) transits from “1” to “0”. In other words, the delay unit 2 transmits the inversion of the output signal B(t) to the latch 1 after delaying it for the delay time “td”. The latch 1 latches the input signal A(t) to “1”. However, such characteristic of time hysteresis does not appear when input signal A(t) transits from “0” to “1”.
  • FIG. 2 is a diagram showing waveforms of signals in the conventional time hysteresis circuit.
  • The time hysteresis circuit in FIG. 2 outputs the output signal B(t) with the glitch eliminated when the input signal A(t) transits from “1” to “0”. However, if the input signal A(t) transits from “0” to “1”, it will output the output signal B(t) with the glitch not being eliminated.
  • As a result, the conventional time hysteresis circuit shows a problem to have only one-way characteristic of time hysteresis wherein the input signal A(t) transits from “1” to “0” or from “0” to “1”.
    • SUMMARY OF THE INVENTION
  • Accordingly, it is an object of the present invention to provide a control logic circuit having a characteristic of time hysteresis when an input signal transits not only from “1” to “0” but also from “0” to “1” by comprising two time hysteresis circuits in series.
  • It is another object of the present invention to provide a control logic circuit having the characteristic of time hysteresis by comprising a time state machine when the input signal transits from “1” to “0” and/or from “0” to “1”.
  • In an embodiment, there is provided a digital control logic circuit having a characteristic of time hysteresis for controlling transition of a digital control signal for a predetermined period, the digital control logic circuit comprising a first time hysteresis unit, a second time hysteresis unit. The first time has the characteristic of time hysteresis when an input signal transits from a first level to a second level. The second time hysteresis unit connected in series to the first hysteresis has the characteristic of time hysteresis when the input signal transits from the second level to the first level.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a diagram showing a conventional time hysteresis circuit.
  • FIG. 2 is a diagram showing waveforms of signals in the conventional time hysteresis circuit.
  • FIG. 3 is a diagram showing the conventional time hysteresis circuit according to a first embodiment of the present invention.
  • FIG. 4 is a diagram showing waveforms of signals in time hysteresis circuit in FIG. 3.
  • FIG. 5 is a simulation diagram according to time hysteresis circuit in FIG. 3.
  • FIG. 6 is a diagram showing time hysteresis circuit according to a second embodiment of the present invention.
  • FIG. 7 illustrates the operation of a state machine in FIG. 6.
  • FIG. 8 is a diagram showing waveforms of signals according to time hysteresis circuit in FIG. 6.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Hereinafter, the embodiments of the present invention will be described in detail with reference to the accompanying drawings.
  • FIG. 3 is a diagram illustrating time hysteresis circuit according to a first embodiment of the present invention. The time hysteresis circuit in FIG. 3 comprises two time hysteresis units 30, 31 connected in series and an inverter 12 to output terminal of the time hysteresis unit 31.
  • The time hysteresis unit 30 which receives the input signal A(t) delays it for the delay time “td1”, and then outputs the output signal B(t). The time hysteresis unit 31 receives the output signal B(t) and delays it for the delay time “td2”. The inverter 12 inverts an output signal from the time hysteresis unit 31 and outputs an output signal C(t). According to the status of the output signal C(t), the inverter I2 may be preferably incorporated into the time hysteresis circuit.
  • Here, the internal configurations of the time hysteresis units 30, 31, respectively, may be designed as shown in FIG. 1. Accordingly, the operating relationship will be described in detail without explanation on the internal configurations.
  • The time hysteresis unit 30 outputs the output signal B(t) after eliminating the glitch generated when the input signal A(t) transits from “1” to “0”, and the time hysteresis unit 31 outputs the output signal C(t) after eliminating the glitch generated when the input signal A(t) transits from “0” to “1”.
  • There are two cases when the input signal A(t) transits from “1” to “0” and when the input signal A(t) transits from “0” to “1”. When the input signal A(t) transits from “1” to “0”, the glitch may be first eliminated by the time hysteresis unit 30.
  • However, additional glitches can be generated when B(t) transits from “1” to “0” during the delay time of “td1” in the time hysteresis unit 30. In order to eliminate the glitches additionally generated when the output signal B(t) transits from “1” to “0”, the time hysteresis unit 31 should be connected to output terminal of the time hysteresis unit 30.
  • If the input signal A(t) transits from “0” to “1”, the delay time “td2” should be longer than delay time “td1” such that the time hysteresis unit 31 may eliminate glitches delayed for the delay time “td1” of the output signal B(t).
  • In other words, it is desirable that delay time “td2” of the time hysteresis unit 31 be longer than the delay time “td1” of time hysteresis unit 30, and preferably, double the delay time “td1”.
  • As described above, the present invention has a characteristic of bi-directional time hysteresis, wherein the time hysteresis unit 30 and the time hysteresis unit 31 are connected in series such that the time hysteresis unit 30 eliminates the glitch generated when the input signal A(t) transits from “1” to “0”, and the time hysteresis unit 31 eliminates the glitch generated when the input signal A(t) transits from “0” to “1”.
  • FIG. 4 is a diagram illustrating waveforms of signals in FIG. 3.
  • As previously explained, when the input signal A(t) transits from “1” to “0”, the output signal B(t) is output after the glitch is eliminated by time hysteresis unit 30.
  • When the input signal A(t) transits from “0” to “1”, the time hysteresis unit 31 outputs the output signal C(t) wherein the glitch is eliminated.
  • As a result, it can be achieved in the present invention to output the output signal C(t) without any glitch for both cases when the input signal A(t) transits from “1” to “0” and when the input signal A(t) transits from “0” to “1”.
  • FIG. 5 is a graph illustrating the result of simulation of time hysteresis circuits in FIG. 3. It can be seen that the result of the real simulation is the same as that of FIG. 4.
  • FIG. 6 is a diagram illustrating time hysteresis circuit according a second embodiment of the present invention.
  • The time hysteresis circuit comprising delay unit 60 and state machine 61 receives the input signal A(t) and outputs an output signal D(t).
  • The delay unit 60 delays the input signal A(t) for the delay time “td3”, and outputs the delayed signal A(t-td3).
  • The state machine 61 receives the input signal A(t) and the delayed signal A(t-td3) from the delay unit 60, and output the out put signal D(t). At this time, the state machine 61 changes the state according to the transition of the input signal A(t) and the delayed signal A(t-td3).
  • The state machine 61 is desirable to be configured with two SR-latches (not shown) or to be embodied with two D-flip flops (not shown).
  • FIG. 7 is a diagram for illustrating the operation of the state machine 61 In FIG. 6.
  • The state machine 61 uses two input signals A(t), A(t-td3) and has four states S0, S1, S3, S3.
  • The State machine 61 transits from an initial state S3 to state S0 outputting T0 value when the input signal A(t) transits from “1” to “0”. Then, the state machine 61 transits from state S0 to state S1 outputting T1 value at the moment when the delayed signal A(t-td3) becomes “0” from “1”.
  • Thereafter, the state machine 61 transits from state S1 to state S2 outputting T2 value when the input signal A(t) transits from “0” to “1”. Finally, the state machine 61 transits to from state S2 to state S3 outputting T3 value when the delayed signal A(t-td3) transits from “0” to “1”.
  • As described above, the state machine 61 may adjust the values T0-T3 to output any desired the output D(t). That is to say, a circuit may be embodied which has various characteristic of hysteresis by changing the output values of the state machine 61.
  • FIG. 8 illustrates examples when the output values of state machine are T0=0, T1=1, T2=1 and T3=0.
  • When the input signal A(t) transits from “1” to “0” or from “0” to “1”, the glitch may be generated. The delay signal A(t-td3) is delayed as much as “td3”, and thus the glitch is generated the same as generated in the input signal A(t).
  • The output signal D(t) has an opposite status to the input signal A(t) and is output without glitches generated when the input signal A(t) transits from “1” to “0” of from “0” to “1”.
  • Accordingly, the present invention may eliminate glitches generated from transition of digital control signals as much as possible.
  • As discussed earlier, a digital control logic circuit having a characteristic of time hysteresis according to the present invention has an advantage of minimizing glitches generated from both transitional periods when the digital control signal transits from “1” to “0” and when it transits from “0” to “1”.
  • In addition, it has an advantage to embody a circuit having various characteristics of hysteresises by comprising a state machine.

Claims (4)

1-5. (canceled)
6. A digital control logic circuit having a characteristic of time hysteresis, comprising:
a delay unit for delaying an input signal; and
a state machine for receiving the input signal and an output signal from the delay unit, having an output value determined under control of the transition state, and adjusting its state according to the output value to have a characteristic of time hysteresis for both cases when the input signal transits from low level to high level and when the input signal transits from high level to low level.
7. The circuit according to claim 6, wherein the state machine is a 2 bit state machine.
8. (canceled)
US11/032,201 2002-12-30 2005-01-11 Digital control logic circuit having a characteristic of time hysteresis Abandoned US20050122766A1 (en)

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US10/608,569 US6842060B2 (en) 2002-12-30 2003-06-30 Digital control logic circuit having a characteristic of time hysteresis
US11/032,201 US20050122766A1 (en) 2002-12-30 2005-01-11 Digital control logic circuit having a characteristic of time hysteresis

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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5184032A (en) * 1991-04-25 1993-02-02 Texas Instruments Incorporated Glitch reduction in integrated circuits, systems and methods
US5563893A (en) * 1994-02-14 1996-10-08 Hewlett-Packard Company Integrated level detector
US5594361A (en) * 1994-05-10 1997-01-14 Integrated Device Technology, Inc. Logic gate with controllable hysteresis and high frequency voltage controlled oscillator
US5604452A (en) * 1995-04-03 1997-02-18 Exar Corporation Clock generator using a state machine to switch between two offset clocks
US6060926A (en) * 1998-02-01 2000-05-09 American Meter Company Pulse conditioning circuit
US6078634A (en) * 1993-10-08 2000-06-20 Texas Instruments Incorporated Phase-locked loop circuit with a multi-cycle phase detector and multi-current charge pump
US6377083B1 (en) * 2000-05-25 2002-04-23 Tsutomu Takabayashi Semiconductor integrated device and methods of detecting and correcting a voltage drop in an integrated circuit
US6388488B1 (en) * 2000-11-02 2002-05-14 National Semiconductor Corporation Schmitt trigger with hysteresis and previous-state memory
US6433602B1 (en) * 2000-08-30 2002-08-13 Lattice Semiconductor Corp. High speed Schmitt Trigger with low supply voltage

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH098612A (en) * 1995-06-16 1997-01-10 Nec Corp Latch circuit

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5184032A (en) * 1991-04-25 1993-02-02 Texas Instruments Incorporated Glitch reduction in integrated circuits, systems and methods
US6078634A (en) * 1993-10-08 2000-06-20 Texas Instruments Incorporated Phase-locked loop circuit with a multi-cycle phase detector and multi-current charge pump
US5563893A (en) * 1994-02-14 1996-10-08 Hewlett-Packard Company Integrated level detector
US5594361A (en) * 1994-05-10 1997-01-14 Integrated Device Technology, Inc. Logic gate with controllable hysteresis and high frequency voltage controlled oscillator
US5604452A (en) * 1995-04-03 1997-02-18 Exar Corporation Clock generator using a state machine to switch between two offset clocks
US6060926A (en) * 1998-02-01 2000-05-09 American Meter Company Pulse conditioning circuit
US6377083B1 (en) * 2000-05-25 2002-04-23 Tsutomu Takabayashi Semiconductor integrated device and methods of detecting and correcting a voltage drop in an integrated circuit
US6433602B1 (en) * 2000-08-30 2002-08-13 Lattice Semiconductor Corp. High speed Schmitt Trigger with low supply voltage
US6388488B1 (en) * 2000-11-02 2002-05-14 National Semiconductor Corporation Schmitt trigger with hysteresis and previous-state memory

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KR100516712B1 (en) 2005-09-22
KR20040060166A (en) 2004-07-06
US6842060B2 (en) 2005-01-11
US20040124897A1 (en) 2004-07-01

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