US20050031057A1 - Method for automatic gain control, for instance in a telecommunication system, device and computer program product therefor - Google Patents
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- US20050031057A1 US20050031057A1 US10/888,088 US88808804A US2005031057A1 US 20050031057 A1 US20050031057 A1 US 20050031057A1 US 88808804 A US88808804 A US 88808804A US 2005031057 A1 US2005031057 A1 US 2005031057A1
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- 238000004590 computer program Methods 0.000 title description 2
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- 238000009825 accumulation Methods 0.000 description 3
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3052—Automatic control in amplifiers having semiconductor devices in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3036—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/18—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
- H03M1/181—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values
- H03M1/183—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values the feedback signal controlling the gain of an amplifier or attenuator preceding the analogue/digital converter
- H03M1/185—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values the feedback signal controlling the gain of an amplifier or attenuator preceding the analogue/digital converter the determination of the range being based on more than one digital output value, e.g. on a running average, a power estimation or the rate of change
Definitions
- the present invention relates to techniques for automatic gain control (AGC), and more particularly, to an automatic gain control of signals received in a mobile telecommunication system.
- AGC automatic gain control
- Exemplary telecommunication systems are those systems based on the CDMA (Code Division Multiple Access) technique, and in the following, reference will primarily be made to CDMA systems. However, this is not to be construed in a limiting sense, and the present invention is applicable to a wide variety of telecommunication systems including but not limited to satellite telecommunications systems and terrestrial mobile telecommunication systems operating according to the GSM, UMTS, CDMA2000, IS95 and WBCDMA standards.
- CDMA Code Division Multiple Access
- the received signal envelope may exhibit a very large dynamic range.
- a gain control is therefore required in the receiver to adjust the signal amplitude at the input of the analog-to-digital converter (ADC).
- the automatic gain control should control the signal amplitude to avoid or limit saturation of the analog-to-digital converter, and at the same time, ensure an efficient exploitation of the ADC dynamic range.
- the AGC loop adjustment is based on the measurement of the received signal power. This measurement can be effected directly at the RF unit or after (i.e., downstream) the ADC.
- the signal level is adjusted by multiplying the signal itself by a proper scale factor. This scale factor is calculated by measuring the received signal power over a certain interval.
- FIG. 1 a simplified block diagram of an AGC loop according to the prior art is shown.
- Such an AGC loop is designated by the reference numeral 10 and receives an input signal S in , which corresponds to the received signal, as well as a reference digital signal P ref that is indicative of a reference power level.
- the reference power signal P ref is fed to a summation node 11 along with a measured power signal P meas .
- the measured power signal P meas is added with a negative sign (i.e., subtracted) from the reference digital power signal P ref to obtain an error signal P err .
- the error signal P err is fed into a loop filter 12 with a transfer function F(z) that usually involves a FIR (Finite Impulse Response) filter, a gain factor and an integrator.
- the filter 12 produces a filtered error signal P f , which is multiplied in a multiplying node 13 by the input signal S in .
- the output of the multiplying node 13 is sent to an analog-to-digital converter 14 that produces a digital output signal x(t) comprising a controlled output signal S out of the loop 10 .
- the controlled output signal S out is also transmitted over a feedback branch back to the summing node 11 .
- the feedback branch includes a power measurement block 15 , which measures the power of the output signal S out , thus generating the measured power signal P meas that is fed back to the summation node 11 .
- the power measurement block 15 usually performs squaring and averaging operations over a certain time interval of the controlled output signal S out to obtain the above mentioned scale factor for multiplying the input signal S in .
- the reference digital power signal P ref can be regarded as a steady state signal exempt from disturbances, whereas the power variations of the input signal S in can be regarded as a source of disturbances.
- the loop shown in FIG. 1 performs a direct measurement of the power of the received signal. Such a direct measurement is, however, quite expensive in terms of required hardware resources and power consumption involved.
- An object of the present invention is to provide an arrangement that reduces the cost of the hardware resources required for automatic gain control and the power consumption at the receiver.
- the present invention is achieved by a method for the automatic gain control in telecommunication systems having the characteristics set forth in the claims that follow.
- the invention also relates to a corresponding receiver, as well as to a computer program product directly loadable in the memory of a digital computer and comprising software code portions for performing the method when the product is run on a computer.
- the present invention provides for an indirect estimation of the power of the received signal, which is obtained through the measurement of a threshold crossing rate of the received signal.
- the present invention reduces the hardware resource and the supply power requirements at the receiver.
- FIG. 1 is a block diagram of a receiver adapted for implementing an automatic gain control according to the prior art
- FIG. 2 is a block diagram of a receiver adapted for implementing an automatic gain control according to the present invention
- FIG. 3 schematically illustrates in greater detail the power measurement block as shown in FIG. 2 ;
- FIG. 4 schematically details an alternative embodiment of the power measurement block circuit as shown in FIG. 3 .
- the basic idea underlying the arrangement described herein is to measure over a given observation window the number of times the absolute value of the signal at the output of the analog-to-digital converter is above a certain threshold. Such a measurement provides an indirect estimate of the power of the received signal, which is then compared to a reference value (power set-point) to obtain the loop error signal.
- the error signal is used to drive a variable gain amplifier to control the amplitude of the signal at the input of the analog-to-digital converter.
- the variable gain amplifier has an exponential characteristic.
- the illustrated AGC loop 20 receives at its two inputs the input signal S in that corresponds to the received signal, and the reference power value Pref that is preferably expressed in dB.
- the reference digital power signal P ref is fed to the summation node 11 along with the measured power signal P meas .
- the measured power signal P meas is subtracted from the reference digital power signal P ref to obtain the error signal P err .
- the error signal P err is then fed into a loop filter 22 .
- the filtered error signal P f from the loop filter 22 is sent as a control signal to a variable gain amplifier 23 that receives at its input the input signal S in .
- the gain of the variable gain amplifier 23 is thus set by the value of the filtered error signal P f .
- the output of the variable gain amplifier 23 is then sent to the analog-to-digital converter 14 that supplies the controlled output signal S out to the output of the AGC loop 20 and to the feedback branch.
- the feedback branch comprises a power measurement block 25 .
- This in turn includes a module 27 for estimating the threshold crossing rate of the power of the controlled output signal S out .
- the module 27 is associated with a module for calculating the power value from the threshold crossing rate, indicated by reference 29 .
- a linear-to-logarithm (dB) conversion block 26 is arranged to ensure a uniform behavior over a large operating range.
- the values of the variable ⁇ are representative of the crossings of the threshold T h by the signal x(t) at the output of the analog-to-digital converter 14 .
- This operation can be implemented by accumulating over a given time window a number N of values of the variable ⁇ in the module 27 for estimating the threshold crossing rate.
- the function ierfc(E( ⁇ )) can be obtained simply by a look up table (LUT) without having to perform a difficult analytical or numerical calculation. This will be shown with reference to FIG. 3 , and results in a small number of values within a small, limited range.
- the look up table also takes into account the squaring and division operations required by equation (6).
- the final behavior of the AGC loop 20 depends on the actual setting of a number of parameters, in particular, parameters like the digital reference power P ref , the power threshold T h used for the crossing-rate measurement, a loop operating frequency f s , and a loop gain K G .
- K G the loop gain
- the dynamic range of the analog-to-digital converter 14 should be taken into account.
- such a range is set to [ ⁇ 2, 2] and the analog-to-digital converter 14 has a unitary gain.
- fine tuning may be needed to optimize performance in a number of different fading conditions.
- the loop operating frequency f s is chosen equal to 1.5 KHz (i.e., the slot rate of the received signal in the UMTS/WCDMA standard). As shown above, the frequency response of a first order loop is already quite satisfactory. For this reason no additional loop filters have been introduced.
- the AGC loop 20 is actually required to compensate only power variations of the received signal due to slow fading. Consequently, the loop bandwidth is set to 15 Hz which corresponds to a loop gain K G value of 0.07 (eq. 7).
- the AGC loop 20 is able to significantly compensate the slow power variations over the channel, and is almost not sensitive to fast variations.
- FIG. 3 an embodiment of the power measurement block 25 is shown.
- the digital output signal x(t) from the analog-to-digital converter 14 is input to the module 27 for estimating the threshold crossing rate. Specifically, this is done via two threshold comparators 21 and 22 , operating on the I-channel and the Q-channel of the output signal x(t), respectively.
- a logic circuit is provided downstream of the summation node 24 .
- This logic circuit includes a first data register 34 followed by a second data register 36 .
- a control circuit 33 controls a reset input RST of the first data register 34 and an enable input EN of the second data register 36 .
- the output of the data register 34 is fed to the data register 36 and to the summing node 24 . This is done to accumulate the values of the variable ⁇ up to the moment the control circuit 33 enables feeding the accumulated value through the data register 36 to a look up table that embodies the module for calculating the power value from the threshold crossing rate 29 .
- the logic circuit also performs under the control of the control circuit 33 a division by 2N, to evaluate the crossing rate or the estimator.
- a look up table 29 contains the values of the inverse of function f single .
- the threshold crossing rate is used to extract from the look up table 29 the value of the relative estimated power expressed in dB.
- the observation window may be chosen to be equal to 38400 for example, and the threshold T h set to half of the single-sided output range of the analog-to-digital converter 14 .
- Such a choice of the threshold value has the additional advantage of requiring a very simple comparator since only the 2 most significant bits of the digital output x(t) are required to detect the threshold crossing event.
- the accumulation result may be mapped onto the power values in the look up table 29 differently according to the degree of accuracy selected.
- the result of the accumulation is divided by 1024.
- an integer value in the range [0, 75] is obtained at the input of the look up table 29 .
- the estimated power is given as the output.
- the conversion to the logarithmic domain can be included in the look-up-table in such a way that the look-up table 29 and the a linear-to-logarithmic conversion block 26 results in a single physical component
- multiple threshold comparisons can be adopted, to improve performance in terms of estimation mean square error. This can be obtained by adding a moderate amount of complexity to the basic circuitry.
- T h1 , T h2 , T h3 the thresholds may in fact be any number.
- T h1 , T h2 , T h3 can be easily obtained by applying equation (2).
- E ( ⁇ ) corresponds to the multilevel function f Multi :
- E( ⁇ ) an accumulation of N values of the variable ⁇ , E( ⁇ ) is obtained as:
- ⁇ 2 f Multi ⁇ 1 (E( ⁇ )) (12)
- the power measurement block 35 comprises a module for estimating the threshold crossing rate 37 by using two multilevel comparators 31 and 32 for the I channel and the Q channel of the signal x(t), respectively.
- the power measurement block 35 is then substantially identical to the block 25 for the single threshold method shown in FIG. 3 , with the exception of a look up table 39 that implements the inverse of multi-threshold function f Multi from equation (12). However, the look up table 39 has the same size as the look up table 29 for the single threshold.
- the functions implemented in the look-up tables 29 and 39 are significantly non-linear. It is thus advisable to use a non-uniform quantization on the x axis to minimize hardware complexity. This may be done while applying a uniform quantization on the y axis.
- circuit complexity and hardware requirements at the receiver are significantly reduced due to absence of any multipliers. Savings on the order of 55% of the chip area in the single threshold case, and 30% in the multi-threshold case can be achieved in comparison with the conventional implementation, as shown for instance in FIG. 1 . Such a reduction also involves a reduction in power consumption at the receiver.
- Receivers implementing the automatic gain control method described exhibit undistorted estimation even in the presence of strong saturation at the output of the analog-to-digital converter.
- devices different from the illustrated variable gain amplifier may be used for mixing the received signal with the error signal in the AGC loop.
- Any device/circuit adapted to scale the received signal on the basis of a proportionality relationship to the error signal and/or the measured power may be used for that purpose.
- the primary field of application of the arrangement disclosed herein are for devices where the gain of an incoming signal is to be controlled.
- a typical case is for receivers in mobile telecommunications systems, such as receivers for satellite and terrestrial mobile telecommunications systems according to the GSM, UMTS, CDMA2000, IS95 and WBCDMA standards, for example.
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Abstract
Description
- The present invention relates to techniques for automatic gain control (AGC), and more particularly, to an automatic gain control of signals received in a mobile telecommunication system.
- Exemplary telecommunication systems are those systems based on the CDMA (Code Division Multiple Access) technique, and in the following, reference will primarily be made to CDMA systems. However, this is not to be construed in a limiting sense, and the present invention is applicable to a wide variety of telecommunication systems including but not limited to satellite telecommunications systems and terrestrial mobile telecommunication systems operating according to the GSM, UMTS, CDMA2000, IS95 and WBCDMA standards.
- In a mobile telecommunication system the received signal envelope may exhibit a very large dynamic range. A gain control is therefore required in the receiver to adjust the signal amplitude at the input of the analog-to-digital converter (ADC). The automatic gain control should control the signal amplitude to avoid or limit saturation of the analog-to-digital converter, and at the same time, ensure an efficient exploitation of the ADC dynamic range.
- As reported in the standard technical literature, the AGC loop adjustment is based on the measurement of the received signal power. This measurement can be effected directly at the RF unit or after (i.e., downstream) the ADC. In a classical AGC implementation, the signal level is adjusted by multiplying the signal itself by a proper scale factor. This scale factor is calculated by measuring the received signal power over a certain interval.
- In
FIG. 1 a simplified block diagram of an AGC loop according to the prior art is shown. Such an AGC loop is designated by thereference numeral 10 and receives an input signal Sin, which corresponds to the received signal, as well as a reference digital signal Pref that is indicative of a reference power level. - The reference power signal Pref is fed to a
summation node 11 along with a measured power signal Pmeas. In thesummation node 11 the measured power signal Pmeas is added with a negative sign (i.e., subtracted) from the reference digital power signal Pref to obtain an error signal Perr. The error signal Perr is fed into aloop filter 12 with a transfer function F(z) that usually involves a FIR (Finite Impulse Response) filter, a gain factor and an integrator. Thefilter 12 produces a filtered error signal Pf, which is multiplied in amultiplying node 13 by the input signal Sin. - The output of the
multiplying node 13 is sent to an analog-to-digital converter 14 that produces a digital output signal x(t) comprising a controlled output signal Sout of theloop 10. The controlled output signal Sout is also transmitted over a feedback branch back to thesumming node 11. The feedback branch includes apower measurement block 15, which measures the power of the output signal Sout, thus generating the measured power signal Pmeas that is fed back to thesummation node 11. Thepower measurement block 15 usually performs squaring and averaging operations over a certain time interval of the controlled output signal Sout to obtain the above mentioned scale factor for multiplying the input signal Sin. - The reference digital power signal Pref can be regarded as a steady state signal exempt from disturbances, whereas the power variations of the input signal Sin can be regarded as a source of disturbances. The loop shown in
FIG. 1 performs a direct measurement of the power of the received signal. Such a direct measurement is, however, quite expensive in terms of required hardware resources and power consumption involved. - An object of the present invention is to provide an arrangement that reduces the cost of the hardware resources required for automatic gain control and the power consumption at the receiver.
- According to the present invention, this object is achieved by a method for the automatic gain control in telecommunication systems having the characteristics set forth in the claims that follow. The invention also relates to a corresponding receiver, as well as to a computer program product directly loadable in the memory of a digital computer and comprising software code portions for performing the method when the product is run on a computer.
- Substantially, the present invention provides for an indirect estimation of the power of the received signal, which is obtained through the measurement of a threshold crossing rate of the received signal. In comparison with prior art arrangements, the present invention reduces the hardware resource and the supply power requirements at the receiver.
- The present invention will now be described, purely by way of a non-limiting example, with reference to the annexed drawings, wherein:
-
FIG. 1 is a block diagram of a receiver adapted for implementing an automatic gain control according to the prior art; -
FIG. 2 is a block diagram of a receiver adapted for implementing an automatic gain control according to the present invention; -
FIG. 3 schematically illustrates in greater detail the power measurement block as shown inFIG. 2 ; and -
FIG. 4 schematically details an alternative embodiment of the power measurement block circuit as shown inFIG. 3 . - The basic idea underlying the arrangement described herein is to measure over a given observation window the number of times the absolute value of the signal at the output of the analog-to-digital converter is above a certain threshold. Such a measurement provides an indirect estimate of the power of the received signal, which is then compared to a reference value (power set-point) to obtain the loop error signal. The error signal, properly scaled and filtered, is used to drive a variable gain amplifier to control the amplitude of the signal at the input of the analog-to-digital converter. The variable gain amplifier has an exponential characteristic.
- In
FIG. 2 , the blocks and elements that perform the same functions as those included in theAGC loop 10 described with reference toFIG. 1 are indicated by the same reference numbers. The illustratedAGC loop 20 receives at its two inputs the input signal Sin that corresponds to the received signal, and the reference power value Pref that is preferably expressed in dB. - The reference digital power signal Pref is fed to the
summation node 11 along with the measured power signal Pmeas. In thesummation node 11 the measured power signal Pmeas is subtracted from the reference digital power signal Pref to obtain the error signal Perr. The error signal Perr is then fed into aloop filter 22. The filtered error signal Pf from theloop filter 22 is sent as a control signal to avariable gain amplifier 23 that receives at its input the input signal Sin. - The gain of the
variable gain amplifier 23 is thus set by the value of the filtered error signal Pf. The output of thevariable gain amplifier 23 is then sent to the analog-to-digital converter 14 that supplies the controlled output signal Sout to the output of theAGC loop 20 and to the feedback branch. - The feedback branch comprises a
power measurement block 25. This in turn includes amodule 27 for estimating the threshold crossing rate of the power of the controlled output signal Sout. Themodule 27 is associated with a module for calculating the power value from the threshold crossing rate, indicated byreference 29. Downstream of themodule 29, a linear-to-logarithm (dB)conversion block 26 is arranged to ensure a uniform behavior over a large operating range. - As previously indicated, x(t) denotes the digital output process of the analog-to-
digital converter 14, and is then defined as a discrete random variable:
Th indicates a power threshold value. - Thus, the values of the variable β are representative of the crossings of the threshold Th by the signal x(t) at the output of the analog-to-
digital converter 14. The overflow probability P, i.e., the probability for the variable β to be equal to 1, which means an overflow of the analog-to-digital converter 14 with respect to the threshold Th, can be expressed as:
where σ2 indicates the variance (i.e., the power) of the signal x(t). - Indicating with E(β) the statistical expectation of the variable β, i.e.,:
the variance σ2 can be obtained by the measurement of the expectation E(β). - This operation can be implemented by accumulating over a given time window a number N of values of the variable β in the
module 27 for estimating the threshold crossing rate. An estimator indicated by χ is thus obtained that substantially represents the crossing rate in the chosen observation window:
The statistical expectation E(χ) of the estimator χ is:
where fsingle indicates a single threshold function binding the variance σ2 to the estimator χ, as opposed to a multi-threshold function fMulti that will be described below. - Thus, inversion of the single level function fsingle, (i.e., inverting the complementary error function erfc), yields:
{acute over (σ)}2 corresponds to the measurement of the power of the signal x(t). - Due to the range of expectation E(χ), namely [0,1] being the same as the input value of the inverse error function ierfc in the
power measure block 25, the function ierfc(E(χ)) can be obtained simply by a look up table (LUT) without having to perform a difficult analytical or numerical calculation. This will be shown with reference toFIG. 3 , and results in a small number of values within a small, limited range. The look up table also takes into account the squaring and division operations required by equation (6). - The final behavior of the
AGC loop 20 depends on the actual setting of a number of parameters, in particular, parameters like the digital reference power Pref, the power threshold Th used for the crossing-rate measurement, a loop operating frequency fs, and a loop gain KG. - It can be demonstrated that the
AGC loop 20 behaves essentially like a first order high-pass filter with a normalized cut-off frequency fhp:
Thus, by setting the loop gain KG value it is possible to obtain a given bandwidth. To set the digital reference power Pref level, the dynamic range of the analog-to-digital converter 14 should be taken into account. - In the embodiment described herein such a range is set to [−2, 2] and the analog-to-
digital converter 14 has a unitary gain. This means that the output range will be in the interval [−2, 2] with a fractional quantization step depending on the word size. An acceptable value for the saturation rate of the ADC is about 5%, which corresponds to a variance σ2=1, as it can be derived from equation 3. The value selected for the digital reference power is then Pref=0 dB (on each component). However, fine tuning may be needed to optimize performance in a number of different fading conditions. - The center point of the single side dynamic range, i.e., for a threshold value Th=1, is chosen as the value of the threshold. The loop operating frequency fs is chosen equal to 1.5 KHz (i.e., the slot rate of the received signal in the UMTS/WCDMA standard). As shown above, the frequency response of a first order loop is already quite satisfactory. For this reason no additional loop filters have been introduced.
- The
AGC loop 20 is actually required to compensate only power variations of the received signal due to slow fading. Consequently, the loop bandwidth is set to 15 Hz which corresponds to a loop gain KG value of 0.07 (eq. 7). In this way, for the chosen value of the loop gain KG, the oscillations of the input power, in dB, are reduced by a factor of about 9×10−2 at a frequency fs*10−3 (1.5 Hz @ fs=1.5 KHz) and by a factor of about 7×10−1 at a frequency fs*10−2 (15 Hz @ fs=1.5 KHz). - The
AGC loop 20 is able to significantly compensate the slow power variations over the channel, and is almost not sensitive to fast variations. InFIG. 3 an embodiment of thepower measurement block 25 is shown. The digital output signal x(t) from the analog-to-digital converter 14 is input to themodule 27 for estimating the threshold crossing rate. Specifically, this is done via twothreshold comparators - The results of the two comparisons performed at the
threshold comparators summation node 24. To accumulate over the chosen observation window, i.e., N times, the results from thecomparators summation node 24. This logic circuit includes afirst data register 34 followed by asecond data register 36. Acontrol circuit 33 controls a reset input RST of the first data register 34 and an enable input EN of thesecond data register 36. The output of the data register 34 is fed to the data register 36 and to the summingnode 24. This is done to accumulate the values of the variable β up to the moment thecontrol circuit 33 enables feeding the accumulated value through the data register 36 to a look up table that embodies the module for calculating the power value from thethreshold crossing rate 29. - The logic circuit also performs under the control of the control circuit 33 a division by 2N, to evaluate the crossing rate or the estimator. Such a look up table 29 contains the values of the inverse of function fsingle. The threshold crossing rate is used to extract from the look up table 29 the value of the relative estimated power expressed in dB.
- The observation window may be chosen to be equal to 38400 for example, and the threshold Th set to half of the single-sided output range of the analog-to-
digital converter 14. Such a choice of the threshold value has the additional advantage of requiring a very simple comparator since only the 2 most significant bits of the digital output x(t) are required to detect the threshold crossing event. - The accumulation result may be mapped onto the power values in the look up table 29 differently according to the degree of accuracy selected. In a simple case (uniform quantization with 75 points), the result of the accumulation is divided by 1024. In this way, at the input of the look up table 29 an integer value in the range [0, 75] is obtained. For each one of these values the estimated power is given as the output. For a more efficient implementation, the conversion to the logarithmic domain can be included in the look-up-table in such a way that the look-up table 29 and the a linear-to-
logarithmic conversion block 26 results in a single physical component - In an alternative embodiment, as shown in
FIG. 4 , multiple threshold comparisons can be adopted, to improve performance in terms of estimation mean square error. This can be obtained by adding a moderate amount of complexity to the basic circuitry. - In the following the case is detailed of three thresholds of increasing values Th1, Th2, Th3,. Those of skill in the art will promptly appreciate that the thresholds may in fact be any number. The discrete variable β is defined as:
Overflow probabilities with respect to each of the three thresholds, Th1, Th2, Th3 can be easily obtained by applying equation (2). - In this case, the statistical expectation E (β) corresponds to the multilevel function fMulti:
By applying the same procedure already described for the single threshold method, an accumulation of N values of the variable β, E(χ) is obtained as:
and, using χ as an estimator of σ2:
σ2=fMulti −1(E(χ)) (12) - This is implemented through a
power measurement block 35, as shown inFIG. 4 . Thepower measurement block 35 comprises a module for estimating thethreshold crossing rate 37 by using twomultilevel comparators - The
power measurement block 35 is then substantially identical to theblock 25 for the single threshold method shown inFIG. 3 , with the exception of a look up table 39 that implements the inverse of multi-threshold function fMulti from equation (12). However, the look up table 39 has the same size as the look up table 29 for the single threshold. - The functions implemented in the look-up tables 29 and 39 are significantly non-linear. It is thus advisable to use a non-uniform quantization on the x axis to minimize hardware complexity. This may be done while applying a uniform quantization on the y axis.
- The arrangements disclosed herein permit remarkable advantages to be obtained over the known approaches. Circuit complexity and hardware requirements at the receiver are significantly reduced due to absence of any multipliers. Savings on the order of 55% of the chip area in the single threshold case, and 30% in the multi-threshold case can be achieved in comparison with the conventional implementation, as shown for instance in
FIG. 1 . Such a reduction also involves a reduction in power consumption at the receiver. - Receivers implementing the automatic gain control method described exhibit undistorted estimation even in the presence of strong saturation at the output of the analog-to-digital converter. Without prejudice to the underlying principle of the invention, the details and embodiment may vary, also significantly, with respect to what has been discussed just by way of example without departing from the scope of the invention, and as defined by the claims that follow.
- For instance, devices different from the illustrated variable gain amplifier may be used for mixing the received signal with the error signal in the AGC loop. Any device/circuit adapted to scale the received signal on the basis of a proportionality relationship to the error signal and/or the measured power may be used for that purpose.
- The primary field of application of the arrangement disclosed herein are for devices where the gain of an incoming signal is to be controlled. A typical case is for receivers in mobile telecommunications systems, such as receivers for satellite and terrestrial mobile telecommunications systems according to the GSM, UMTS, CDMA2000, IS95 and WBCDMA standards, for example.
Claims (39)
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Application Number | Priority Date | Filing Date | Title |
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EP03354064.2 | 2003-07-15 | ||
EP03354064A EP1499014B1 (en) | 2003-07-15 | 2003-07-15 | A method for automatic gain control, for instance in a telecommunication system, device and computer program therefor |
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US20050031057A1 true US20050031057A1 (en) | 2005-02-10 |
US7447283B2 US7447283B2 (en) | 2008-11-04 |
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US10/888,088 Active 2026-04-17 US7447283B2 (en) | 2003-07-15 | 2004-07-09 | Method for automatic gain control, for instance in a telecommunication system, device and computer program product therefor |
Country Status (3)
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US (1) | US7447283B2 (en) |
EP (1) | EP1499014B1 (en) |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100034327A1 (en) * | 2008-08-05 | 2010-02-11 | Qualcomm Incorporated | Joint time-frequency automatic gain control for wireless communication |
US20100329321A1 (en) * | 2009-06-30 | 2010-12-30 | Stmicroelectronics S.R.L. | Electronic device for receiving a radio-frequency signal |
WO2011068489A1 (en) * | 2009-12-01 | 2011-06-09 | Thomson Licensing | Software wideband automatic gain control |
WO2013017070A1 (en) * | 2011-08-02 | 2013-02-07 | 京信通信系统(中国)有限公司 | Digital automatic gain control method and system |
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US6314278B1 (en) * | 1998-12-30 | 2001-11-06 | Uniden America Corporation | Adjusting gain in a receiver using received signal sample values |
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IT1190872B (en) * | 1982-06-17 | 1988-02-24 | Sgs Microelettronica Spa | AUDIO AMPLIFICATION SYSTEM WITH INCREASE IN THE AVERAGE LISTENING POWER |
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- 2003-07-15 DE DE60331728T patent/DE60331728D1/en not_active Expired - Lifetime
- 2003-07-15 EP EP03354064A patent/EP1499014B1/en not_active Expired - Lifetime
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2004
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US5563916A (en) * | 1995-06-05 | 1996-10-08 | Hitachi America, Ltd. | Apparatus and method for varying the slew rate of a digital automatic gain control circuit |
US6229858B1 (en) * | 1996-12-09 | 2001-05-08 | Raytheon Company | Phaselock threshold correction |
US6324387B1 (en) * | 1998-12-29 | 2001-11-27 | Philips Electronics N.A. Corp. | LNA control-circuit for receive closed loop automatic gain control |
US6314278B1 (en) * | 1998-12-30 | 2001-11-06 | Uniden America Corporation | Adjusting gain in a receiver using received signal sample values |
US6668027B1 (en) * | 1999-03-02 | 2003-12-23 | Hitachi America, Ltd. | Self adjusting automatic gain control (AGC) power reference level circuit |
US6744838B1 (en) * | 2000-08-24 | 2004-06-01 | National Semiconductor Corporation | PLL lock detector |
US20020187765A1 (en) * | 2001-04-02 | 2002-12-12 | Itran Communications Ltd. | Dynamic automatic gain control circuit employing kalman filtering |
US7076379B2 (en) * | 2001-12-29 | 2006-07-11 | Lg Electronics Inc. | Method of estimating doppler frequency shift and method of transmitting data using the same |
Cited By (6)
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US20100034327A1 (en) * | 2008-08-05 | 2010-02-11 | Qualcomm Incorporated | Joint time-frequency automatic gain control for wireless communication |
US8548105B2 (en) * | 2008-08-05 | 2013-10-01 | Qualcomm Incorported | Joint time-frequency automatic gain control for wireless communication |
US20100329321A1 (en) * | 2009-06-30 | 2010-12-30 | Stmicroelectronics S.R.L. | Electronic device for receiving a radio-frequency signal |
US8582702B2 (en) | 2009-06-30 | 2013-11-12 | Stmicroelectronics S.R.L. | Electronic device for receiving a radio-frequency signal |
WO2011068489A1 (en) * | 2009-12-01 | 2011-06-09 | Thomson Licensing | Software wideband automatic gain control |
WO2013017070A1 (en) * | 2011-08-02 | 2013-02-07 | 京信通信系统(中国)有限公司 | Digital automatic gain control method and system |
Also Published As
Publication number | Publication date |
---|---|
EP1499014B1 (en) | 2010-03-17 |
US7447283B2 (en) | 2008-11-04 |
EP1499014A1 (en) | 2005-01-19 |
DE60331728D1 (en) | 2010-04-29 |
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