TWI847479B - Overlay measurement element and operating method thereof - Google Patents
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Abstract
Description
本揭露是有關一種疊對量測元件及一種疊對量測元件的操作方法。The present disclosure relates to a stacked measurement element and an operating method of the stacked measurement element.
一般而言,積體電路晶片的內部電路包括各種半導體元件,如二極體、電晶體、電容器和其他元件,半導體元件透過製程相互連接以製作不同的晶片。在晶片的製程中,堆疊層之間的重疊位移(overlay shift)會影響晶圓的良率,因此對晶圓實施的疊對量測(overlay measurement)十分重要。Generally speaking, the internal circuit of an integrated circuit chip includes various semiconductor components, such as diodes, transistors, capacitors and other components. The semiconductor components are interconnected through the process to produce different chips. In the chip manufacturing process, the overlay shift between the stacking layers will affect the wafer yield, so the overlay measurement performed on the wafer is very important.
目前的疊對量測通常使用光或者電子束作為量測訊號,包括基於光學影像之疊對(image-based overlay ,IBO) 量測、基於光學繞射之疊對(diffraction-based overlay,DBO)量測與需使用臨界尺寸掃描式電子顯微鏡(critical dimension scanning electron microscope,CD-SEM)的晶粒內疊對(in-die overlay)量測。Current overlay metrology usually uses light or electron beam as the measurement signal, including image-based overlay (IBO) measurement, diffraction-based overlay (DBO) measurement, and in-die overlay measurement that requires the use of a critical dimension scanning electron microscope (CD-SEM).
本揭露之一技術態樣為一種疊對量測元件的操作方法。One technical aspect of the present disclosure is an operating method of a stacked measurement element.
根據本揭露之一些實施方式,一種疊對量測元件的操作方法包括量測通過在第一導電層上的第二導電層的第一區段、第一導電層與第二導電層的第二區段的第一電流,其中第一導電層位於第一絕緣層中,第二導電層位於第二絕緣層中,第一區段的底面接觸第一導電層及第一絕緣層的第一部分;量測通過第二導電層的第三區段、第一導電層與第二導電層的第四區段的第二電流,其中第四區段的底面接觸第一導電層及第一絕緣層的第二部分,第一絕緣層的第一部分與第二部分分別位於第一導電層的相對兩側;比較第一電流與第二電流以判斷第一導電層的中心線與第二導電層的對稱線是否重疊。According to some embodiments of the present disclosure, a method for operating a stacked measuring element includes measuring a first current passing through a first section of a second conductive layer on a first conductive layer, and a second section of the first conductive layer and the second conductive layer, wherein the first conductive layer is located in a first insulating layer, the second conductive layer is located in the second insulating layer, and a bottom surface of the first section contacts the first conductive layer and a first portion of the first insulating layer; measuring A second current passes through the third section of the second conductive layer, the first conductive layer, and the fourth section of the second conductive layer, wherein the bottom surface of the fourth section contacts the first conductive layer and the second portion of the first insulating layer, and the first portion and the second portion of the first insulating layer are respectively located at opposite sides of the first conductive layer; the first current is compared with the second current to determine whether the center line of the first conductive layer and the symmetry line of the second conductive layer overlap.
在一些實施方式中,上述疊對量測元件的操作方法更包括當第一電流等於第二電流時,第一導電層的中心線與第二導電層的對稱線重疊。In some implementations, the method for operating the stacked measurement element further includes overlapping a center line of the first conductive layer and a symmetric line of the second conductive layer when the first current is equal to the second current.
在一些實施方式中,當上述第一導電層的中心線與第二導電層的對稱線重疊時,第二導電層的第一區段與第一導電層之間的第一接觸面積等於第二導電層的第四區段與第一導電層之間的第二接觸面積。In some embodiments, when the center line of the first conductive layer overlaps with the symmetry line of the second conductive layer, a first contact area between the first segment of the second conductive layer and the first conductive layer is equal to a second contact area between the fourth segment of the second conductive layer and the first conductive layer.
在一些實施方式中,上述疊對量測元件的操作方法更包括當第一電流大於第二電流時,第二導電層的對稱線在第一導電層的中心線右側而分開一距離。In some implementations, the operating method of the stacked measurement element further includes that when the first current is greater than the second current, the symmetry lines of the second conductive layer are separated by a distance on the right side of the center line of the first conductive layer.
在一些實施方式中,當上述第二導電層的對稱線在第一導電層的中心線右側而分開一距離時,第二導電層的第一區段與第一導電層之間的第一接觸面積大於第二導電層的第四區段與第一導電層之間的第二接觸面積。In some embodiments, when the symmetry lines of the second conductive layer are separated by a distance to the right of the center line of the first conductive layer, a first contact area between the first segment of the second conductive layer and the first conductive layer is larger than a second contact area between the fourth segment of the second conductive layer and the first conductive layer.
在一些實施方式中,上述疊對量測元件的操作方法更包括當第一電流小於第二電流時,第二導電層的對稱線在第一導電層的中心線左側而分開一距離。In some implementations, the operating method of the stacked measurement element further includes that when the first current is less than the second current, the symmetry lines of the second conductive layer are separated by a distance on the left side of the center line of the first conductive layer.
在一些實施方式中,當上述第二導電層的對稱線在第一導電層的中心線左側而分開一距離時,第二導電層的第一區段與第一導電層之間的第一接觸面積小於第二導電層的第四區段與第一導電層之間的第二接觸面積。In some embodiments, when the symmetry lines of the second conductive layer are separated by a distance to the left of the center line of the first conductive layer, a first contact area between the first segment of the second conductive layer and the first conductive layer is smaller than a second contact area between the fourth segment of the second conductive layer and the first conductive layer.
在一些實施方式中,上述疊對量測元件的操作方法更包括在量測通過在第一導電層上的第二導電層的第一區段、第一導電層與第二導電層的第二區段的第一電流時,施加偏壓於第二導電層的第一區段與第二區段;以及在量測通過第二導電層的第三區段、第一導電層與第二導電層的第四區段的第二電流時,施加上述偏壓於第二導電層的第四區段與第三區段。In some embodiments, the operating method of the stacked measuring element further includes applying a bias to the first segment and the second segment of the second conductive layer when measuring a first current passing through a first segment of the second conductive layer on the first conductive layer, and the first conductive layer and the second segment of the second conductive layer; and applying the above-mentioned bias to the fourth segment and the third segment of the second conductive layer when measuring a second current passing through a third segment of the second conductive layer, and the first conductive layer and the fourth segment of the second conductive layer.
本揭露之另一技術態樣為一種疊對量測元件。Another technical aspect of the present disclosure is a stacked measurement element.
根據本揭露之一些實施方式,一種疊對量測元件包括半導體基板、第一導電層、第一絕緣層、第二導電層與第二絕緣層。半導體基板具有切割道。第一導電層位於半導體基板的切割道上。第一絕緣層位於半導體基板的切割道上。第一絕緣層圍繞第一導電層,且具有分別在第一導電層相對兩側的第一部分與第二部分。第二導電層位於第一導電層上,且依序具有第一區段、第二區段、第三區段與第四區段。第一區段的底面接觸第一導電層與第一絕緣層的第一部分。第四區段的底面接觸第一導電層與第一絕緣層的第二部分。第一區段、第二區段、第三區段與第四區段具有對稱線,第一區段及第二區段分別與第四區段及第三區段沿對稱線對稱。第一區段、第二區段、第三區段與第四區段的每一者具有相同的底面積。第二絕緣層位於第一導電層與第一絕緣層上,且圍繞第二導電層。According to some embodiments of the present disclosure, a stacked measurement element includes a semiconductor substrate, a first conductive layer, a first insulating layer, a second conductive layer and a second insulating layer. The semiconductor substrate has a cutting path. The first conductive layer is located on the cutting path of the semiconductor substrate. The first insulating layer is located on the cutting path of the semiconductor substrate. The first insulating layer surrounds the first conductive layer and has a first portion and a second portion respectively on opposite sides of the first conductive layer. The second conductive layer is located on the first conductive layer and has a first section, a second section, a third section and a fourth section in sequence. The bottom surface of the first section contacts the first conductive layer and the first portion of the first insulating layer. The bottom surface of the fourth segment contacts the first conductive layer and the second portion of the first insulating layer. The first segment, the second segment, the third segment and the fourth segment have a symmetry line, and the first segment and the second segment are symmetric with the fourth segment and the third segment respectively along the symmetry line. Each of the first segment, the second segment, the third segment and the fourth segment has the same bottom area. The second insulating layer is located on the first conductive layer and the first insulating layer, and surrounds the second conductive layer.
在一些實施方式中,上述第二導電層的第一區段與第二區段之間及第三區段與第四區段之間具有相同的第一間距,第二導電層更具有複數個第五區段,第五區段位於第二區段與第三區段之間,第五區段相鄰兩者之間的距離為第一間距或與第一間距不同的第二間距。In some embodiments, the first segment and the second segment and the third segment and the fourth segment of the second conductive layer have the same first distance, and the second conductive layer further has a plurality of fifth segments, the fifth segment is located between the second segment and the third segment, and the distance between two adjacent fifth segments is the first distance or a second distance different from the first distance.
在一些實施方式中,上述第二導電層的第一區段、第二區段、第三區段與第四區段每一者具有分開的複數個部分,部分的相鄰兩者之間的距離相同,且部分的俯視形狀為矩形或圓形。In some embodiments, each of the first segment, the second segment, the third segment, and the fourth segment of the second conductive layer has a plurality of separated parts, the distance between two adjacent parts is the same, and the top view shape of the parts is rectangular or circular.
在本揭露上述實施方式中,由於疊對量測元件的操作方法包括比較第一電流與第二電流以判斷第一導電層的中心線與第二導電層的對稱線是否重疊,因此使用上述操作方法的疊對量測(overlay measurement)是基於疊對量測元件的電性,而非使用光或者電子束作為量測訊號,與傳統基於光學影像之疊對(image-based overlay ,IBO) 量測、基於光學繞射之疊對(diffraction-based overlay,DBO)量測與需使用臨界尺寸掃描式電子顯微鏡(critical dimension scanning electron microscope,CD-SEM)的晶粒內疊對(in-die overlay)量測不同,可不受光或電子束訊號的限制。In the above-mentioned embodiments of the present disclosure, since the operation method of the overlay measurement element includes comparing the first current and the second current to determine whether the center line of the first conductive layer and the symmetry line of the second conductive layer overlap, the overlay measurement using the above-mentioned operation method is based on the electrical properties of the overlay measurement element, rather than using light or electron beam as the measurement signal. Different from the traditional image-based overlay (IBO) measurement, the diffraction-based overlay (DBO) measurement and the in-die overlay measurement that requires the use of a critical dimension scanning electron microscope (CD-SEM), the overlay measurement is not limited by the light or electron beam signal.
以下揭示之實施方式內容提供了用於實施所提供的標的之不同特徵的許多不同實施方式,或實例。下文描述了元件和佈置之特定實例以簡化本案。當然,該等實例僅為實例且並不意欲作為限制。此外,本案可在各個實例中重複元件符號及/或字母。此重複係用於簡便和清晰的目的,且其本身不指定所論述的各個實施方式及/或配置之間的關係。The embodiments disclosed below provide many different embodiments, or examples, for implementing the different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these examples are only examples and are not intended to be limiting. In addition, the present invention may repeat component symbols and/or letters in each example. This repetition is for the purpose of simplicity and clarity, and does not itself specify the relationship between the various embodiments and/or configurations discussed.
諸如「在……下方」、「在……之下」、「下部」、「在……之上」、「上部」等等空間相對術語可在本文中為了便於描述之目的而使用,以描述如附圖中所示之一個元件或特徵與另一元件或特徵之關係。空間相對術語意欲涵蓋除了附圖中所示的定向之外的在使用或操作中的裝置的不同定向。裝置可經其他方式定向(旋轉90度或以其他定向)並且本文所使用的空間相對描述詞可同樣相應地解釋。Spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein for descriptive purposes to describe the relationship of one element or feature to another element or feature as illustrated in the accompanying figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
第1圖繪示根據本揭露一實施方式之疊對量測元件的操作方法的流程圖。第2圖至第4圖繪示根據本揭露一實施方式之疊對量測元件100的操作方法在不同情況下之疊對量測元件100的剖面圖。同時參閱第1圖與第2圖,疊對量測元件(例如第2圖的疊對量測元件100)的操作方法包括以下流程。在步驟S1時,量測通過在第一導電層120上的第二導電層140的第一區段141、第一導電層120與第二導電層140的第二區段142的第一電流I1。第一導電層120位於第一絕緣層130中。第二導電層140位於第二絕緣層150中。第一區段141的底面接觸第一導電層120及第一絕緣層130的第一部分131。接著,在步驟S2時,量測通過第二導電層140的第三區段143、第一導電層120與第二導電層140的第四區段144的第二電流I2。第四區段144的底面接觸第一導電層120及第一絕緣層130的第二部分132。第一絕緣層130的第一部分131與第二部分132分別位於第一導電層120的相對兩側。之後,在步驟S3時,比較第一電流I1與第二電流I2以判斷第一導電層120的中心線L1與第二導電層140的對稱線L2是否重疊。FIG. 1 is a flow chart showing an operation method of a stacked measurement element according to an embodiment of the present disclosure. FIG. 2 to FIG. 4 are cross-sectional views of the
由於疊對量測元件100的操作方法包括比較第一電流I1與第二電流I2以判斷第一導電層120的中心線L1與第二導電層140的對稱線L2是否重疊,因此使用上述操作方法的疊對量測(overlay measurement)是基於疊對量測元件100的電性,而非使用光或者電子束作為量測訊號,與傳統基於光學影像之疊對(image-based overlay ,IBO) 量測、基於光學繞射之疊對(diffraction-based overlay,DBO)量測與需使用臨界尺寸掃描式電子顯微鏡(critical dimension scanning electron microscope,CD-SEM)的晶粒內疊對(in-die overlay)量測不同,可不受光或電子束訊號的限制。Since the operation method of the
在一些實施方式中,由於第一導電層120的中心線L1與第二導電層140的對稱線L2重疊(如第2圖所示),且第二導電層140的第一區段141與第一導電層120之間的第一接觸面積A1等於第二導電層140的第四區段144與第一導電層120之間的第二接觸面積A2,因此可量測出第一電流I1等於該第二電流I2。也就是說,當第一電流I1等於第二電流I2時,第一導電層120的中心線L1與第二導電層140的對稱線L2重疊,且第二導電層140的第一區段141與第一導電層120之間的第一接觸面積A1等於第二導電層140的第四區段144與第一導電層120之間的第二接觸面積A2。如此一來,便可得知第一導電層120與第二導電層140之間不具有重疊位移(overlay shift)。In some embodiments, since the center line L1 of the first
同時參閱第3圖與第4圖,一旦分別用以定義第一導電層120的圖案與第二導電層140的圖案的第一半導體曝光機與第二半導體曝光機存在非預期的偏差/機差,將使第一導電層120與第二導電層140之間具有重疊位移。參閱第3圖,在一些實施方式中,第二導電層140的對稱線L2在第一導電層120的中心線L1右側而分開距離D,且第二導電層140的第一區段141與第一導電層120之間的第一接觸面積A1大於第二導電層140的第四區段144與第一導電層120之間的第二接觸面積A2,因此可量測出第一電流I1大於第二電流I2。除此之外,由於第一電流I1與第二電流I2分別正比於第一接觸面積A1與第二接觸面積A2,可使用第一電流I1與第二電流I2計算第二導電層140的對稱線L2與第一導電層120的中心線L1之間的距離D。因此,當第一電流I1大於第二電流I2時,第二導電層140的對稱線L2在第一導電層120的中心線L1右側而分開距離D,距離D可藉由計算得知,且第二導電層140的第一區段141與第一導電層120之間的第一接觸面積A1大於第二導電層140的第四區段144與第一導電層120之間的第二接觸面積A2。Referring to FIG. 3 and FIG. 4 at the same time, if the first semiconductor exposure machine and the second semiconductor exposure machine used to define the pattern of the first
參閱第4圖,在一些實施方式中,第二導電層140的對稱線L2在第一導電層120的中心線L1左側而分開距離D,且第二導電層140的第一區段141與第一導電層120之間的第一接觸面積A1小於第二導電層140的第四區段144與第一導電層120之間的第二接觸面積A2,因此可量測出第一電流I1大於第二電流I2。因此,當第一電流I1小於第二電流I2時,第二導電層140的對稱線L2在第一導電層120的中心線L1左側而分開距離D,距離D可藉由計算得知,且第二導電層140的第一區段141與第一導電層120之間的第一接觸面積A1小於第二導電層140的第四區段144與第一導電層120之間的第二接觸面積A2。Referring to FIG. 4 , in some embodiments, the symmetry line L2 of the second
參閱第1圖,疊對量測元件100的操作方法並不限於上述步驟S1至S3。步驟S1至步驟S3可各包含多個詳細步驟。在一些實施方式中,疊對量測元件100的操作方法可更包括其他步驟於上述任兩步驟中。此外,步驟S1與步驟S2的順序可調換。Referring to FIG. 1 , the operation method of the
參閱第2圖,在一些實施方式中,在量測通過第二導電層140的第一區段141、第一導電層120與第二導電層140的第二區段142的第一電流I1時,施加偏壓V於第二導電層140的第一區段141與第二區段142;以及在量測通過第二導電層140的第三區段143、第一導電層120與第二導電層140的第四區段144的第二電流I2時,施加相同的偏壓V於第二導電層140的第四區段144與第三區段143。如此一來,由於第二導電層140的第一區段141與第二區段142的偏壓與第四區段144與第三區段143的偏壓相同(皆為偏壓V),因此可避免第一電流I1與第二電流I2的量測結果受到電壓差異的影響,進而影響後續對疊對位移的計算。除此之外,根據歐姆定律(Ohm's law),疊對量測元件100的操作方法更可包括比較與第一電流I1及第二電流I2分別對應的第一電阻及第二電阻以判斷第一導電層120的中心線L1與第二導電層140的對稱線L2是否重疊。Referring to FIG. 2 , in some embodiments, when measuring a first current I1 passing through a
應瞭解到,已敘述過的元件的操作方法將不再重複贅述,合先敘明。在以下敘述中,將說明疊對量測元件100的結構。It should be understood that the operation methods of the components that have been described will not be repeated, and are described first. In the following description, the structure of the stacked
第5圖繪示根據本揭露一實施方式之疊對量測元件100的俯視圖。同時參閱第2圖與第5圖,疊對量測元件100包括半導體基板110、第一導電層120、第一絕緣層130、第二導電層140與第二絕緣層150。半導體基板110具有切割道112。第一導電層120位於半導體基板110的切割道112上。第一絕緣層130位於半導體基板110的切割道112上,並圍繞第一導電層120。也就是說,第一導電層120在第一絕緣層130中。第一絕緣層130具有分別在第一導電層120相對兩側的第一部分131與第二部分132。第二導電層140位於第一導電層120上。第二導電層140依序具有第一區段141、第二區段142、第三區段143與第四區段144。第二導電層140的第一區段141的底面接觸第一導電層120與第一絕緣層130的第一部分131。第二導電層140的第一區段141與第一導電層120之間具有第一接觸面積A1。 第二導電層140的第四區段144的底面接觸第一導電層120與第一絕緣層130的第二部分132。第二導電層140的第四區段144與第一導電層120之間具有第二接觸面積A2。第二導電層140的第一區段141、第二區段142、第三區段143與第四區段144具有對稱線L2。第二導電層140的第一區段141及第二區段142分別與第四區段144及第三區段143沿對稱線L2對稱。第二導電層140的第一區段141、第二區段142、第三區段143與第四區段144的每一者具有相同的底面積。第二絕緣層150位於第一導電層120與第一絕緣層130上,且圍繞第二導電層140。也就是說,第二導電層140在第二絕緣層150中。FIG. 5 shows a top view of a stacked
由於第二導電層140的第一區段141與第一導電層120之間具有第一接觸面積A1,第四區段144與第一導電層120之間具有第二接觸面積A2,因此,可量測經過第一接觸面積A1與第二接觸面積A2的電流並根據歐姆定律計算第一接觸面積A1與第二接觸面積A2,使疊對量測元件100可用於量測晶粒內對應的導電層之間重疊位移(overlay shift),以利於後續製程中修正重疊位移帶來的誤差,並提升晶圓的良率。Since there is a first contact area A1 between the
除此之外,疊對量測元件100的第二導電層140的第一區段141、第二區段142、第三區段143與第四區段144相鄰兩者之間具有相同的第一間距d1。這樣的設計可固定經過第一區段141、第二區段142、第三區段143與第四區段144相鄰兩者之電流在第一導電層120的路徑長度。In addition, the
在一些實施方式中,疊對量測元件100的半導體基板110的材料可包括矽或碳化矽,第一導電層120的材料與第二導電層140材料可包括金屬或多晶矽,第一絕緣層130的材料與第二絕緣層150的材料可包括氮化物或氧化物,但並不以此為限。In some embodiments, the material of the
應瞭解到,已敘述過的元件結構、材料與功效將不再重複贅述,合先敘明。在以下敘述中,將說明其他形式的疊對量測元件。It should be understood that the previously described device structures, materials and functions will not be repeated, and are described first. In the following description, other forms of stacked measurement devices will be described.
第6圖繪示根據本揭露另一實施方式之疊對量測元件100a的俯視圖。疊對量測元件100a包括半導體基板110、第一導電層120、第一絕緣層130、第二導電層140與第二絕緣層150。本實施方式與第5圖實施方式不同的地方在於第二導電層140更具有複數個第五區段145。在本實施方式中,第二導電層140具有兩個第五區段145,但並不用以限制本揭露。第五區段145位於第二區段142與第三區段143之間,第五區段145相鄰兩者之間的距離為第一間距d1。第二區段142與第三區段143任一者與第五區段145之間的距離為第一間距d1。第五區段145的每一者、第一區段141、第二區段142、第三區段143與第四區段144的每一者具有相同的底面積。這樣的設計使疊對量測元件100a可量測更大的重疊位移。舉例而言,若分別用以定義疊對量測元件100a的第一導電層120的圖案與第二導電層140的圖案的第一半導體曝光機與第二半導體曝光機存在偏差/機差,使第二導電層140的對稱線L2在第一導電層120的中心線L1右側或左側,且第二導電層140的第五區段145其中一者接觸第一導電層120及第一絕緣層130,可藉由疊對量測元件100a的電性找出第五區段145的該者,並以經過第五區段145的該者的電流計算第五區段145的該者與第一導電層120之間的接觸面積以及第二導電層140與第一導電層120之間的重疊位移。FIG. 6 shows a top view of a stacked
第7圖繪示根據本揭露又一實施方式之疊對量測元件100b的俯視圖。疊對量測元件100b包括半導體基板110、第一導電層120、第一絕緣層130、第二導電層140與第二絕緣層150。本實施方式與第6圖實施方式不同的地方在於疊對量測元件100b的第二導電層140的第五區段145相鄰兩者之間的距離為第二間距d2,且第二間距d2與第一間距d1不同。FIG. 7 shows a top view of a stacked
第8圖繪示根據本揭露再一實施方式之疊對量測元件100c的俯視圖。疊對量測元件100c包括半導體基板110、第一導電層120、第一絕緣層130、第二導電層140與第二絕緣層150。本實施方式與第5圖實施方式不同的地方在於第二導電層140的第一區段141、第二區段142、第三區段143與第四區段144每一者具有分開的複數個部分,其中第一區段141具有複數個部分146,第二區段142具有複數個部分147,第三區段143具有複數個部分148,第四區段144具有複數個部分149,這些部分146、147、148、149的俯視形狀可為矩形或方形。第一區段141的部分146相鄰兩者之間的距離相同,第二區段142的部分147相鄰兩者之間的距離相同,第三區段143的部分148相鄰兩者之間的距離相同,且第四區段144的部分149相鄰兩者之間的距離相同。第一區段141的部分146、第二區段142的部分147、第三區段143的部分148與第四區段144的部分149的俯視形狀為矩形。這樣的設計,因每一區段沿第二方向D2有複數個部分(例如四個),使用於量測沿第一方向D1的重疊位移的疊對量測元件100c可沿第二方向D2進行多次(例如四次)量測而具有更好的解析度。除此之外,疊對量測元件100c可用於量測沿第二方向D2的重疊位移。FIG8 shows a top view of a stacked
第9圖繪示根據本揭露一實施方式之疊對量測元件100d的俯視圖。疊對量測元件100d包括半導體基板110、第一導電層120、第一絕緣層130、第二導電層140與第二絕緣層150。本實施方式與第8圖實施方式不同的地方在於,疊對量測元件100d的第一區段141的部分146、第二區段142的部分147、第三區段143的部分148與第四區段144的部分149的俯視形狀為圓形。FIG. 9 shows a top view of a stacked
前述概述了幾個實施方式的特徵,使得本領域技術人員可以更好地理解本揭露的態樣。本領域技術人員應當理解,他們可以容易地將本揭露用作設計或修改其他過程和結構的基礎,以實現與本文介紹的實施方式相同的目的和/或實現相同的優點。本領域技術人員還應該認識到,這樣的等效構造不脫離本揭露的精神和範圍,並且在不脫離本揭露的精神和範圍的情況下,它們可以在這裡進行各種改變,替換和變更。The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and/or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications here without departing from the spirit and scope of the present disclosure.
100,100a,100b,100c,100d:疊對量測元件 110:半導體基板 112:切割道 120:第一導電層 130:第一絕緣層 131:第一部分 132:第二部分 140:第二導電層 141:第一區段 142:第二區段 143:第三區段 144:第四區段 145:第五區段 146,147,148,149:部分 150:第二絕緣層 A1:第一接觸面積 A2:第二接觸面積 D:距離 D1:第一方向 D2:第二方向 d1:第一間距 d2:第二間距 I1:第一電流 I2:第二電流 L1:中心線 L2:對稱線 V:偏壓 100,100a,100b,100c,100d: stacked measuring element 110: semiconductor substrate 112: cutting path 120: first conductive layer 130: first insulating layer 131: first part 132: second part 140: second conductive layer 141: first section 142: second section 143: third section 144: fourth section 145: fifth section 146,147,148,149: part 150: second insulating layer A1: first contact area A2: second contact area D: distance D1: first direction D2: second direction d1: first spacing d2: second spacing I1: first current I2: second current L1: center line L2: symmetry line V: bias voltage
當與隨附圖示一起閱讀時,可由後文實施方式最佳地理解本揭露內容的態樣。注意到根據此行業中之標準實務,各種特徵並未按比例繪製。實際上,為論述的清楚性,可任意增加或減少各種特徵的尺寸。 第1圖繪示根據本揭露一實施方式之疊對量測元件的操作方法的流程圖。 第2圖至第4圖繪示根據本揭露一實施方式之疊對量測元件的操作方法在不同情況下之疊對量測元件的剖面圖。 第5圖繪示根據本揭露一實施方式之疊對量測元件的俯視圖。 第6圖繪示根據本揭露另一實施方式之疊對量測元件的俯視圖。 第7圖繪示根據本揭露又一實施方式之疊對量測元件的俯視圖。 第8圖繪示根據本揭露再一實施方式之疊對量測元件的俯視圖。 第9圖繪示根據本揭露一實施方式之疊對量測元件的俯視圖。 The disclosure is best understood from the following embodiments when read in conjunction with the accompanying illustrations. Note that various features are not drawn to scale in accordance with standard practice in the industry. In fact, the sizes of various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 illustrates a flow chart of a method for operating a stacked measurement element according to an embodiment of the disclosure. FIG. 2 to FIG. 4 illustrate cross-sectional views of stacked measurement elements under different circumstances in accordance with the method for operating a stacked measurement element according to an embodiment of the disclosure. FIG. 5 illustrates a top view of a stacked measurement element according to an embodiment of the disclosure. FIG. 6 illustrates a top view of a stacked measurement element according to another embodiment of the disclosure. FIG. 7 shows a top view of a stacked measurement element according to another embodiment of the present disclosure. FIG. 8 shows a top view of a stacked measurement element according to another embodiment of the present disclosure. FIG. 9 shows a top view of a stacked measurement element according to an embodiment of the present disclosure.
100:疊對量測元件 100: Stacked measuring element
110:半導體基板 110:Semiconductor substrate
112:切割道 112: Cutting Road
120:第一導電層 120: First conductive layer
130:第一絕緣層 130: First insulation layer
131:第一部分 131: Part 1
132:第二部分 132: Part 2
140:第二導電層 140: Second conductive layer
141:第一區段 141: Section 1
142:第二區段 142: Second section
143:第三區段 143: The third section
144:第四區段 144: Section 4
150:第二絕緣層 150: Second insulation layer
A1:第一接觸面積 A1: First contact area
A2:第二接觸面積 A2: Second contact area
I1:第一電流 I1: first current
I2:第二電流 I2: Second current
L1:中心線 L1: Centerline
L2:對稱線 L2: symmetry line
V:偏壓 V: Bias voltage
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