TWI834728B - Inspection instruction information generation device, substrate inspection system, inspection instruction information generation method and inspection instruction information generation program - Google Patents
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
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- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
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- G—PHYSICS
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Abstract
檢查指示資訊產生裝置3包括:儲存部34,儲存導電結構資訊D1,所述導電結構資訊D1表示具備設有多個導電部P的表背一對基板面F1、F2、積層在基板面F1、基板面F2之間的層即配線層L、及將配線層L的配線與多個導電部P連接的通孔V的基板B的導電部P、配線W及通孔V如何導通連接;以及檢查指示資訊產生部33,執行檢查指示資訊產生處理,所述檢查指示資訊產生處理基於導電結構資訊D1使形成於同一基板面的導電部P彼此成對地將多個導電部P兩兩組合,並產生表示該組合後的一對導電部P的資訊作為檢查指示資訊D2。The inspection instruction information generating device 3 includes a storage unit 34 that stores conductive structure information D1. The conductive structure information D1 represents a pair of front and back substrate surfaces F1 and F2 provided with a plurality of conductive portions P. The substrate surfaces F1 and F2 are laminated on the substrate surfaces F1 and F2. How the wiring layer L, which is the layer between the substrate surfaces F2, and the through hole V connecting the wiring of the wiring layer L to the plurality of conductive parts P, the conductive portion P of the substrate B, the wiring W, and the through hole V are electrically connected; and inspection The instruction information generation unit 33 executes an inspection instruction information generation process that combines a plurality of conductive portions P formed on the same substrate surface in pairs based on the conductive structure information D1, and Information representing the combined pair of conductive parts P is generated as inspection instruction information D2.
Description
本發明是有關於一種產生用於指示檢查基板時的檢查部位的檢查指示資訊的檢查指示資訊產生裝置、使用該檢查指示資訊進行檢查的基板檢查系統、檢查指示資訊產生方法以及檢查指示資訊產生程式。 The present invention relates to an inspection instruction information generation device that generates inspection instruction information for instructing an inspection location when inspecting a substrate, a substrate inspection system that uses the inspection instruction information to perform inspection, an inspection instruction information generation method, and an inspection instruction information generation program. .
自先前以來,已知有如下的檢查裝置:針對設置在基板上的穿通孔(through hole),使探針跨越基板的表背分別與穿通孔的一端和另一端接觸,從而進行穿通孔的電阻測量(例如,參照專利文獻1)。 Conventionally, there has been known an inspection device that measures the resistance of a through hole provided in a substrate by making probes reach one end and the other end of the through hole across the front and back of the substrate. Measurement (for example, refer to Patent Document 1).
[現有技術文獻] [Prior art documents]
[專利文獻] [Patent Document]
[專利文獻1]日本專利特開平09-043295號公報 [Patent Document 1] Japanese Patent Application Publication No. 09-043295
但是,如所述的檢查裝置般,為了測量基板的表背之間的電壓,需要跨越基板的表背牽引將探針連接到電壓表上的配線。因此,測量配線的迴路變大,容易拾取雜訊,結果可能會降低電阻 測量精度。另外,如果跨越基板的表背,使探針分別接觸基板的表面和背面,由於在基板的兩面間對外來雜訊的影響產生差異,探針的檢測電壓上疊加雜訊,因此有可能降低電阻測量精度。 However, like the above inspection device, in order to measure the voltage between the front and back of the substrate, it is necessary to pull the wire connecting the probe to the voltmeter across the front and back of the substrate. Therefore, the measurement wiring loop becomes larger and noise is easily picked up, which may result in lower resistance. Measurement accuracy. In addition, if the probe is placed across the front and back of the substrate and contacts the surface and back of the substrate respectively, the influence of external noise on the two sides of the substrate is different, and noise is superimposed on the detection voltage of the probe, which may reduce the resistance. Measurement accuracy.
本發明的目的在於提供一種產生檢查指示資訊的檢查指示資訊產生裝置、包含該檢查指示資訊產生裝置的基板檢查系統、檢查指示資訊產生方法以及檢查指示資訊產生程式,所述檢查指示資訊表示容易提高通孔的電阻測量精度的檢查部位。 An object of the present invention is to provide an inspection instruction information generation device that generates inspection instruction information, a substrate inspection system including the inspection instruction information generation device, an inspection instruction information generation method, and an inspection instruction information generation program. The inspection instruction information representation is easily improved. Check the resistance measurement accuracy of through holes.
本發明的一個例子所涉及的檢查指示資訊產生裝置是用於對基板進行檢查的檢查指示資訊產生裝置,所述基板具備設置有多個導電部的表背一對基板面、積層於所述一對基板面之間的層即配線層、以及將所述配線層的配線和所述導電部連接的通孔,所述檢查指示資訊產生裝置具備:儲存部,儲存表示所述基板的所述導電部、所述配線、及所述通孔如何導通連接的導電結構資訊;以及檢查指示資訊產生部,執行檢查指示資訊產生處理,該檢查指示資訊產生處理基於所述導電結構資訊,使形成於同一所述基板面的所述導電部彼此成對地將所述導電部兩兩組合,並產生表示該組合後的一對導電部的資訊作為檢查指示資訊。 An inspection instruction information generating device according to an example of the present invention is an inspection instruction information generating device for inspecting a substrate having a pair of front and back substrate surfaces provided with a plurality of conductive portions, and is laminated on the one surface. The inspection instruction information generating device is provided with a storage unit for storing the conductive information indicating the substrate for the wiring layer that is a layer between the substrate surfaces and the through hole connecting the wiring of the wiring layer and the conductive part. part, the wiring, and the conductive structure information of how the through hole is connected; and the inspection instruction information generation unit performs inspection instruction information generation processing. The inspection instruction information generation processing is based on the conductive structure information to form the same The conductive portions on the substrate surface are combined into pairs, and information representing the combined pair of conductive portions is generated as inspection instruction information.
另外,本發明的一個例子所涉及的檢查指示資訊產生方法是用於對基板進行檢查的檢查指示資訊產生方法,所述基板具備設置有多個導電部的表背一對基板面、積層於所述一對基板面之間的層即配線層、以及將所述配線層的配線和所述導電部連接 的通孔,所述檢查指示資訊產生方法執行檢查指示資訊產生處理,該檢查指示資訊產生處理基於表示所述基板的所述導電部、所述配線、及所述通孔如何導通連接的導電結構資訊,使形成於同一所述基板面的所述導電部彼此成對地將所述導電部兩兩組合,並產生表示該組合後的一對導電部的資訊作為檢查指示資訊。 In addition, an inspection instruction information generating method according to an example of the present invention is a method for generating inspection instruction information for inspecting a substrate having a pair of front and back substrate surfaces provided with a plurality of conductive portions, which are laminated on the substrate. The wiring layer is a layer between the pair of substrate surfaces, and the wiring of the wiring layer is connected to the conductive portion. of the through hole, the inspection instruction information generation method executes inspection instruction information generation processing based on a conductive structure indicating how the conductive portion, the wiring, and the through hole of the substrate are electrically connected. Information is generated by combining the conductive portions formed on the same substrate surface into pairs, and generating information representing the combined pair of conductive portions as inspection instruction information.
另外,本發明的一個例子所涉及的檢查指示資訊產生程式是用於對基板進行檢查的檢查指示資訊產生程式,所述基板具備設置有多個導電部的表背一對基板面、積層於所述一對基板面之間的層即配線層、以及將所述配線層的配線和所述導電部連接的通孔,所述檢查指示資訊產生程式使電腦執行檢查指示資訊產生處理,該檢查指示資訊產生處理基於表示所述基板的所述導電部、所述配線、及所述通孔如何導通連接的導電結構資訊,使形成於同一所述基板面的所述導電部彼此成對地將所述導電部兩兩組合,並產生表示該組合的一對導電部的資訊作為檢查指示資訊。 In addition, an inspection instruction information generation program according to an example of the present invention is an inspection instruction information generation program for inspecting a substrate having a pair of front and back substrate surfaces provided with a plurality of conductive portions, and is laminated on the substrate. The wiring layer is a layer between the pair of substrate surfaces, and a through hole connects the wiring of the wiring layer to the conductive part. The inspection instruction information generating program causes the computer to execute inspection instruction information generation processing. The inspection instruction The information generation process is based on the conductive structure information indicating how the conductive portion, the wiring, and the through hole of the substrate are electrically connected, so that the conductive portions formed on the same substrate surface are paired with each other. The conductive parts are combined in pairs, and information representing the combined pair of conductive parts is generated as inspection instruction information.
另外,本發明的基板檢查系統包括:所述檢查指示資訊產生裝置;以及基板檢查裝置,基於由所述檢查指示資訊產生裝置產生的檢查指示資訊,執行所述通孔的檢查。 In addition, the substrate inspection system of the present invention includes: the inspection instruction information generating device; and a substrate inspection device that performs inspection of the through hole based on the inspection instruction information generated by the inspection instruction information generating device.
1:基板檢查系統 1:Substrate inspection system
2:基板檢查裝置 2:Substrate inspection device
3:檢查指示資訊產生裝置 3: Check the instruction information generating device
4U、4L:測量治具 4U, 4L: Measuring fixture
12:測量塊 12:Measurement block
13:掃描器部 13:Scanner Department
20:控制部 20:Control Department
21:檢查處理部 21:Inspection Processing Department
31:簡化處理部 31: Simplified processing department
32:樹狀結構資料轉換部 32:Tree structure data conversion department
33:檢查指示資訊產生部 33: Inspection instruction information generation department
22、34:儲存部 22, 34: Storage Department
110:基板固定裝置 110:Substrate fixing device
112:框體 112:Frame
121、122:測量部 121, 122: Measurement Department
125:移動機構 125:Mobile mechanism
a1~a4、b1~b4、c1、c2、d1:導電路徑 a1~a4, b1~b4, c1, c2, d1: conductive path
B、B1~B5:基板 B, B1~B5: substrate
CS、CM:電源部 CS, CM: Power Department
D1:導電結構資訊 D1: Conductive structure information
D1':簡化導電結構資訊 D1': Simplified conductive structure information
D1":樹狀結構導電結構資訊 D1": Tree structure conductive structure information
D2:檢查指示資訊 D2: Check instruction information
F1、F2:基板面 F1, F2: substrate surface
+F、-F:電流端子 +F, -F: current terminal
I:電流值 I: current value
IP、IPa、IPd:面狀導體 IP, IPa, IPd: planar conductor
L、L1、L2、Lc、L4:配線層 L, L1, L2, Lc, L4: wiring layer
M、Mr1~Mr6、M11~M14、M22、M41~M47:分支 M, Mr1~Mr6, M11~M14, M22, M41~M47: branches
N、N11、N12、N21、N41、N42:節點 N, N11, N12, N21, N41, N42: nodes
NR:根節點 NR: root node
P、P1~P7、P11~P17:導電部 P, P1~P7, P11~P17: conductive part
Pr:探針 Pr: probe
+S、-S:電壓檢測端子 +S, -S: voltage detection terminal
S1、S2、S3、S4、S11、S5、S5a、S5b、S6a、S6、S11、S12、S12a、S12b、S13、S13a、S14、S15、S15a、S21、S22、S23、S24、S25、S26、S27、S28:步驟 S1, S2, S3, S4, S11, S5, S5a, S5b, S6a, S6, S11, S12, S12a, S12b, S13, S13a, S14, S15, S15a, S21, S22, S23, S24, S25, S26, S27, S28: steps
VM:電壓檢測部 VM: Voltage detection department
V、V11~V17、V21~V27、V31~V36、V41~V45、V51~V57:通孔 V, V11~V17, V21~V27, V31~V36, V41~V45, V51~V57: through holes
W、W11、W12、W21、W22、W41~W45:配線 W, W11, W12, W21, W22, W41~W45: Wiring
圖1是概念性地表示本發明的一實施方式的基板檢查系統的構成的示意圖。 FIG. 1 is a schematic diagram conceptually showing the structure of a substrate inspection system according to an embodiment of the present invention.
圖2是表示圖1所示測量部的電氣構成的一例的框圖。 FIG. 2 is a block diagram showing an example of the electrical configuration of the measurement unit shown in FIG. 1 .
圖3是表示作為檢查對象的基板的一例的剖面圖。 FIG. 3 is a cross-sectional view showing an example of a substrate to be inspected.
圖4是表示作為檢查對象的基板的一例的平面圖。 FIG. 4 is a plan view showing an example of a substrate to be inspected.
圖5是圖示簡化導電結構資訊的一例的圖。 FIG. 5 is a diagram illustrating an example of simplified conductive structure information.
圖6是圖示樹狀結構導電結構資訊的一例的圖。 FIG. 6 is a diagram illustrating an example of tree-structured conductive structure information.
圖7是表示檢查指示資訊產生方法及檢查指示資訊產生裝置的運作的一例的流程圖。 FIG. 7 is a flowchart showing an example of the operation of the inspection instruction information generating method and the inspection instruction information generating device.
圖8是表示檢查指示資訊產生方法及檢查指示資訊產生裝置的運作的一例的流程圖。 FIG. 8 is a flowchart showing an example of the operation of the inspection instruction information generating method and the inspection instruction information generating device.
圖9是搜索處理的說明圖。 FIG. 9 is an explanatory diagram of search processing.
圖10是圖7的變形例。 FIG. 10 is a modification of FIG. 7 .
圖11是圖8的變形例。 FIG. 11 is a modification of FIG. 8 .
圖12是圖10的步驟S5a的變形例。 FIG. 12 is a modification of step S5a in FIG. 10 .
圖13是圖11的步驟S12a的變形例。 FIG. 13 is a modification of step S12a in FIG. 11 .
圖14是檢查指示資訊的說明圖。 FIG. 14 is an explanatory diagram of inspection instruction information.
圖15是表示圖1所示的基板檢查裝置的運作的一例的流程圖。 FIG. 15 is a flowchart showing an example of the operation of the substrate inspection device shown in FIG. 1 .
以下,根據圖式對本發明的實施方式進行說明。再者,於各圖中賦予了相同的符號的構成表示相同的構成,並省略其說明。圖1中所示的基板檢查系統1包括檢查指示資訊產生裝置3與基板檢查裝置2。
Hereinafter, embodiments of the present invention will be described based on the drawings. In addition, components assigned the same reference numerals in the respective drawings represent the same components, and descriptions thereof will be omitted. The
圖1中所示的檢查指示資訊產生裝置3包括簡化處理部
31、樹狀結構資料轉換部32、檢查指示資訊產生部33、及儲存部34。檢查指示資訊產生裝置3例如使用個人電腦等電腦來構成,包括:執行規定的運算處理的中央處理單元(Central Processing Unit,CPU)、暫時地儲存資料的隨機存取記憶體(Random Access Memory,RAM)、硬磁碟驅動機(Hard Disk Drive,HDD)及/或快閃記憶體等非揮發性的儲存裝置、通信電路、以及該些的周邊電路等。
The inspection instruction
而且,檢查指示資訊產生裝置3藉由執行例如已被儲存於非揮發性的儲存裝置的本發明一實施方式的檢查指示資訊產生程式,而作為簡化處理部31、樹狀結構資料轉換部32、及檢查指示資訊產生部33發揮功能。儲存部34例如使用所述非揮發性的儲存裝置來構成。
Furthermore, the examination instruction
於儲存部34儲存導電結構資訊D1。可自外部經由例如省略圖示的通信電路而朝檢查指示資訊產生裝置3發送導電結構資訊D1,藉此將該經發送的導電結構資訊D1儲存於儲存部34,亦可藉由檢查指示資訊產生裝置3讀取已被儲存於例如通用串列匯流排(Universal Serial Bus,USB)記憶體等儲存媒體的導電結構資訊D1,而將導電結構資訊D1儲存於儲存部34,可利用各種方法將導電結構資訊D1儲存於儲存部34。
The conductive structure information D1 is stored in the
導電結構資訊D1是表示後述的基板B的導電部P、各配線層L的配線W或面狀導體IP、以及通孔V如何導通連接的資訊。作為導電結構資訊D1,例如可使用基板的製造中所使用的所 謂的格伯資料(gerber data)、及/或網路連線表(netlist)等。 The conductive structure information D1 is information indicating how the conductive portion P of the substrate B described below, the wiring W or the planar conductor IP of each wiring layer L, and the through hole V are electrically connected. As the conductive structure information D1, for example, any information used in the production of the substrate can be used. So-called Gerber data (gerber data), and/or network connection list (netlist), etc.
簡化處理部31對基於導電結構資訊D1而並聯連接的配線和通孔進行簡化,並產生簡化導電結構資訊D1'。簡化導電結構資訊D1'相當於導電結構資訊的一例。
The
樹狀結構資料轉換部32藉由使配線W對應於節點、使通孔V對應於分支、使面狀導體IP對應於根節點,將簡化導電結構資訊D1'轉換為樹狀結構的資料結構,產生樹狀結構導電結構資訊D1"。樹狀結構導電結構資訊D1"相當於導電結構資訊的一例。
The tree structure
檢查指示資訊產生部33基於導電結構資訊D1(D1'、D1"),針對基板檢查裝置2產生檢查指示資訊D2,所述檢查指示資訊D2用於指示為了檢查而應流入電流的導電部P的對。檢查指示資訊產生部33亦可經由例如省略圖示的通信電路而朝基板檢查裝置2發送檢查指示資訊D2。或者,檢查指示資訊產生部33亦可將檢查指示資訊D2寫入儲存媒體。而且,使用者亦可使基板檢查裝置2自所述儲存媒體讀入檢查指示資訊D2。檢查指示資訊產生部33的運作的詳細情況將後述。
The inspection instruction
圖1中所示的基板檢查裝置2是用於檢查作為檢查對象的被檢查基板的基板B的裝置。
The
基板B例如為中間基板或多層基板,亦可為印刷配線基板、膜形載體(film carrier)、可撓性基板、陶瓷多層配線基板、半導體晶片及半導體晶圓等半導體基板、半導體封裝用的封裝基板、液晶顯示器或電漿顯示器用的電極板、及製造該些基板的過 程的中間基板、或所謂的承載基板。 The substrate B is, for example, an intermediate substrate or a multilayer substrate. It may also be a printed wiring substrate, a film carrier, a flexible substrate, a ceramic multilayer wiring substrate, a semiconductor substrate such as a semiconductor chip or a semiconductor wafer, or a package for semiconductor packaging. Substrates, electrode plates for liquid crystal displays or plasma displays, and processes for manufacturing these substrates The intermediate substrate of the process, or the so-called carrier substrate.
圖1中所示的基板檢查裝置2具有框體112。於框體112的內部空間,主要設置有基板固定裝置110、測量部121、測量部122、移動機構125、以及控制部20。基板固定裝置110以將基板B固定於規定的位置的方式構成。
The
測量部121位於固定於基板固定裝置110的基板B的上方。測量部122位於固定於基板固定裝置110的基板B的下方。測量部121、測量部122包括用於使探針接觸設置於基板B的多個導電部的測量治具4U、測量治具4L。
The
於測量治具4U、測量治具4L安裝有多個探針Pr。測量治具4U、測量治具4L以與設置於基板B的表面的測量對象的導電部的配置對應的方式配置、保持多個探針Pr。移動機構125根據來自控制部20的控制訊號來使測量部121、測量部122於框體112內適宜移動,而使測量治具4U、測量治具4L的探針Pr接觸基板B的各導電部。
A plurality of probes Pr are attached to the measuring
再者,基板檢查裝置2亦可僅包括測量部121、測量部122中的任一者,基板B亦可僅於一面設置有導電部。另外,基板檢查裝置2亦可使被檢查基板進行表背反轉,而藉由任一個測量部來進行其兩面的測量。
Furthermore, the
控制部20例如包括如下構件來構成:執行規定的運算處理的CPU(Central Processing Unit)、暫時地儲存資料的RAM(Random Access Memory)、儲存規定的控制程式的唯讀記憶體
(Read Only Memory,ROM)、HDD(Hard Disk Drive)等非揮發性的儲存部22,以及該些的周邊電路等。而且,控制部20藉由執行例如已被儲存於儲存部22的控制程式,而作為檢查處理部21發揮功能。
The
圖2中所示的測量部121包括:掃描器部13、多個測量塊12、以及多個探針Pr。再者,測量部122與測量部121同樣地構成,因此省略其說明。
The
測量塊12包括電源部CS、電源部CM及電壓檢測部VM。電源部CS、電源部CM是輸出對應於來自控制部20的控制訊號的電流I的定電流電路。電源部CS使電流I於朝掃描器部13供給的方向上流動,電源部CM使電流I於自掃描器部13引入的方向上流動。電壓檢測部VM是測量電壓,並朝控制部20中發送其電壓值的電壓檢測電路。
The
再者,測量塊12不一定需要具備電源部CS、電源部CM這兩者。測量塊12亦可以僅具備電源部CS、電源部CM中的任意一者。
Furthermore, the
掃描器部13例如為使用電晶體或繼電器開關等開關元件來構成的切換電路。掃描器部13對應於多個測量塊12,包括多個用於對基板B供給電阻測量用的電流I的電流端子+F、電流端子-F,及用於檢測藉由電流I而於基板B的導電部間產生的電壓的電壓檢測端子+S、電壓檢測端子-S。另外,於掃描器部13電性連接有多個探針Pr。掃描器部13對應於來自控制部20的控制訊
號,切換電流端子+F、電流端子-F及電壓檢測端子+S、電壓檢測端子-S與多個探針Pr之間的連接關係。
The
電源部CS的輸出端子的一端與電路接地(circuit ground)連接,另一端與電流端子+F連接。電源部CM的輸出端子的一端與電路接地連接,另一端與電流端子-F連接。電壓檢測部VM的一端與電壓檢測端子+S連接,另一端與電壓檢測端子-S連接。 One end of the output terminal of the power supply unit CS is connected to circuit ground, and the other end is connected to the current terminal +F. One end of the output terminal of the power supply unit CM is connected to the circuit ground, and the other end is connected to the current terminal -F. One end of the voltage detection unit VM is connected to the voltage detection terminal +S, and the other end is connected to the voltage detection terminal -S.
而且,掃描器部13可對應於來自控制部20的控制訊號,將電流端子+F、電流端子-F及電壓檢測端子+S、電壓檢測端子-S與任意的探針Pr導通連接。藉此,掃描器部13可對應於來自控制部20的控制訊號,使電流I流入探針Pr所接觸的任意的導電部間,並利用電壓檢測部VM來測量於所述導電部間產生的電壓V。
Furthermore, the
由於設置有多個測量塊12,因此可對多個導電部間同時執行電流供給與電壓測量。 Since a plurality of measurement blocks 12 are provided, current supply and voltage measurement can be simultaneously performed between a plurality of conductive parts.
再者,電源部CS、電源部CM只要可使電流I經由掃描器部13而流入基板B即可,並不限定於電源部CS、電源部CM的一端與電路接地連接的例子。例如,亦可為將電源部CS的一端與電源部CM的一端連接來形成電流迴路(current loop)的構成。
In addition, as long as the power supply unit CS and the power supply unit CM can cause the current I to flow into the substrate B via the
藉此,控制部20可藉由朝掃描器部13輸出控制訊號,而利用多個電源部CS、電源部CM來使電流I流入任意的多對探針Pr間,並利用多個電壓檢測部VM來檢測任意的多對探針Pr
間的電壓。
Thereby, the
再者,測量塊12不必限定於設置多個的例子。亦可以構成為藉由一個測量塊12,對多個導電部間依次執行電流供給和電壓測量。
Furthermore, the measurement blocks 12 are not necessarily limited to the example in which a plurality of measurement blocks 12 are provided. It may also be configured so that one
圖3兼作基板B的剖面圖、及圖示基板B的導電結構資訊D1的說明圖。導電結構資訊D1未必是由圖像表示的資料,但於以下的說明中,為了容易理解,利用圖式來表示並說明由導電結構資訊D1表示的結構。 FIG. 3 serves as a cross-sectional view of the substrate B and an explanatory diagram illustrating the conductive structure information D1 of the substrate B. As shown in FIG. The conductive structure information D1 is not necessarily data represented by an image. However, in the following description, in order to facilitate understanding, the structure represented by the conductive structure information D1 is represented and explained using diagrams.
圖3中所示的基板B是將五塊基板B1~B5積層而成的多層基板。將基板B的一個表面設為基板面F1,將另一個表面設為基板面F2。在基板B1和基板B2之間設置配線層L1,在基板B2和基板B3之間設置配線層L2,在基板B3和基板B4之間設置配線層Lc,在基板B4和基板B5之間設置配線層L4。 The substrate B shown in FIG. 3 is a multilayer substrate in which five substrates B1 to B5 are laminated. Let one surface of the substrate B be a substrate surface F1 and the other surface be a substrate surface F2. A wiring layer L1 is provided between the substrates B1 and B2, a wiring layer L2 is provided between the substrates B2 and B3, a wiring layer Lc is provided between the substrates B3 and B4, and a wiring layer is provided between the substrates B4 and B5. L4.
於基板面F1設置有導電部P1~導電部P7,於基板面F2設置有導電部P11~導電部P17。導電部P1~導電部P7、導電部P11~導電部P17成為焊墊、凸塊、配線、電極等被探針Pr抵接的檢查點。 Conductive portions P1 to P7 are provided on the substrate surface F1, and conductive portions P11 to P17 are provided on the substrate surface F2. The conductive portions P1 to P7 and the conductive portions P11 to P17 serve as inspection points where the pads, bumps, wirings, electrodes, etc. are contacted by the probe Pr.
於配線層Lc設置有擴展成面狀或網狀的導體即面狀導體IP,作為配線的一例。於配線層L1設置有配線W11、配線W12,於配線層L2設置有配線W21、配線W22,於配線層L4設置有配線W41、配線W42、配線W43與配線W44、配線W45。面狀導體IP可為擴展成一塊片材狀,即面狀的形狀,亦可為具有如下的 形狀的導體:將配線等導體圖案組合成規則或無規則的網狀(網眼狀),於同一層內作為整體而擴展成面狀。 As an example of wiring, a planar conductor IP, which is a conductor expanded in a planar or mesh shape, is provided on the wiring layer Lc. The wiring layer L1 is provided with the wiring W11 and the wiring W12, the wiring layer L2 is provided with the wiring W21 and the wiring W22, and the wiring layer L4 is provided with the wiring W41, the wiring W42, the wiring W43, the wiring W44, and the wiring W45. The planar conductor IP can be expanded into a sheet shape, that is, a planar shape, or it can have the following properties: Shaped conductors: Conductor patterns such as wiring are combined into a regular or irregular mesh (mesh-like), and are expanded into a planar shape as a whole within the same layer.
再者,於圖3中,表示了面狀導體IP擴展至基板B的大致整個區域的例子,但面狀導體IP未必限定於擴展至基板B的大致整個區域的例子。面狀導體IP亦可僅設置於基板B的一部分的區域。例如,於配線層Lc中的未設置基板B的面狀導體IP的區域,亦可設置配線W。 3 shows an example in which the planar conductor IP extends to substantially the entire area of the substrate B, but the planar conductor IP is not necessarily limited to the example in which it extends to substantially the entire area of the substrate B. The planar conductor IP may be provided in only a part of the substrate B. For example, the wiring W may be provided in a region of the wiring layer Lc where the planar conductor IP of the substrate B is not provided.
圖4中所示的基板B包括相互電性分離的面狀導體IPa與面狀導體IPd。面狀導體IPa例如可用作類比接地(analog ground),面狀導體IPd例如可用作數位接地(digital ground)。如圖4所示,基板B亦可包括相互絕緣的多個面狀導體IP。 The substrate B shown in FIG. 4 includes a planar conductor IPa and a planar conductor IPd that are electrically separated from each other. The planar conductor IPa can be used as an analog ground, for example, and the planar conductor IPd can be used as a digital ground, for example. As shown in FIG. 4 , the substrate B may also include a plurality of planar conductors IP that are insulated from each other.
配線W41、W42、W43是配線層L4的配線W41、配線W42、及配線W43相連而成的一根配線,但為了便於說明,將一根配線W41、W42、W43的各部分稱為配線W41、配線W42、及配線W43。同樣地,配線W44、W45是配線W44與配線W45相連而成的一根配線,配線W44及配線W45分別為配線W44、W45的一部分。 The wiring W41, W42, and W43 are one wiring in which the wiring W41, the wiring W42, and the wiring W43 of the wiring layer L4 are connected. However, for convenience of explanation, each part of one wiring W41, W42, and W43 is called wiring W41, W42, and W43. Wiring W42 and wiring W43. Similarly, wiring W44 and W45 are one wiring in which wiring W44 and wiring W45 are connected, and wiring W44 and wiring W45 are parts of wiring W44 and W45 respectively.
另外,於基板B,設置有貫穿基板B1的通孔V11~通孔V17,設置有貫穿基板B2的通孔V21~通孔V27,設置有貫穿基板B3的通孔V31~通孔V36,設置有貫穿基板B4的通孔V41~通孔V45,設置有貫穿基板B5的通孔V51~通孔V57。 In addition, the substrate B is provided with through holes V11 to V17 penetrating the substrate B1, through holes V21 to V27 penetrating the substrate B2, and through holes V31 to V36 penetrating the substrate B3. Through-holes V41 to V45 penetrating the substrate B4 are provided, and through-holes V51 to V57 penetrating the substrate B5 are provided.
於已被儲存於儲存部34的導電結構資訊D1,包含表示
該些導電部P1~導電部P7、導電部P11~導電部P17,配線W11、配線W12、配線W21、配線W22、配線W41~配線W45,通孔V11~通孔V17、通孔V21~通孔V27、通孔V31~通孔V36、通孔V41~通孔V45、通孔V51~通孔V57,以及面狀導體IP如何導通連接的資訊,例如表示圖3中所圖示的連接關係的資訊。
The conductive structure information D1 that has been stored in the
以下,將導電部P1~導電部P7、導電部P11~導電部P17等導電部總稱為導電部P,將配線W11、配線W12、配線W21、配線W22、配線W41~配線W45等配線總稱為配線W,將通孔V11~通孔V17、通孔V21~通孔V27、通孔V31~通孔V36、通孔V41~通孔V45、通孔V51~通孔V57等總稱為通孔V,將配線層L1、配線層L2、配線層Lc、配線層L4總稱為配線層L。 Hereinafter, the conductive portions P1 to P7, P11 to P17, and other conductive portions are collectively referred to as the conductive portion P, and the wirings W11, W12, W21, W22, W41 to W45, and other wirings are collectively referred to as wirings. W, the through hole V11~through hole V17, the through hole V21~the through hole V27, the through hole V31~the through hole V36, the through hole V41~the through hole V45, the through hole V51~the through hole V57, etc. are collectively called the through hole V, and The wiring layer L1, the wiring layer L2, the wiring layer Lc, and the wiring layer L4 are collectively referred to as the wiring layer L.
導電結構資訊D1中進而包括表示各配線W、各通孔V以及各面狀導體IP的厚度、寬度、長度以及電阻率的資訊、及/或表示各通孔V的電阻值、各配線W以及各面狀導體IP的片電阻值的資訊。藉此,檢查指示資訊產生部33能夠基於導電結構資訊D1計算任意的導電路徑的電阻值。
The conductive structure information D1 further includes information indicating the thickness, width, length, and resistivity of each wiring W, each through hole V, and each planar conductor IP, and/or information indicating the resistance value of each through hole V, each wiring W, and Information on the sheet resistance value of each planar conductor IP. Thereby, the inspection instruction
再者,導電結構資訊D1的資料形式能夠採用各種形式。導電結構資訊D1可以是例如單個資料檔案、可以由多個資料檔案構成、並且可以是不具有檔案形式的資料結構。 Furthermore, the data form of the conductive structure information D1 can adopt various forms. The conductive structure information D1 may be, for example, a single data file, may be composed of multiple data files, and may be a data structure without a file form.
各導電部P經由通孔V和配線W而與面狀導體IP導通連接。如此,各導電部P與面狀導體IP導通連接的配線結構通常用於電路接地或電源模式的連接用途。再者,基板B當然亦可包 含未與電路接地或電源模式連接的配線或焊墊等。 Each conductive part P is electrically connected to the planar conductor IP via the through hole V and the wiring W. In this way, the wiring structure in which each conductive part P and the planar conductor IP are electrically connected is generally used for circuit grounding or power supply mode connection purposes. Furthermore, substrate B can of course also include Contains wiring or pads that are not connected to circuit ground or power mode.
若將基板B安裝於基板固定裝置110,則藉由移動機構125,使測量部121的各探針Pr抵接於導電部P1~導電部P7,並使測量部122的各探針Pr抵接於導電部P11~導電部P17。藉此,測量部121、測量部122可使電流I流入任意的一對導電部P間,而檢測所述一對導電部P間的電壓。
When the substrate B is mounted on the
測量部121、測量部122為了利用所謂的四端子電阻測量法的電阻測量,可使電流供給用的探針Pr與電壓測量用的探針Pr接觸一個導電部P,為了利用所謂的二端子電阻測量法的電阻測量,亦可使兼任電流供給與電壓測量的一個探針Pr接觸一個導電部P。
In order to measure resistance using a so-called four-terminal resistance measurement method, the
檢查處理部21對測量部121、測量部122進行控制,將來自電源部CS(參照圖2)的電流I供給至如後述般選擇的一對導電部P中的一者,並藉由電源部CM(參照圖2)而自另一者中抽出電流I,藉此將電流I供給至導電部P間,並檢測所述導電部P間的電壓,且基於所述電流與所述電壓來檢查基板B。檢查處理部21例如可基於所述電流與所述電壓,利用四端子電阻測量法或二端子電阻測量法進行電阻測量,並基於其電阻值,進行基板B的檢查。
The
以下,將檢查處理部21藉由控制測量部121、測量部122來進行電流供給及電壓檢測的情況僅如檢查處理部21供給電流、檢測電壓般記載。檢查處理部21的運作的詳細情況將後述。
Hereinafter, the case where the
繼而,對所述檢查指示資訊產生裝置3的運作進行說明。以產生對應於圖3中所示的基板B的檢查指示資訊的情況為例進行說明。以下,一面參照圖5~圖8,一面對基於本發明一實施方式的檢查指示資訊產生程式來執行檢查指示資訊產生方法的檢查指示資訊產生裝置3的運作進行說明。
Next, the operation of the inspection instruction
再者,在以下的流程圖中,對相同的處理附加相同的步驟編號,省略其說明。 In addition, in the following flowcharts, the same step numbers are assigned to the same processing, and the description thereof is omitted.
首先,簡化處理部31執行使由導電結構資訊D1表示的連接結構簡單化的處理作為前處理。具體地說,簡化處理部31在多個配線層L的配線W並聯連接的情況下,以將該並聯連接的配線W替換為一根配線W的方式對導電結構資訊D1進行複製、變更,從而產生簡化導電結構資訊D1'(步驟S1:簡化處理)。
First, the
具體而言,於圖3中所示的導電結構資訊D1中,多個配線層L1、配線層L2的配線W11、配線W21藉由通孔V21、通孔V22而並聯連接。於此情況下,相對於導電結構資訊D1,如圖5所示,將兩根配線W11、配線W21替換成配線W11、配線W21之中例如最接近基板面F1的一根配線W11,而產生簡化導電結構資訊D1'。此時,通孔V22的一端變成打開,因此於資料上,亦可視為不存在通孔V22的處理。藉此,將基板B的配線結構簡單化,因此以後的處理變得容易。 Specifically, in the conductive structure information D1 shown in FIG. 3 , the wiring W11 and the wiring W21 of the wiring layers L1 and L2 are connected in parallel by the through holes V21 and V22. In this case, with respect to the conductive structure information D1, as shown in FIG. 5 , the two wires W11 and W21 are replaced with, for example, one wire W11 closest to the substrate surface F1 among the wires W11 and W21, resulting in simplification. Conductive structure information D1'. At this time, one end of the through hole V22 becomes open, so in the data, it can also be regarded as processing that the through hole V22 does not exist. This simplifies the wiring structure of the substrate B, making subsequent processing easier.
繼而,簡化處理部31於藉由配線W與面狀導體IP,而將通孔V或通孔V的行並聯連接的情況下,以將該經並聯連接的 通孔V或通孔V的行替換成一個通孔或一行通孔的方式,變更簡化導電結構資訊D1'(步驟S2:簡化處理)。 Next, when the through-holes V or the rows of the through-holes V are connected in parallel by the wiring W and the planar conductor IP, the parallel-connected The through-hole V or the row of through-holes V is replaced with one through-hole or a row of through-holes, and the simplified conductive structure information D1' is changed (step S2: simplification processing).
具體而言,於圖3所示的導電結構資訊D1中,將通孔V24、通孔V33串聯連接而形成行,將通孔V25、通孔V34串聯連接而形成行。而且,藉由配線W12與面狀導體IP,而將通孔V24、通孔V33的行與通孔V25、通孔V34的行並聯連接。另外,藉由配線W22與面狀導體IP,而將通孔V32與通孔V33並聯連接。 Specifically, in the conductive structure information D1 shown in FIG. 3 , the vias V24 and V33 are connected in series to form a row, and the vias V25 and V34 are connected in series to form a row. Furthermore, the rows of via holes V24 and via holes V33 are connected in parallel to the rows of via holes V25 and via holes V34 by the wiring W12 and the planar conductor IP. In addition, the through hole V32 and the through hole V33 are connected in parallel by the wiring W22 and the planar conductor IP.
於此情況下,例如如圖5所示,針對簡化導電結構資訊D1',將通孔V24、通孔V33的行與通孔V25、通孔V34的行替換成任一行,例如替換成通孔V24、通孔V33的行,將通孔V32與通孔V33替換成一個通孔V,例如替換成通孔V32。 In this case, for example, as shown in FIG. 5 , for the simplified conductive structure information D1 ′, the rows of vias V24 and V33 and the rows of vias V25 and V34 are replaced with any row, for example, with vias In the rows of V24 and through hole V33, the through hole V32 and the through hole V33 are replaced with one through hole V, for example, replaced with the through hole V32.
另外,於圖3所示的導電結構資訊D1中,藉由配線W41、配線W42、配線W43的串聯配線與面狀導體IP,而將通孔V41與通孔V42並聯連接。於此情況下,例如如圖5所示,於簡化導電結構資訊D1'中,將通孔V41、通孔V42替換成一個通孔V,例如替換成通孔V41。另外,於圖3所示的導電結構資訊D1中,藉由配線W44、配線W45與面狀導體IP,而將通孔V43、通孔V44、通孔V45並聯連接。於此情況下,例如如圖5所示,在簡化導電結構資訊D1'中,將通孔V43、通孔V44、通孔V45替換成一個通孔V,例如替換成通孔V43。藉此,將基板B的配線結構簡單化,因此以後的處理變得容易。 In addition, in the conductive structure information D1 shown in FIG. 3 , the through hole V41 and the through hole V42 are connected in parallel by the series wiring of the wiring W41 , the wiring W42 , and the wiring W43 and the planar conductor IP. In this case, for example, as shown in FIG. 5 , in the simplified conductive structure information D1 ′, the through hole V41 and the through hole V42 are replaced by one through hole V, for example, replaced by the through hole V41 . In addition, in the conductive structure information D1 shown in FIG. 3 , the through hole V43 , the through hole V44 , and the through hole V45 are connected in parallel by the wiring W44 , the wiring W45 and the planar conductor IP. In this case, for example, as shown in FIG. 5 , in the simplified conductive structure information D1 ′, the through hole V43 , the through hole V44 , and the through hole V45 are replaced with one through hole V, for example, with the through hole V43 . This simplifies the wiring structure of the substrate B, making subsequent processing easier.
再者,未必需要具備簡化處理部31,亦可不執行步驟S1、步驟S2,而在以後的處理中,使用表示圖3所示的基板B的實際的配線結構的資料形式的導電結構資訊D1來代替簡化導電結構資訊D1'。
Furthermore, the
繼而,樹狀結構資料轉換部32將簡化導電結構資訊D1'的資料結構轉換成樹狀結構(步驟S3)。將已被轉換成樹狀結構的簡化導電結構資訊D1'稱為樹狀結構導電結構資訊D1"。如圖6所示,於樹狀結構導電結構資訊D1"中,一根配線W由一個節點N表達,面狀導體IP由根節點NR表達,通孔V作為將導電部P與節點間連接的分支M、或將節點相互間連接的分支M來表達。
Then, the tree structure
再者,未必需要具備樹狀結構資料轉換部32,亦可不執行步驟S3,而使用表示基板B的配線結構的資料形式的導電結構資訊D1、或簡化導電結構資訊D1'執行以後的處理。於以下的說明中,對於節點N的處理與對於對應於所述節點N的配線W的處理相同,對於根節點NR的處理與對於面狀導體IP的處理相同,對於分支M的處理與對於對應於所述分支M的通孔V的處理相同。
Furthermore, the tree structure
於圖6所示的樹狀結構的樹狀結構導電結構資訊D1"的例子中,節點N11對應於配線W11(W21),節點N12對應於配線W12,節點N21對應於配線W22,節點N41對應於配線W41、配線W42、配線W43,節點N42對應於配線W44、配線W45。另外,分支M11對應於通孔V11(V21),分支M12對應於通孔V12 (V22),分支M13對應於通孔V14,分支M14對應於通孔V15,分支M22對應於通孔V24(V25),分支Mr1對應於通孔V31,分支Mr2對應於通孔V32(V33),分支Mr3對應於通孔V16、通孔V26、通孔V35,分支Mr4對應於通孔V17、通孔V27、通孔V36,分支M41對應於通孔V51,分支M42對應於通孔V52,分支M43對應於通孔V53,分支M44對應於通孔V54,分支M45對應於通孔V55,分支M46對應於通孔V56,分支M47對應於通孔V57,分支Mr5對應於通孔V41(V42),分支Mr6對應於通孔V43(V44、V45)。 In the example of the tree-structured conductive structure information D1" of the tree structure shown in FIG. 6 , the node N11 corresponds to the wiring W11 (W21), the node N12 corresponds to the wiring W12, the node N21 corresponds to the wiring W22, and the node N41 corresponds to The wiring W41, the wiring W42, the wiring W43, and the node N42 correspond to the wiring W44 and the wiring W45. In addition, the branch M11 corresponds to the through hole V11 (V21), and the branch M12 corresponds to the through hole V12 (V22), branch M13 corresponds to the through hole V14, branch M14 corresponds to the through hole V15, branch M22 corresponds to the through hole V24 (V25), branch Mr1 corresponds to the through hole V31, branch Mr2 corresponds to the through hole V32 (V33), Branch Mr3 corresponds to through-hole V16, through-hole V26, and through-hole V35, branch Mr4 corresponds to through-hole V17, through-hole V27, and through-hole V36, branch M41 corresponds to through-hole V51, branch M42 corresponds to through-hole V52, and branch M43 Corresponding to the through hole V53, the branch M44 corresponds to the through hole V54, the branch M45 corresponds to the through hole V55, the branch M46 corresponds to the through hole V56, the branch M47 corresponds to the through hole V57, the branch Mr5 corresponds to the through hole V41 (V42), the branch Mr6 corresponds to via V43 (V44, V45).
繼而,檢查指示資訊產生部33對於使基板面F1上的導電部P彼此、即形成於同一基板面的導電部P彼此成對的全部組合,基於導電結構資訊D1計算出所述一對導電部P之間的電阻值(步驟S4)。再者,在步驟S4中,對於基板B的所有導電部P的全部組合,可計算所述一對導電部P之間的電阻值,並在後述步驟S11中使用該計算值。
Next, the inspection instruction
另外,對於使導電部P彼此成對的所有組合,亦可以不計算該一對導電部P間的電阻值。例如,亦可以對一對導電部P間為規定距離以下的組合計算電阻值。藉由削減計算電阻值的組合,獲得縮短處理時間的效果。 In addition, for all combinations in which the conductive parts P are paired with each other, the resistance value between the pair of conductive parts P does not need to be calculated. For example, the resistance value may be calculated for a combination in which the distance between a pair of conductive parts P is equal to or less than a predetermined distance. By reducing the number of combinations of calculated resistance values, the processing time is shortened.
繼而、檢查指示資訊產生部33自步驟S4得到的計算上的電阻值小的組合起,依序以導電部P不重覆的方式選擇導電部對,並記錄於檢查指示資訊(步驟S5:檢查指示資訊產生處理)。
以下,將導電部P1、導電部P2間的電阻值記為R(P1,P2),將導電部P3、P4間的電阻值記為R(P3,P4)...
Next, the inspection instruction
例如,於圖3所示的導電結構資訊D1中,當按照R(P1,P2),R(P4,P5),R(P6,P7)的順序電阻值變大時,選擇導電部P1、P2,導電部P4、P5,導電部P6、P7的每一對,並將其記錄在檢查指示資訊中。 For example, in the conductive structure information D1 shown in Figure 3, when the resistance value becomes larger in the order of R(P1, P2), R(P4, P5), R(P6, P7), select the conductive parts P1 and P2 , each pair of conductive parts P4, P5, and conductive parts P6, P7, and record them in the inspection instruction information.
繼而,檢查指示資訊產生部33在基板面F1上的導電部P的數量為奇數時,在包含最後殘留的導電部P的組合中選擇電阻值最小的導電部對,並追加記錄於檢查指示資訊(步驟S6)。
Next, when the number of conductive parts P on the substrate surface F1 is an odd number, the inspection instruction
在圖3所示的導電結構資訊D1中,最後殘留有導電部P3,因此,在包含導電部P3的組合中,作為電阻值最小的導電部對,例如選擇導電部P3、導電部P4,並追加記錄在檢查指示資訊中。 In the conductive structure information D1 shown in FIG. 3 , the conductive part P3 remains at the end. Therefore, among the combinations including the conductive part P3, as the conductive part pair with the smallest resistance value, for example, the conductive part P3 and the conductive part P4 are selected, and Additional records are added to the inspection instruction information.
繼而,檢查指示資訊產生部33對於使基板面F2上的導電部P彼此、即形成於同一基板面的導電部P彼此成對的全部組合,基於導電結構資訊D1計算出該一對導電部P之間的電阻值(步驟S11)。
Next, the inspection instruction
繼而,檢查指示資訊產生部33自步驟S11得到的計算上的電阻值小的組合起,依序以導電部P不重覆的方式,選擇導電部對,並記錄於檢查指示資訊(步驟S12:檢查指示資訊產生處理)。
Then, starting from the combination with the smaller calculated resistance value obtained in step S11, the inspection instruction
例如,於圖3所示的導電結構資訊D1中,當按照R (P11,P12),R(P13,P14),R(P15,P16)的順序電阻值變大時,選擇導電部P11、P12,導電部P13、P14,導電部P15、P16的每一對,並將其記錄在檢查指示資訊中。 For example, in the conductive structure information D1 shown in Figure 3, when according to R When the sequential resistance values of (P11, P12), R (P13, P14), and R (P15, P16) become larger, select each pair of conductive parts P11, P12, conductive parts P13, P14, and conductive parts P15, P16, And record it in the inspection instruction information.
繼而,檢查指示資訊產生部33在基板面F2上的導電部P的數量為奇數時,在包含最後殘留的導電部P的組合中選擇電阻值最小的導電部對,並追加記錄於檢查指示資訊(步驟S13)。
Next, when the number of conductive portions P on the substrate surface F2 is an odd number, the inspection instruction
於圖3所示的導電結構資訊D1中,最後殘留有導電部P17,因此,在包含導電部P17的組合中,作為電阻值最小的導電部對,例如選擇導電部P16、導電部P17,並追加記錄在檢查指示資訊中。 In the conductive structure information D1 shown in FIG. 3 , the conductive part P17 remains at the end. Therefore, among the combinations including the conductive part P17 , as the conductive part pair with the smallest resistance value, for example, the conductive part P16 and the conductive part P17 are selected, and Additional records are added to the inspection instruction information.
繼而,檢查指示資訊產生部33基於樹狀結構的樹狀結構導電結構資訊D1"來搜索不位於在步驟S5、步驟S6、步驟S12、步驟S13中選擇的各導電部對的,自一個導電部P到另一個導電部P的導電路徑上的檢測洩漏通孔(步驟S14:搜索處理)。
Then, the inspection instruction
參照圖9,導電部P1與導電部P2、導電部P4與導電部P5、導電部P6與導電部P7、及導電部P3與導電部P4的各導電部對中的自一個導電部P到另一個導電部P的導電路徑a1~導電路徑a4、以及導電部P11與導電部P12、導電部P13與導電部P14、導電部P15與導電部P16、及導電部P16與導電部P17的各導電部對中的自一個導電部P到另一個導電部P的導電路徑b1~導電路徑b4中,不包含分支Mr1、分支Mr2、分支Mr5、分支Mr6。 Referring to FIG. 9 , the conductive portions P1 and P2, P4 and P5, P6 and P7, and P3 and P4 are aligned from one conductive portion P to the other. The conductive paths a1 to a4 of one conductive part P, and the conductive parts of the conductive part P11 and the conductive part P12, the conductive part P13 and the conductive part P14, the conductive part P15 and the conductive part P16, and the conductive part P16 and the conductive part P17 The pair of conductive paths b1 to b4 from one conductive part P to the other conductive part P do not include branch Mr1, branch Mr2, branch Mr5, and branch Mr6.
因此,藉由檢查指示資訊產生部33查出分支Mr1、分
支Mr2、分支Mr5、分支Mr6,即通孔V31、通孔V32、通孔V41(V42)、通孔V43(V44、V45)作為檢測洩漏通孔。
Therefore, the inspection instruction
繼而,檢查指示資訊產生部33優先在同一基板面內,且按照電阻值小的組合順序選擇在導電路徑中包含在步驟S14中搜索到的檢測洩漏通孔的導電部對,並記錄在檢查指示資訊中(步驟S15:導電部追加處理)。
Then, the inspection instruction
具體而言,檢查指示資訊產生部33首先在同一基板面內搜索在導電路徑中包含檢測洩漏通孔的導電部對,當在同一基板面內未發現的情況下,跨基板兩面進行搜索,據此使同一基板面內優先。
Specifically, the inspection instruction
例如,於選擇在導電路徑中包括分支Mr1,即通孔V31的導電部對的情況下,檢查指示資訊產生部33基於圖9所示的樹狀結構導電結構資訊D1",首先通過優先選擇基板面F1上的導電部P1~導電部P7來選擇導電部對。
For example, when selecting a pair of conductive parts including branch Mr1, that is, a through hole V31, in the conductive path, the inspection instruction
具體而言,選擇將其中一者設為導電部P1、導電部P2中的任一者、將另一者設為導電部P3~導電部P7中的任一者的導電部對作為在導電路徑中包含分支Mr1的導電部對的候補。繼而,檢查指示資訊產生部33自作為候補而選擇的導電部對中選擇電阻值最小的導電部對,例如導電部P1、導電部P6,並記錄於檢查指示資訊。同樣,作為在導電路徑中包含分支Mr2的導電部對,例如選擇導電部P3、導電部P6。
Specifically, a pair of conductive parts in which one of them is any one of the conductive parts P1 and P2 and the other one is any one of the conductive parts P3 to P7 is selected as the conductive path. Candidates for conductive portion pairs including branch Mr1. Next, the inspection instruction
繼而,作為在導電路徑中包含分支Mr5、分支Mr6的導 電部對,基板面F2上的導電部P11~導電部P17優先,例如選擇導電部P14、導電部P15,並記錄在檢查指示資訊中。 Then, as the conductive path including branch Mr5 and branch Mr6 For the electrical part pair, the electrically conductive parts P11 to P17 on the substrate surface F2 are given priority, for example, the electrically conductive part P14 and the electrically conductive part P15 are selected and recorded in the inspection instruction information.
藉此,在導電部P1、導電部P6之間的導電路徑c1中包含分支Mr1,在導電部P3、導電部P6之間的導電路徑c2中包含分支Mr2,在導電部P14、導電部P15之間的導電路徑d1中包含分支Mr5、分支Mr6,因此後述的基板檢查裝置2基於這樣得到的檢查指示資訊進行檢查,藉此可對所有的通孔V進行檢查。
Thereby, the conductive path c1 between the conductive parts P1 and P6 includes the branch Mr1, the conductive path c2 between the conductive parts P3 and P6 includes the branch Mr2, and the conductive part P14 and the conductive part P15 include the branch Mr2. The conductive path d1 between the two substrates includes branches Mr5 and Mr6. Therefore, the
在步驟S15中,當在同一基板面內不存在包含檢測洩漏通孔的導電部對時,檢查指示資訊產生部33自包含基板面F1的導電部P和基板面F2的導電部P的導電部對,即,包含檢測洩漏通孔的導電部對中,選擇電阻值最小的導電部對。以上藉由步驟S1~步驟S15,圖14所示的檢查指示資訊D2完成,結束處理。
In step S15 , when there is no conductive part pair including the leakage detection via hole in the same substrate surface, the inspection instruction
根據步驟S5、步驟S6、步驟S12、步驟S13,藉由同一基板面上的導電部P彼此組合來選擇導電部對。另外,根據步驟S15,優先選擇同一基板面內的導電部對。其結果,在進行由這樣得到的檢查指示資訊所指示的導電部對間的電阻測量來進行通孔的檢查的情況下,如以下所說明般,其電阻測量精度提高。 According to step S5, step S6, step S12, and step S13, a pair of conductive parts is selected by combining the conductive parts P on the same substrate surface with each other. In addition, according to step S15, pairs of conductive portions within the same substrate surface are preferentially selected. As a result, when the through hole is inspected by measuring the resistance between the pairs of conductive parts indicated by the inspection instruction information obtained in this way, the resistance measurement accuracy is improved as explained below.
即,在基板B的同一面內的導電部彼此之間進行電阻測量的情況下,如圖1所示,能夠僅藉由設置在測量治具4U或測量治具4L的任一個測量治具上的探針Pr進行測量,因此,能夠僅藉由測量部121、測量部122中的任一個測量部進行測量用電流的供給及電壓檢測。
That is, when performing resistance measurement between conductive portions on the same surface of the substrate B, as shown in FIG. Therefore, the measurement current can be supplied and the voltage can be detected only by any one of the
另一方面,在跨基板B的兩面在一對導電部彼此之間進行電阻測量的情況下,需要使用測量治具4U的探針Pr和測量治具4L的探針Pr,跨測量部121和測量部122進行測量用電流的供給和電壓檢測。在這種情況下,與在基板B的同一平面內的各導電部之間進行電阻測量的情況相比,測量部121、測量部122的電流供給用配線和電壓檢測用配線形成的迴路變大。配線迴路大時,通過該配線迴路內的電磁雜訊增加,且配線迴路的阻抗增大。
On the other hand, when performing resistance measurement between a pair of conductive parts across both surfaces of the substrate B, it is necessary to use the probe Pr of the measuring
另外,當藉由在基板B的一對導電部P之間流入電流來檢測所述導電部對間的電壓,根據歐姆定律從所述電流和測量電壓來測量電阻值時,外來電磁場作為雜訊而與檢測電壓重疊。於基板B的一個面內,以大致相同的方式施加外來電磁場,因此於基板B的一個面側,由外來電磁場所引起的雜訊電壓變得大致固定。因此,於測量基板B的一個面內的一對導電部P之間的電壓的情況下,與所述測量電壓重疊的雜訊變成共同模式(common mode),其結果,雜訊對測量電壓造成的影響減少。 In addition, when the voltage between the pair of conductive parts P is detected by flowing a current between the pair of conductive parts P of the substrate B, and the resistance value is measured from the current and the measured voltage according to Ohm's law, the external electromagnetic field acts as noise And overlap with the detection voltage. The external electromagnetic field is applied in a substantially uniform manner on one surface of the substrate B. Therefore, the noise voltage caused by the external electromagnetic field becomes substantially constant on one surface side of the substrate B. Therefore, when the voltage between a pair of conductive portions P in one surface of the substrate B is measured, the noise that overlaps with the measured voltage becomes a common mode. As a result, the noise affects the measured voltage. impact is reduced.
另一方面,於基板B的兩面間,在基板B的表背所施加的電磁場強度產生差,於基板B的一個面與另一個面,由外來電磁場所引起的雜訊電壓產生差。因此,於跨基板B的兩面測量一對導電部P之間的電壓的情況下,與所述測量電壓重疊的雜訊變成正常模式(normal mode),其結果,雜訊電壓直接與測量電壓重疊。其結果,與測量基板B的一個面內的一對導電部P之間的電壓的情況相比,跨基板B的兩面測量一對導電部P之間的電壓時 雜訊的影響變大。 On the other hand, a difference in the intensity of the electromagnetic field applied to the front and back of the substrate B occurs between the two surfaces of the substrate B, and a difference in noise voltage caused by the external electromagnetic field occurs between one surface and the other surface of the substrate B. Therefore, when the voltage between a pair of conductive portions P is measured across both sides of the substrate B, the noise that overlaps with the measured voltage becomes a normal mode. As a result, the noise voltage directly overlaps with the measured voltage. . As a result, compared with the case where the voltage between a pair of conductive parts P is measured on one surface of the substrate B, when the voltage between a pair of conductive parts P is measured across both surfaces of the substrate B, The impact of noise becomes greater.
因此,當藉由在步驟S5、步驟S6、步驟S12、步驟S13中由同一基板面上的導電部P彼此組合選擇導電部對,在步驟S15中優先選擇同一基板面內的導電部對,來進行由這樣得到的檢查指示資訊所指示的導電部對間的電阻測量來進行通孔的檢查時,其電阻測量精度提高。 Therefore, when the conductive part pairs are selected by combining the conductive parts P on the same substrate surface in steps S5, S6, S12, and S13, and the conductive part pairs within the same substrate surface are preferentially selected in step S15, and the resistance between the conductive part pairs indicated by the inspection instruction information obtained in this way is measured to inspect the through hole, the resistance measurement accuracy is improved.
另外,根據步驟S5、步驟S6、步驟S12、步驟S13、步驟S15,自導電部對間的電阻值的理論值小的組合起,依序選擇導電部對的組合。其結果,在進行由這樣得到的檢查指示資訊所指示的導電部對間的電阻測量來進行通孔V的檢查時,其檢查精度提高。 In addition, in step S5, step S6, step S12, step S13, and step S15, combinations of conductive part pairs are selected in order from the combination with the smallest theoretical resistance value between the conductive part pairs. As a result, when the through hole V is inspected by measuring the resistance between the pairs of conductive parts indicated by the inspection instruction information obtained in this way, the inspection accuracy is improved.
即,在進行通孔V的檢查的情況下,理想的是測量通孔V本身的電阻值。但是,如圖3所示,由於通孔V的兩端沒有露出至基板B的表面,因此無法直接測量通孔V本身的電阻值。因此,藉由選擇在包括通孔V的導電路徑上相互連接的導電部對,測量整個所述導電路徑的電阻值來檢查通孔V。 That is, when inspecting the through hole V, it is desirable to measure the resistance value of the through hole V itself. However, as shown in FIG. 3 , since both ends of the through hole V are not exposed to the surface of the substrate B, the resistance value of the through hole V itself cannot be directly measured. Therefore, the through hole V is inspected by selecting a pair of conductive parts connected to each other on the conductive path including the through hole V and measuring the resistance value of the entire conductive path.
在進行這樣的檢查時,導電路徑整體的電阻值越小,通孔V的電阻值占導電路徑整體電阻值的比率增大的概率變高,通孔V以外的配線電阻的影響就越小。因此,在步驟S5、步驟S6、步驟S12、步驟S13、步驟S15中,以導電部對間的電阻值越小則越優先的方式選擇導電部對的組合,藉此進行由這樣得到的檢查指示資訊所指示的導電部對間的電阻測量來進行通孔V的檢查 時,其檢查精度提高。 When such an inspection is performed, the smaller the resistance value of the entire conductive path, the higher the probability that the ratio of the resistance value of the via hole V to the resistance value of the entire conductive path will increase, and the smaller the influence of wiring resistance other than the via hole V will be. Therefore, in steps S5, S6, S12, S13, and S15, the combination of the conductive portion pairs is selected so that the smaller the resistance value between the conductive portion pairs is, the higher the priority is, and the inspection instruction obtained in this way is performed. Check the through hole V by measuring the resistance between the pairs of conductive parts indicated by the information. time, its inspection accuracy is improved.
再者,在步驟S5、步驟S6、步驟S12、步驟S13中,不一定限定於藉由同一基板面上的導電部P彼此的組合來選擇導電部對的例子。但是,從能夠產生容易提高通孔V的檢查精度的檢查指示資訊這一點來看,更佳為在步驟S5、步驟S6、步驟S12、步驟S13中,藉由同一基板面上的導電部P彼此的組合來選擇導電部對。 Furthermore, in step S5, step S6, step S12, and step S13, it is not necessarily limited to the example in which the pair of conductive parts is selected by combining the conductive parts P on the same substrate surface. However, from the point of view of being able to generate inspection instruction information that can easily improve the inspection accuracy of the through hole V, it is more preferable to communicate with each other through the conductive portions P on the same substrate surface in steps S5, S6, S12, and S13. combination to select pairs of conductive parts.
另外,在步驟S15中,不限於優先選擇同一基板面內的導電部對的例子。但是,從能夠產生容易提高通孔V的檢查精度的檢查指示資訊這一點來看,更佳為在步驟S15中優先選擇同一基板面內的導電部對。 In addition, in step S15, it is not limited to the example of preferentially selecting pairs of conductive portions within the same substrate surface. However, from the viewpoint of being able to generate inspection instruction information that can easily improve the inspection accuracy of the through hole V, it is more preferable to preferentially select pairs of conductive portions within the same substrate surface in step S15 .
然而,在檢查例如具備四個通孔和與這些通孔連接的導電部X1~導電部X4的基板的通孔的情況下,存在如下方法:固定檢查對象的導電部對中的一者,如導電部X1-導電部X2、導電部X1-導電部X3、導電部X1-導電部X4般,通過三次電阻測量來檢查四個通孔。 However, in the case of inspecting, for example, a through hole of a substrate having four through holes and conductive portions X1 to X4 connected to these through holes, there is a method as follows: fixing one of the pair of conductive portions of the inspection object, such as The conductive part X1 - the conductive part X2, the conductive part X1 - the conductive part X3, the conductive part X1 - the conductive part X4 are the same, and the four through holes are inspected through three resistance measurements.
但是,根據步驟S5和步驟S12,以兩兩不重覆的方式組合多個導電部P,從而產生表示作為檢查部位的導電部對的檢查指示資訊。其結果,當基於這樣獲得的檢查指示資訊對通孔進行檢查時,與上述方法相比,檢查次數減少。因此,容易縮短通孔的檢查時間。 However, according to steps S5 and S12, a plurality of conductive parts P are combined in a non-overlapping manner, thereby generating inspection instruction information indicating a pair of conductive parts as an inspection part. As a result, when the through hole is inspected based on the inspection instruction information obtained in this way, the number of inspections is reduced compared to the above method. Therefore, it is easy to shorten the inspection time of the through hole.
即,可知若將多個導電P以兩兩不重覆的方式組合,則 所述導電部X1~導電部X4成為導電部X1-導電部X2和導電部X3-導電部X4兩組,藉由兩次電阻測量就能夠檢查四個通孔,因此與上述方法相比檢查次數減少,通孔的檢查時間縮短。 That is, it can be seen that if a plurality of conductive Ps are combined in a non-overlapping manner, then The conductive part X1 ~ conductive part X4 are divided into two groups: conductive part X1 - conductive part X2 and conductive part X3 - conductive part Reduced, through-hole inspection time is shortened.
另外,可以不執行步驟S3,不基於樹狀結構的樹狀結構導電結構資訊D1",而基於導電結構資訊D1或簡化導電結構資訊D1',來執行步驟S14的搜索處理和步驟S15的導電部追加處理。但是,若執行步驟S3,基於樹狀結構的樹狀結構導電結構資訊D1"執行步驟S14、步驟S15,則在能夠簡化步驟S14、步驟S15的處理這一點上更佳。 In addition, step S3 may not be performed, and the search process of step S14 and the conductive part of step S15 may be performed based not on the tree-like structure conductive structure information D1" of the tree structure, but on the conductive structure information D1 or the simplified conductive structure information D1'. Additional processing. However, if step S3 is executed and steps S14 and S15 are executed based on the tree-structured conductive structure information D1", it is more preferable in that the processing of steps S14 and S15 can be simplified.
另外,可以不執行步驟S1,亦可以不執行步驟S2。而且,在步驟S3中,可以將導電結構資訊D1轉換為樹狀結構的樹狀結構導電結構資訊D1"。但是,藉由執行步驟S1、步驟S2的簡化處理,步驟S3的向樹狀結構的樹狀結構導電結構資訊D1"的變換處理得以簡化,且亦使樹狀結構導電結構資訊D1"簡單化。其結果,在簡化基於樹狀結構導電結構資訊D1"的步驟S14、步驟S15的處理這一點上更佳。 In addition, step S1 may not be executed, and step S2 may not be executed. Furthermore, in step S3, the conductive structure information D1 can be converted into tree-structured conductive structure information D1" of a tree structure. However, by performing the simplification processes of steps S1 and S2, the conductive structure information D1 of step S3 can be converted into tree-structured conductive structure information D1". The conversion process of the tree-structure conductive structure information D1" is simplified, and the tree-structure conductive structure information D1" is also simplified. As a result, the processing of steps S14 and S15 based on the tree-structure conductive structure information D1" is simplified. Better at this point.
再者,如圖10、圖11所示,可以不執行步驟S4、步驟S11,在步驟S5a、步驟S12a中並非按照電阻值小的組合順序,而按照基板面上的導體部對間的距離短的組合順序選擇導電部對。另外,可以執行圖12、圖13所示的步驟S5b、步驟S12b來代替步驟S5a、步驟S12a,而不論組合順序如何都從同一基板面上的導電部對中,以導電部P不重覆的方式選擇導電部對。另外,可 以在步驟S6a、步驟S13a中,選擇基板面上的導電部對間的距離最短的導電部對,而非電阻值最小的導電部對。 Furthermore, as shown in FIGS. 10 and 11 , steps S4 and S11 may not be executed. Steps S5a and S12a are performed not in the order of combinations with small resistance values, but in order of the distance between pairs of conductor portions on the substrate surface being short. Select the pair of conductive parts in the order of combination. In addition, steps S5b and S12b shown in FIGS. 12 and 13 can be performed instead of steps S5a and S12a, and regardless of the order of combination, the conductive parts on the same substrate surface are centered so that the conductive parts P do not overlap. The method selects the conductive part pair. In addition, it can In step S6a and step S13a, the pair of conductive parts with the shortest distance between the pairs of conductive parts on the substrate surface is selected instead of the pair of conductive parts with the smallest resistance value.
在這種情況下,不需要步驟S4、步驟S11中的電阻值的計算處理,因此能夠降低檢查指示資訊產生處理的資料處理量。另外,基板面上的導電部對之間的距離越短,該導電部對間的導電路徑長度短的可能性越高,因此電阻值低的可能性越高。 In this case, the calculation processing of the resistance value in steps S4 and S11 is not required, so the data processing amount of the inspection instruction information generation processing can be reduced. In addition, the shorter the distance between the pairs of conductive parts on the substrate surface, the higher the possibility that the length of the conductive path between the pairs of conductive parts will be short, and therefore the higher the possibility that the resistance value will be low.
因此,在步驟S6a、步驟S13a中,代替步驟S6、步驟S13中電阻值小的組合順序,設為基板面上的導電部對間的距離短的組合順序,藉此能夠在不執行步驟S4、步驟S11的情況下,以近似電阻值小的組合順序的優先順序來選擇導電部對。 Therefore, in steps S6a and S13a, instead of the combination order in which the resistance value is small in steps S6 and step S13, a combination order in which the distance between the pairs of conductive portions on the substrate surface is short is used, thereby enabling steps S4 and S13 to be performed without executing steps S4 and S13. In the case of step S11, the pairs of conductive portions are selected in priority order approximately in the order of combinations with small resistance values.
另外,導電部對的導電部間的導電路徑所包含的通孔數量和配線數量的合計越少,該導電部對間的導電路徑長度短的可能性越高,因此電阻值低的可能性越高。配線的數量對應於樹狀結構導電結構資訊D1"中節點N(通孔V和通孔V之間)的數量。 In addition, the smaller the total number of via holes and the number of wirings included in the conductive path between the conductive portion pairs, the higher the possibility that the conductive path length between the conductive portion pair will be short, and therefore the resistance value will be low. high. The number of wirings corresponds to the number of nodes N (between via V and via V) in the tree structure conductive structure information D1".
因此,在步驟S15a中,代替步驟S15中的電阻值小的組合,導電部對中的導電部間的導電路徑所包含的通孔的數量和配線的數量的合計少的組合優先,藉此可不執行步驟S4、步驟S11而以近似電阻值小的組合順序的優先順序來選擇導電部對。 Therefore, in step S15a, instead of the combination with a small resistance value in step S15, a combination with a small total number of through holes and the number of wirings included in the conductive path between the conductive parts in the conductive part pair is given priority, thereby eliminating the need for Steps S4 and S11 are executed to select pairs of conductive portions in a priority order that approximates the order of combinations with small resistance values.
再者,在執行圖7、圖8所示的步驟S1~步驟S14之後,可執行步驟S15a來代替步驟S15。另外,在執行圖10、圖11所示的步驟S1~步驟S14之後,可執行步驟S15來代替步驟S15a。 Furthermore, after executing steps S1 to S14 shown in FIGS. 7 and 8 , step S15a may be executed instead of step S15. In addition, after executing steps S1 to S14 shown in FIGS. 10 and 11 , step S15 may be executed instead of step S15a.
另外,在步驟S15a中,可以代替導電部對中的導電部 間的導電路徑所包含的通孔的數量和配線的數量的合計少的組合,而與步驟S5a、步驟S12a同樣地,按照基板面上的導電部對間的距離短的組合順序選擇導電部對。 In addition, in step S15a, the conductive part in the pair of conductive parts may be replaced with The combinations in which the total number of through holes and the number of wirings included in the conductive paths between them are small, and similarly to steps S5a and S12a, the pairs of conductive parts on the substrate surface are selected in the order of the combinations in which the distance between the pairs of conductive parts is short. .
但是,檢測洩漏通孔很可能是多層基板中的遠離表層的配線層之間的通孔。包含遠離表層的配線層之間的通孔的導電路徑的長度與接近表層的層間的通孔相比,與基板面上的導電部對間的距離的相關性弱。 However, the leakage detection through hole is likely to be a through hole between wiring layers far away from the surface layer in a multilayer substrate. The length of the conductive path including the via hole between the wiring layers far from the surface layer has a weaker correlation with the distance between the pairs of conductive portions on the substrate surface than the through hole between layers close to the surface layer.
因此,在選擇導電路徑中包含檢測洩漏通孔的導電部對時,與基板面上的導電部對間的距離短的組合順序相比,按導電部對中的導電部間的導電路徑所包含的通孔的數量和配線的數量的合計少的組合順序來選擇導電部對時,能夠選擇對間的電阻值小的導電部對的可能性增大,因此較佳。 Therefore, when selecting a pair of conductive portions that include a leakage detection via hole in the conductive path, the order of combinations in which the distance between the pairs of conductive portions on the substrate surface is short is compared to the order in which the conductive portions in the pair are included in the conductive paths. It is preferable to select a pair of conductive parts in a combination order in which the total number of through holes and the number of wirings is small because the possibility of selecting a pair of conductive parts with a small resistance value between the pairs increases.
另外,在步驟S5a、步驟S12a中可不按照基板面上的導電部對間的距離短的組合順序,而與步驟S15a同樣地,設為導電部對中的導電部間的導電路徑所包含的通孔的數量和配線的數量的合計少的組合順序。但是,從不需要進行搜索導電部對間的導電路徑的處理這一點來看,更佳為在步驟S5a、步驟S12a中按照基板面上的導電部對間的距離短的組合順序選擇導電部對。 In addition, in steps S5a and S12a, it is not necessary to follow the order in which the distance between the pairs of conductive parts on the substrate surface is short. Instead, as in step S15a, the path included in the conductive path between the conductive parts in the pair of conductive parts may be used. A combination sequence in which the total number of holes and wiring is small. However, since there is no need to perform a process of searching for a conductive path between the conductive portion pairs, it is more preferable to select the conductive portion pairs in steps S5a and S12a in the order in which the distance between the conductive portion pairs on the substrate surface is short. .
另外,在步驟S6a、步驟S13a中可以不選擇基板面上的導電部對間的距離最短的導電部對,而選擇導電部對中的導電部間的導電路徑所包含的通孔的數量和配線的數量的合計最少的導電部對。但是,從不需要搜索導電部對間的導電路徑的處理這一 點來看,更佳為在步驟S6a、步驟S13a中選擇基板面上的導電部對間的距離最短的導電部對。 In addition, in steps S6a and S13a, instead of selecting the pair of conductive parts with the shortest distance between the pairs of conductive parts on the substrate surface, the number of through holes and wiring included in the conductive paths between the conductive parts in the pair of conductive parts may be selected. The sum of the smallest number of pairs of conductive parts. However, there is never a need for a process of searching for a conductive path between pairs of conductive parts. From this point of view, it is more preferable to select the pair of conductive parts with the shortest distance between the pairs of conductive parts on the substrate surface in steps S6a and S13a.
圖14是表示如上所述記錄的檢查指示資訊D2的一例的表形式的說明圖。將這樣得到的檢查指示資訊D2例如利用省略圖示的通信電路發送給基板檢查裝置2,或將檢查指示資訊D2儲存在USB記憶體等儲存媒體中,並使基板檢查裝置2讀入該儲存媒體,藉此能夠儲存在儲存部22中。
FIG. 14 is an explanatory diagram in a table format showing an example of the inspection instruction information D2 recorded as described above. The inspection instruction information D2 obtained in this way is sent to the
繼而,參照圖15說明上述基板檢查裝置2的運作。以下,以儲存部22儲存有圖14所示的檢查指示資訊D2的情況為例進行說明。
Next, the operation of the above-described
首先,檢查處理部21從檢查指示資訊D2對應一對地讀出表示導電部對的資訊(步驟S21)。接著,檢查處理部21一邊向所讀出的一對導電部間供給電流值I的測量用電流,一邊測量該導電部對間的電壓V(步驟S22)。接著,檢查處理部21基於電流值I和電壓V,以R=V/I的方式計算出作為檢查對象的導電部對間的電阻R(步驟S23)。
First, the
例如,檢查處理部21從圖14所示的檢查指示資訊D2讀出最初的導電部對P1、P2,向導電部對P1、P2之間的導電路徑a1流入測量用電流,計算導電部對P1、P2之間的電阻R(步驟S21~步驟S23)。
For example, the
接著,檢查處理部21檢查電阻R是否在預先設定的判定基準的範圍內(步驟S24)。判定基準例如可以設為檢查對象的
導電部對間的計算上的電阻值的-10%~+10%的範圍。
Next, the
如果電阻R在判定基準的範圍內(步驟S24中為是(YES)),則檢查處理部21判定為檢查對象的導電部對間的通孔V正常(步驟S25),並轉移至步驟S27。例如,如果導電部對P1、P2為檢查對象,則檢查處理部21判斷為與導電路徑a1上的分支M11、分支M12對應的通孔V11、通孔V21、通孔V12、通孔V22正常。再者,不一定需要確定通孔V,只要將檢查對象的導電部對間判斷為正常即可。
If the resistance R is within the range of the determination criterion (YES in step S24), the
另一方面,如果電阻R在判定基準的範圍之外(步驟S24中為否(NO)),則檢查處理部21判定為檢查對象的導電部對間的導電路徑不良(步驟S26),並轉移至步驟S27。例如,如果導電部對P1、P2為檢查對象,則檢查處理部21判斷為導電路徑a1不良。
On the other hand, if the resistance R is outside the range of the determination criterion (NO in step S24), the
在步驟S27中,檢查處理部21檢查檢查指示資訊D2的所有導電部對是否已完成檢查(步驟S27)。如果還有未檢查的導電部對(步驟S27中為否),則檢查處理部21從檢查指示資訊D2讀出新的導電部對(步驟S28),並再次重覆步驟S22~步驟S27。
In step S27, the
重覆所述步驟,若檢查指示資訊D2的所有導電部對都完成檢查(步驟S27中為是),則檢查處理部21結束檢查處理。
Repeating the above steps, if all conductive part pairs of the inspection instruction information D2 have completed inspection (YES in step S27), the
根據步驟S21~步驟S28的處理,測量對應於圖14所示的所有導電部對的導電路徑a1~導電路徑a4、導電路徑b1~導電路徑b4、導電路徑c1、導電路徑c2和導電路徑d1的電阻值R, 並且可以基於所述電阻值R檢查導電路徑a1~導電路徑a4、導電路徑b1~導電路徑b4、導電路徑c1、導電路徑c2和導電路徑d1中包括的通孔V。 According to the processing of steps S21 to step S28, the conductive paths a1 to a4, the conductive paths b1 to b4, the conductive paths c1, the conductive path c2 and the conductive path d1 corresponding to all pairs of conductive parts shown in FIG. 14 are measured. Resistance value R, And the via holes V included in the conductive paths a1 to a4, b1 to b4, c1, c2 and d1 can be checked based on the resistance value R.
即,本發明的一例所涉及的檢查指示資訊產生裝置是用以檢查基板的檢查指示資訊產生裝置,所述基板具備設置有多個導電部的表背一對基板面、積層於所述一對基板面之間的層即配線層、以及將所述配線層的配線和所述導電部連接的通孔,所述檢查指示資訊產生裝置具備:儲存部,儲存表示所述基板的所述導電部、所述配線、及所述通孔如何導通連接的導電結構資訊;以及檢查指示資訊產生部,執行檢查指示資訊產生處理,該檢查指示資訊產生處理基於所述導電結構資訊,使形成於同一所述基板面的所述導電部彼此成對地將所述導電部兩兩組合,並產生表示該組合後的一對導電部的資訊作為檢查指示資訊。 That is, an inspection instruction information generating device according to an example of the present invention is an inspection instruction information generating device for inspecting a substrate having a pair of front and back substrate surfaces provided with a plurality of conductive portions, and is laminated on the pair of substrate surfaces. A wiring layer is a layer between the substrate surfaces, and a through hole connects the wiring of the wiring layer to the conductive part. The inspection instruction information generating device includes a storage unit that stores the conductive part indicating the substrate. , the conductive structure information of how the wiring and the through-hole are connected; and the inspection instruction information generation unit performs inspection instruction information generation processing. The inspection instruction information generation processing is based on the conductive structure information, so that the inspection instruction information is formed in the same place. The conductive portions on the substrate surface are combined into pairs, and information representing the combined pair of conductive portions is generated as inspection instruction information.
另外,本發明的一個例子所涉及的檢查指示資訊產生方法是用於對基板進行檢查的檢查指示資訊產生方法,所述基板具備設置有多個導電部的表背一對基板面、積層於所述一對基板面之間的層即配線層、以及將所述配線層的配線和所述導電部連接的通孔,所述檢查指示資訊產生方法執行檢查指示資訊產生處理,該檢查指示資訊產生處理基於表示所述基板的所述導電部、所述配線、及所述通孔如何導通連接的導電結構資訊,使形成於同一所述基板面的所述導電部彼此成對地將所述導電部兩兩組合,並產生表示該組合後的一對導電部的資訊作為檢查指示資訊。 In addition, an inspection instruction information generating method according to an example of the present invention is a method for generating inspection instruction information for inspecting a substrate having a pair of front and back substrate surfaces provided with a plurality of conductive portions, which are laminated on the substrate. The wiring layer, which is a layer between the pair of substrate surfaces, and the through hole connecting the wiring of the wiring layer and the conductive part, the inspection instruction information generating method executes inspection instruction information generation processing, and the inspection instruction information generates The process is based on the conductive structure information indicating how the conductive portion, the wiring, and the through hole of the substrate are electrically connected, so that the conductive portions formed on the same substrate surface connect the conductive portions to each other in pairs. The parts are combined in pairs, and information representing the combined pair of conductive parts is generated as inspection instruction information.
另外,本發明的一個例子所涉及的檢查指示資訊產生程式是用於對基板進行檢查的檢查指示資訊產生程式,所述基板具備設置有多個導電部的表背一對基板面、積層於所述一對基板面之間的層即配線層、以及將所述配線層的配線和所述導電部連接的通孔,所述檢查指示資訊產生程式使電腦執行檢查指示資訊產生處理,該檢查指示資訊產生處理基於表示所述基板的所述導電部、所述配線、及所述通孔如何導通連接的導電結構資訊,使形成於同一所述基板面的所述導通部彼此成對地將所述導電部兩兩組合,並產生表示該組合後的一對導電部的資訊作為檢查指示資訊。 In addition, an inspection instruction information generating program according to an example of the present invention is an inspection instruction information generating program for inspecting a substrate having a pair of front and back substrate surfaces provided with a plurality of conductive portions, and is laminated on the substrate. The wiring layer is a layer between the pair of substrate surfaces, and a through hole connects the wiring of the wiring layer to the conductive part. The inspection instruction information generation program causes the computer to execute inspection instruction information generation processing. The inspection instruction The information generation process is based on the conductive structure information indicating how the conductive portion, the wiring, and the through hole of the substrate are conductively connected, so that the conductive portions formed on the same substrate surface are paired with each other. The conductive parts are combined in pairs, and information representing the combined pair of conductive parts is generated as inspection instruction information.
根據所述裝置、方法以及程式,藉由在同一基板面內的檢查,可以產生表示比背景技術中記載的方法更容易提高通孔的電阻測量精度的檢查部位的檢查指示資訊。 According to the above-mentioned device, method and program, through inspection within the same substrate surface, it is possible to generate inspection instruction information indicating an inspection location that is easier to improve the resistance measurement accuracy of the through hole than the method described in the background art.
另外,較佳為所述檢查指示資訊產生處理是如下處理:在將所述多個導電部兩兩組合時,藉由自該組合的一對導電部間的計算上的電阻值小的對開始依序組合,從而產生所述檢查指示資訊。 In addition, it is preferable that the inspection instruction information generating process is a process in which, when combining the plurality of conductive parts in pairs, starting from a pair with a smaller calculated resistance value between a pair of the combined conductive parts. Combined in sequence to generate the inspection instruction information.
成為檢查部位的一對導電部間的電阻值越小,通孔的電阻值占該導電部間的電阻值的比例增大的概率就越高,通孔以外的配線電阻的影響就越小。因此,以導電部對間的電阻值越小越優先的方式選擇導電部對的組合,藉此當進行由這樣獲得的檢查指示資訊指示的導電部對間的電阻測量來檢查通孔時,其檢查精 度提高。 The smaller the resistance value between a pair of conductive parts serving as the inspection site, the higher the probability that the ratio of the resistance value of the through hole to the resistance value between the conductive parts increases, and the smaller the influence of wiring resistance other than the through hole. Therefore, the combination of the conductive portion pairs is selected in such a way that the smaller the resistance value between the conductive portion pairs is, the higher the priority, whereby when the resistance measurement between the conductive portion pairs indicated by the inspection instruction information obtained in this way is performed to inspect the through hole, the combination of the conductive portion pairs is selected with priority. Check fine degree increased.
另外,較佳為所述檢查指示資訊產生處理是如下處理:當將所述多個導電部兩兩組合時,藉由自該組合的一對導電部間的在所述基板面上的距離短的對開始依序組合,而產生所述檢查指示資訊。 In addition, it is preferable that the inspection instruction information generating process is a process in which, when the plurality of conductive parts are combined in pairs, the distance between the combined pair of conductive parts on the substrate surface is short. The pairs are combined sequentially to generate the inspection instruction information.
基板面上的導電部對間的距離越短,該導電部對間的導電路徑長度短的可能性越高,因此電阻值低的可能性越高。另外,在自基板面上的距離短的對開始依序組合導電部的處理中,不需要計算導電部對間的導電路徑的電阻值,因此能夠減少處理量。因而,根據所述構成,能夠減少處理量並且以近似電阻值小的組合順序的優先順序來選擇導電部對。 The shorter the distance between the pairs of conductive parts on the substrate surface, the higher the possibility that the length of the conductive path between the pairs of conductive parts will be short, and therefore the higher the possibility that the resistance value will be low. In addition, in the process of sequentially combining the conductive parts starting from the pair with a short distance on the substrate surface, there is no need to calculate the resistance value of the conductive path between the pairs of conductive parts, so the processing amount can be reduced. Therefore, according to the above configuration, it is possible to select pairs of conductive portions in a priority order that approximates the order of combinations with small resistance values while reducing the amount of processing.
另外,較佳為所述檢查指示資訊產生處理是如下處理:在將所述多個導電部兩兩組合時,藉由自該組合的一對導電部間的導電路徑中包含的通孔的數量和配線的數量的合計少的對開始依序組合,而產生所述檢查指示資訊。 In addition, it is preferable that the inspection instruction information generating process is a process in which, when the plurality of conductive parts are combined in pairs, the number of through holes included in the conductive path between the pair of the combined conductive parts is determined. Pairs with a smaller total number of wirings are combined sequentially to generate the inspection instruction information.
導電部對中的導電部間的導電路徑所包含的通孔數量和配線數量的合計越少,該導電部對間的導電路徑長度短的可能性越高,因此電阻值低的可能性越高。另外,計數導電部間的導電路徑中包含的通孔的數量和配線數量的總和的處理不需要計算導電部對間的導電路徑的電阻值,因此可以減少處理量。因此,根據所述構成,能夠減少處理量並且以近似電阻值小的組合順序的優先順序來選擇導電部對。 The smaller the total number of via holes and the number of wirings included in the conductive path between the conductive portion pairs, the higher the possibility that the conductive path length between the conductive portion pair will be short, and therefore the resistance value will be low. . In addition, the process of counting the total number of via holes and the number of wirings included in the conductive path between the conductive parts does not require calculation of the resistance value of the conductive path between the conductive part pairs, so the processing amount can be reduced. Therefore, according to the above configuration, it is possible to select pairs of conductive portions in a priority order that approximates the order of combinations with small resistance values while reducing the amount of processing.
另外,較佳為所述檢查指示資訊產生部進而執行:搜索處理,基於所述導電結構資訊,搜索不位於在所述檢查指示資訊產生處理中組合的各對的自一個導電部到另一個導電部的導電路徑上的通孔;以及導電部追加處理,當在所述搜索處理中發現不位於所述導電路徑上的通孔時,基於所述導電結構資訊選擇位於包含該被發現的通孔的導電路徑的兩端的一對導電部,將表示該一對導電部的資訊追加到所述檢查指示資訊中。 In addition, it is preferable that the inspection instruction information generating unit further executes a search process for searching from one conductive portion to another conductive portion that is not located in each pair combined in the inspection instruction information generation process based on the conductive structure information. a through hole on the conductive path of the part; and a conductive part additional process, when a through hole that is not located on the conductive path is found in the search process, select the through hole that contains the discovered through hole based on the conductive structure information. A pair of conductive parts at both ends of the conductive path, and information indicating the pair of conductive parts is added to the inspection instruction information.
根據所述構成,在基於檢查指示資訊的檢查中減少了產生未經檢查的通孔的可能性。 According to the above configuration, the possibility of generating uninspected via holes during inspection based on the inspection instruction information is reduced.
另外,較佳為所述導電部追加處理是如下處理:從位於所述兩端的一對導電部中選擇滿足該導電部對間的計算上的電阻值為最小的條件的導電部對。 In addition, it is preferable that the conductive portion adding process is a process of selecting a pair of conductive portions from a pair of conductive portions located at the two ends that satisfies a condition that a calculated resistance value between the conductive portion pairs is the smallest.
根據所述構成,對於藉由導電部追加處理而追加的導電部對,亦選擇該導電部對間的計算上的電阻值小的導電部對,因此,在進行由檢查指示資訊指示的導電部對間的電阻測量來進行通孔的檢查時,其檢查精度提高。 According to the above configuration, even for the conductive portion pairs added by the conductive portion addition processing, the conductive portion pairs with the smaller calculated resistance values between the conductive portion pairs are selected. Therefore, the conductive portions indicated by the inspection instruction information are selected. When through-hole inspection is performed by measuring the resistance between pairs, the inspection accuracy is improved.
另外,較佳為所述導電部追加處理是如下處理:從位於所述兩端的一對導電部中選擇滿足在所述基板面上的距離最短的條件的導電部對。 In addition, it is preferable that the conductive portion adding process is a process of selecting a pair of conductive portions that satisfies a condition that the distance on the substrate surface is the shortest from a pair of conductive portions located at the both ends.
根據所述構成,對於藉由導電部追加處理而追加的導電部對,亦近似地選擇該導電部對間的計算上的電阻值小的導電部對,因此在進行由檢查指示資訊所指示的導電部對間的電阻測量 來進行通孔的檢查時,其檢查精度提高。 According to the above configuration, even for the conductive part pairs added by the conductive part addition processing, the conductive part pairs with the smaller calculated resistance values between the conductive part pairs are approximately selected. Therefore, the inspection instruction information indicates Resistance measurement between pairs of conductive parts When inspecting through holes, the inspection accuracy is improved.
另外,較佳為所述導電部追加處理是如下處理:從位於所述兩端的一對導電部中,選擇滿足所述導電部間的導電路徑所包含的通孔的數量與配線的數量的合計最少的條件的導電部對。 In addition, preferably, the conductive portion adding process is a process of selecting, from a pair of conductive portions located at both ends, a total number of through holes and a number of wirings included in the conductive path between the conductive portions. Minimal conditions for conductive parts.
根據所述構成,對於藉由導電部追加處理而追加的導電部對,亦近似地選擇該導電部對間的計算上的電阻值小的導電部對,因此在進行由檢查指示資訊所指示的導電部對間的電阻測量來進行通孔的檢查時,其檢查精度提高。 According to the above configuration, even for the conductive part pairs added by the conductive part addition processing, the conductive part pairs with the smaller calculated resistance values between the conductive part pairs are approximately selected. Therefore, the inspection instruction information is performed before the conductive part pairs are added. When through-hole inspection is performed by measuring the resistance between pairs of conductive parts, the inspection accuracy is improved.
另外,較佳為所述導電部追加處理是如下處理:在位於所述兩端的一對導電部中形成在同一基板面上的導電部彼此的導電部對中,優先選擇滿足所述條件的導電部對。 In addition, it is preferable that the conductive portion adding process is a process of preferentially selecting a conductive portion that satisfies the condition among a pair of conductive portions formed on the same substrate surface among a pair of conductive portions located at both ends. Right.
與跨基板的兩面進行電阻測量相比,在基板的一個面內進行電阻測量更不易受到雜訊的影響,因此電阻測量的精度提高。根據所述構成,優先選擇在同一基板面上形成的導電部彼此的導電部對,因此容易提高基於這樣得到的檢查指示資訊的檢查的精度。 Compared with measuring resistance across both sides of the substrate, measuring resistance within one face of the substrate is less susceptible to noise, so the accuracy of the resistance measurement is improved. According to the above configuration, a pair of conductive portions formed on the same substrate surface is preferentially selected, so it is easy to improve the accuracy of inspection based on the inspection instruction information obtained in this way.
另外,較佳為:所述基板更包括多個所述配線層、及連接所述多個配線層間的多個通孔,所述檢查指示資訊產生裝置更具備簡化處理部,該簡化處理部執行簡化處理,該簡化處理在所述多個配線層的配線並聯連接的情況下,以將該並聯連接的多根配線替換為一根配線的方式,變更所述導電結構資訊,所述檢查指示資訊產生部基於執行所述簡化處理的導電結構資訊,執行所 述搜索處理。 In addition, preferably, the substrate further includes a plurality of wiring layers and a plurality of through holes connecting the plurality of wiring layers, and the inspection instruction information generating device further includes a simplified processing unit that executes Simplification processing, which changes the conductive structure information and the inspection instruction information by replacing the plurality of parallel-connected wirings with one wiring when the wirings of the plurality of wiring layers are connected in parallel. The generation unit performs the above-mentioned conductive structure information based on the simplified processing Describe the search process.
根據所述構成,由於簡化了導電結構資訊,並且基於簡化的導電結構資訊執行搜索處理,因此搜索處理變得容易。 According to the above configuration, since the conductive structure information is simplified and the search process is performed based on the simplified conductive structure information, the search process becomes easy.
另外,較佳為所述簡化處理更包括如下處理:在藉由所述多個配線層的配線而並聯連接有所述通孔或通孔的行的情況下,以所述並聯連接的通孔或通孔的行被替換為一個通孔或一行通孔的方式,變更所述導電結構資訊。 In addition, it is preferable that the simplified process further includes a process of: when the via holes or rows of via holes are connected in parallel by wiring of the plurality of wiring layers, the via holes connected in parallel are Or the conductive structure information is changed by replacing the row of via holes with one via hole or a row of via holes.
根據所述構成,由於簡化了導電結構資訊,並且基於簡化的導電結構資訊執行搜索處理,因此搜索處理變得容易。 According to the above configuration, since the conductive structure information is simplified and the search process is performed based on the simplified conductive structure information, the search process becomes easy.
另外,較佳為所述檢查指示資訊產生裝置更包括樹狀結構資訊轉換部,所述樹狀結構資訊轉換部藉由使所述配線與節點對應、使所述通孔與分支對應、使所述面狀導體與根節點對應,將執行了所述簡化處理的導電結構資訊轉換為樹狀結構的資料結構,所述檢查指示資訊產生部基於轉換為所述樹狀結構的資料結構的導電結構資訊,執行所述搜索處理。 In addition, it is preferable that the inspection instruction information generating device further includes a tree structure information conversion unit that associates the wiring with the node and the through hole with the branch. The planar conductor corresponds to the root node, and the conductive structure information that has been subjected to the simplified process is converted into a data structure of a tree structure. The inspection instruction information generation unit is based on the conductive structure converted into the data structure of the tree structure. information to perform the search processing described.
根據所述構成,導電結構資訊被轉換為樹狀結構資料而被簡化,基於簡化的導電結構資訊執行搜索處理,因此搜索處理變得容易。 According to the above configuration, the conductive structure information is converted into tree structure data and simplified, and the search process is performed based on the simplified conductive structure information, so the search process becomes easy.
另外,本發明的基板檢查系統包括:上述的檢查指示資訊產生裝置;以及基板檢查裝置,基於由所述檢查指示資訊產生裝置產生的檢查指示資訊,執行所述通孔的檢查。 In addition, the substrate inspection system of the present invention includes: the above-mentioned inspection instruction information generating device; and a substrate inspection device that performs inspection of the through hole based on the inspection instruction information generated by the inspection instruction information generating device.
根據所述構成,基於表示比背景技術中記載的方法更容 易提高通孔的電阻測量精度的檢查部位的檢查指示資訊來執行通孔的檢查,因此容易提高通孔的電阻測量精度。 According to the above configuration, the representation-based method is easier to use than the method described in the background art. It is easy to improve the resistance measurement accuracy of the through hole by using the inspection instruction information of the inspection part to easily improve the resistance measurement accuracy of the through hole.
這樣構成的檢查指示資訊產生裝置、檢查指示資訊產生方法及檢查指示資訊產生程式能夠產生表示容易提高通孔的電阻測量精度的檢查部位的檢查指示資訊。另外,這種構成的基板檢查系統容易提高通孔的電阻測量精度。 The inspection instruction information generating device, the inspection instruction information generating method, and the inspection instruction information generating program configured in this way can generate inspection instruction information indicating an inspection portion that can easily improve the resistance measurement accuracy of a through hole. In addition, the substrate inspection system having such a structure can easily improve the resistance measurement accuracy of through holes.
本申請案是以2018年11月9日所申請的日本專利申請特願2018-211079為基礎者,其內容包含於本申請案中。再者,用於實施發明的方式的一項中所進行的具體的實施形方式或實施例始終是使本發明的技術內容變得明確者,本發明不應僅限定於此種具體例來狹義地進行解釋。 This application is based on Japanese Patent Application No. 2018-211079 filed on November 9, 2018, and its contents are included in this application. Furthermore, the specific embodiments or examples performed in one of the modes for carrying out the invention are always those that clarify the technical content of the invention, and the invention should not be narrowly limited to such specific examples. to explain.
1:基板檢查系統 1:Substrate inspection system
2:基板檢查裝置 2:Substrate inspection device
3:檢查指示資訊產生裝置 3: Check the instruction information generating device
4U、4L:測量治具 4U, 4L: Measuring fixture
20:控制部 20:Control Department
21:檢查處理部 21:Inspection Processing Department
22:儲存部 22:Storage Department
31:簡化處理部 31: Simplified processing department
32:樹狀結構資料轉換部 32:Tree structure data conversion department
33:檢查指示資訊產生部 33: Inspection instruction information generation department
34:儲存部 34:Storage Department
110:基板固定裝置 110:Substrate fixing device
112:框體 112:Frame
121:測量部 121:Measurement Department
122:測量部 122:Measurement Department
125:移動機構 125:Mobile mechanism
B:基板 B:Substrate
D1:導電結構資訊 D1: Conductive structure information
D2:檢查指示資訊 D2: Check instruction information
Pr:探針 Pr: probe
Claims (14)
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW452868B (en) * | 1998-03-27 | 2001-09-01 | Seiko Epson Corp | Semiconductor device, method for manufacturing the same, circuit board and electronic apparatus |
WO2008001651A1 (en) * | 2006-06-29 | 2008-01-03 | Nidec-Read Corporation | Board inspecting method and board inspecting device |
JP2010050155A (en) * | 2008-08-19 | 2010-03-04 | Denso Corp | Method of manufacturing semiconductor device, and inspecting device for semiconductor used therefor |
WO2018101234A1 (en) * | 2016-12-01 | 2018-06-07 | 日本電産リード株式会社 | Resistance measurement device and resistance measurement method |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03100475A (en) * | 1989-09-13 | 1991-04-25 | Nec Corp | Data forming system for conduction test of multilayer substrate |
JP3191467B2 (en) * | 1993-01-12 | 2001-07-23 | 松下電器産業株式会社 | Printed circuit board inspection data creation method |
JPH0943295A (en) | 1995-07-28 | 1997-02-14 | Toppan Printing Co Ltd | Method of inspecting through hole defect in printed wire board and apparatus therefor |
JP2005326193A (en) * | 2004-05-13 | 2005-11-24 | Hitachi Ltd | Substrate testing method |
JP4959942B2 (en) * | 2005-01-18 | 2012-06-27 | 日本電産リード株式会社 | Substrate inspection apparatus, substrate inspection program, and substrate inspection method |
JP4731339B2 (en) * | 2006-02-02 | 2011-07-20 | 日置電機株式会社 | Inspection device |
JP5463714B2 (en) * | 2009-04-02 | 2014-04-09 | 日本電産リード株式会社 | Substrate inspection method and substrate inspection apparatus |
JP5507430B2 (en) * | 2010-12-03 | 2014-05-28 | 日置電機株式会社 | Circuit board inspection equipment |
JP2013024582A (en) * | 2011-07-15 | 2013-02-04 | Nidec-Read Corp | Substrate checkup device and substrate checkup method |
JP6016415B2 (en) * | 2012-04-04 | 2016-10-26 | 日置電機株式会社 | Inspection data creation device and circuit board inspection device |
JP2018087754A (en) * | 2016-11-29 | 2018-06-07 | マイクロクラフト株式会社 | Inspection device and inspection method of printed wiring board |
JP2019007880A (en) | 2017-06-27 | 2019-01-17 | 日置電機株式会社 | Substrate inspection device and substrate inspection method |
-
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW452868B (en) * | 1998-03-27 | 2001-09-01 | Seiko Epson Corp | Semiconductor device, method for manufacturing the same, circuit board and electronic apparatus |
WO2008001651A1 (en) * | 2006-06-29 | 2008-01-03 | Nidec-Read Corporation | Board inspecting method and board inspecting device |
JP2010050155A (en) * | 2008-08-19 | 2010-03-04 | Denso Corp | Method of manufacturing semiconductor device, and inspecting device for semiconductor used therefor |
WO2018101234A1 (en) * | 2016-12-01 | 2018-06-07 | 日本電産リード株式会社 | Resistance measurement device and resistance measurement method |
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