TWI832455B - Microluminescent diode with dielectric frame and preparation method thereof - Google Patents

Microluminescent diode with dielectric frame and preparation method thereof Download PDF

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TWI832455B
TWI832455B TW111136993A TW111136993A TWI832455B TW I832455 B TWI832455 B TW I832455B TW 111136993 A TW111136993 A TW 111136993A TW 111136993 A TW111136993 A TW 111136993A TW I832455 B TWI832455 B TW I832455B
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dielectric frame
type doped
doped layer
metal electrode
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TW202414858A (en
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王曉靁
施能泰
宋高梅
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王曉靁
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Abstract

本發明提供一種具有介電質邊框的微發光二極體及其製備方法,該具有介電質邊框的微發光二極體包括:一n型摻雜層磊晶於一磊晶基板上;一介電質邊框形成於磊晶基板及n型摻雜層其中之一者上;一多重量子井層成長於介電質邊框中,且位於n型摻雜層上;一p型摻雜層成長於介電質邊框中,且位於多重量子井層上;一第一金屬電極導接於p型摻雜層;一第二金屬電極導接於n型摻雜層及磊晶基板其中之一者;以及一保護層覆於介電質邊框及透明電流分散層之外表面,並曝露出第一金屬電極及第二金屬電極;藉此有效避免平臺蝕刻所造成的瑕疵。 The invention provides a microluminescent diode with a dielectric frame and a preparation method thereof. The microluminescent diode with a dielectric frame includes: an n-type doped layer epitaxy on an epitaxial substrate; A dielectric frame is formed on one of the epitaxial substrate and the n-type doped layer; a multiple quantum well layer is grown in the dielectric frame and is located on the n-type doped layer; a p-type doped layer Grown in the dielectric frame and located on the multiple quantum well layer; a first metal electrode is connected to the p-type doped layer; a second metal electrode is connected to one of the n-type doped layer and the epitaxial substrate and a protective layer covering the outer surface of the dielectric frame and the transparent current dispersion layer, and exposing the first metal electrode and the second metal electrode; thereby effectively avoiding defects caused by platform etching.

Description

具有介電質邊框的微發光二極體及其製備方法 Microluminescent diode with dielectric frame and preparation method thereof

本發明係關於一種微發光二極體及其製備方法,特別係指一種具有介電質邊框的微發光二極體及其製備方法。 The present invention relates to a micro-luminescent diode and a preparation method thereof, in particular to a micro-luminescent diode with a dielectric frame and a preparation method thereof.

隨著時代的進步,顯示器變得更輕薄、更省電,顯示器主流技術已從新興的OLED顯示器,轉而積極投入微發光二極體(Micro light emitting diode,Micro-LED)顯示器,Micro LED顯示器由於具有自發光、低功耗、回應時間快、高亮度、超高對比、廣色域、廣視角、超輕薄、使用壽命長與適應各種工作溫度的諸多優異特性與可行性,在國際領導廠商的引領與產業界的積極參與之下,有望成為下一世代的顯示器的主流技術。Micro LED技術將一般毫米(10-3m)等級之傳統LED尺寸微縮至100微米(10-6m)以下,是原本LED體積的1%。但在生產組裝過程,需透過巨量轉移技術,將成長於磊晶基板(或稱為原生基板或同質基板)之微米等級RGB三色Micro LED晶粒搬運至顯示基板(或稱為目的基板)上,矩陣排列RGB畫素經由定址控制其暗亮程度而達成全彩化,才能形成完整的Micro LED顯示器。 With the advancement of the times, displays have become thinner, lighter and more power-saving. The mainstream display technology has shifted from the emerging OLED display to actively investing in Micro light emitting diode (Micro-LED) displays. Micro LED displays Due to its many excellent characteristics and feasibility of self-illumination, low power consumption, fast response time, high brightness, ultra-high contrast, wide color gamut, wide viewing angle, ultra-thin and light, long service life and adaptability to various operating temperatures, it is a leading international manufacturer. With the leadership of the industry and the active participation of the industry, it is expected to become the mainstream technology of the next generation of displays. Micro LED technology shrinks the size of traditional LEDs in the general millimeter (10 -3 m) class to less than 100 microns (10 -6 m), which is 1% of the original LED volume. However, during the production and assembly process, mass transfer technology is required to transfer the micron-level RGB three-color Micro LED chips grown on the epitaxial substrate (also known as the original substrate or the homogeneous substrate) to the display substrate (or the target substrate) On the other hand, matrix-arranged RGB pixels are addressed and controlled to achieve full color, thereby forming a complete Micro LED display.

然而前述的種種優勢,在考量巨量轉移過程中的複雜性與良率、產出效率的困擾,就形成關鍵挑戰和重大困擾。由於磊晶及分粒完成的晶粒尺寸相當袖珍,要將數以百萬計微米等級的Micro LED晶粒精準地轉移至顯示基板上的正確位置,就成為業界的技術障礙。 However, the above-mentioned advantages, combined with the complexity and yield and output efficiency problems in the mass transfer process, create key challenges and major troubles. Since the size of the die after epitaxy and graining is quite small, accurately transferring millions of micron-level Micro LED die to the correct position on the display substrate has become a technical obstacle for the industry.

為擺脫上述巨量轉移的難題,目前已經有人提出將RGB三種LED元件或至少其中兩種元件在同一磊晶基板上製造,並按照成品需求佈局的技術方案,申請人亦對此提出有相關前案。在Micro-LED的顯示器製造過程中,需採用紅綠藍(RGB)三原色發光二極體來構成單元的畫素(pixels),目前主要的製造技術需混和採用氮化物(Nitrides)系和磷化物(Phosphides)系的發光二極體,才能滿足三原色的需求。不同材料系統發光二極體混用時,不同的發熱及衰減特性直接影響了影像呈現的品質;不同的電氣驅動特性,則直接導致了顯示模組驅動設計上的複雜度。因此,如果在同一材料系統上,實現直接發光RGB(紅綠藍)三原色發光二極體,除了有利於上述問題解決外,也同時因為省去螢光物等色光轉換機制將降低工序複雜度以及轉換所致能效損失,將對Micro LED技術的發展更有利。 In order to get rid of the above-mentioned problem of massive transfer, some people have already proposed a technical solution to manufacture three RGB LED components or at least two of them on the same epitaxial substrate and lay them out according to the finished product requirements. The applicant has also proposed relevant precedents for this. case. In the manufacturing process of Micro-LED displays, three primary color light-emitting diodes of red, green and blue (RGB) are used to form the pixels of the unit. Currently, the main manufacturing technology requires a mixture of nitrides and phosphides. (Phosphides) series of light-emitting diodes can meet the needs of the three primary colors. When light-emitting diodes of different material systems are mixed, different heating and attenuation characteristics directly affect the quality of image presentation; different electrical driving characteristics directly lead to the complexity of display module drive design. Therefore, if a direct-emitting RGB (red, green, and blue) three-primary color light-emitting diode is realized on the same material system, it will not only help solve the above problems, but also reduce the complexity of the process and reduce the complexity of the process by eliminating the color light conversion mechanism such as phosphors. The loss of energy efficiency caused by conversion will be more beneficial to the development of Micro LED technology.

氮化銦鎵InxGa1-xN系磊晶材料是目前製作主流藍光發光二極體的材料系統之一,理論上可藉由銦鎵固溶比例調控覆蓋整個可見光發光範圍,氮化銦鎵受益於具有直接能隙(energy gap)特性也預期將有較佳的發光效能,尤其藍光量產技術純熟,因此受到比其他材料系統更多的關注,在製作具有近似控制條件同時效能佳的直接紅綠藍發光二極體(RGB direct LED)深具潛能。然而受限於基板,目前在InxGa1-xN系磊晶材料的紅光發光二極體卻面臨技術瓶頸,由於要達到紅光合適的發光波段時,需增加InxGa1-xN系磊晶的In含量比例,在磊晶製造工序上必須降以低磊晶溫度等方式增加In含量,卻面臨磊晶品質不符應用規格等阻礙。因此,在紅光InGaN基晶片技術成熟之前,紅光AlGaInP基晶片仍是直接發光晶片使用的主要選擇。 Indium gallium nitride InxGa1-xN epitaxial material is one of the material systems currently used to make mainstream blue light-emitting diodes. In theory, it can cover the entire visible light emission range by controlling the proportion of indium gallium solid solution. Indium gallium nitride benefits from its ability to Direct energy gap (energy gap) characteristics are also expected to have better luminous efficiency, especially blue light mass production technology is mature, so it has received more attention than other material systems. It is necessary to produce direct red, green and blue with similar control conditions and good performance. Light-emitting diodes (RGB direct LED) have great potential. However, limited by the substrate, red light-emitting diodes based on InxGa1-xN epitaxial materials are currently facing technical bottlenecks. To achieve a suitable luminous band for red light, the In content ratio of InxGa1-xN epitaxial materials needs to be increased. , in the epitaxial manufacturing process, it is necessary to increase the In content by reducing the epitaxial temperature, etc., but it faces obstacles such as the epitaxial quality does not meet the application specifications. Therefore, before the red-light InGaN-based wafer technology matures, the red-light AlGaInP-based wafer will still be the main choice for direct light-emitting wafers.

然而另方面,Micro-LED隨著晶粒尺寸大幅微縮,卻同時面臨外部量子效率(EQE,external quantum efficiency)急速下降的問題。Micro-LED元件尺寸需要微縮到小於5~10um才能達到較低成本水準,顯示器商品始能和 LCD、OLED display作價格上的競爭;現有一般尺寸藍光LED元件EQE水準達80%,然而,微縮到5~10um的藍光LED組件EQE通常僅20%或更低;這樣的EQE無法支援能超越LCD、OLED display效能的產品;因此,Micro-LED元件的低EQE問題必須要有效解決才能進入高度競爭的消費市場。 However, on the other hand, Micro-LEDs are facing the problem of rapid decline in external quantum efficiency (EQE) as the size of the crystal grains is greatly reduced. The size of Micro-LED components needs to be reduced to less than 5~10um in order to reach a lower cost level, and then display products can be LCD and OLED displays compete on price; the EQE level of existing general-sized blue LED components reaches 80%. However, the EQE of blue LED components shrunk to 5~10um is usually only 20% or lower; such EQE cannot support the ability to surpass LCD , OLED display performance products; therefore, the low EQE problem of Micro-LED components must be effectively solved in order to enter the highly competitive consumer market.

EQE低落問題的根源來自於晶片側壁存在顯著的缺陷效應;側壁缺陷包含結構損傷、外來汙染物以及空懸鍵(dangling bonds)等,這些缺陷將導致側壁表面發生Shockley-Read-Hall(SRH)非輻射載子復合效應。相關的研究與分析已經證實,這些晶片側壁缺陷主要由LED晶片的平臺蝕刻(mesa etch)造成,一般LED晶片標準蝕刻製程採用的是ICP RIE乾式蝕刻,其高能電漿體、離子轟擊與化學反應等在蝕刻後的側壁表面留下上述缺陷。一般尺寸LED元件側壁即存在前述缺陷導致的非輻射復合效應,隨著元件尺寸微縮,側壁表面積佔元件整體表面積比例隨之上升,側壁缺陷對元件整體發光效率影響也越發顯著,進入Micro-LED尺寸範圍不論是藍光及綠光InGaN基晶片或紅光AlGaInP基晶片均呈現EQE急速下降現象,尤其AlGaInP基晶片因為表面復合速率以及載子擴散長度(carrier diffusion length)均大於InGaN基晶片,EQE下降問題更顯著。 The root cause of the problem of low EQE comes from the significant defect effect on the sidewall of the wafer; sidewall defects include structural damage, foreign contaminants, and dangling bonds, etc. These defects will cause Shockley-Read-Hall (SRH) non-linearity on the sidewall surface. Radiation carrier recombination effect. Relevant research and analysis have confirmed that these wafer sidewall defects are mainly caused by mesa etch of LED wafers. Generally, the standard etching process of LED wafers uses ICP RIE dry etching, which uses high-energy plasma, ion bombardment and chemical reactions. The above-mentioned defects are left on the etched sidewall surface. The sidewalls of general-sized LED components have non-radiative recombination effects caused by the aforementioned defects. As the size of the component shrinks, the proportion of the sidewall surface area to the overall surface area of the component increases. The impact of sidewall defects on the overall luminous efficiency of the component becomes more and more significant. Entering the Micro-LED size Both blue and green InGaN-based wafers or red-light AlGaInP-based wafers show a rapid decline in EQE. In particular, AlGaInP-based wafers have a larger surface recombination rate and carrier diffusion length (carrier diffusion length) than InGaN-based wafers, so the EQE decreases. more significant.

Micro-LED晶粒面臨低EQE問題,主要來自於晶片平臺蝕刻(mesa etch)造成的側壁缺陷。目前最主要的改善方案,是將平臺蝕刻造成的缺陷,以鈍化層(passivation layer)披覆、或側壁表面的化學處理製程等後續的缺陷移除或修復製程加以彌補。其中,鈍化層披覆目前以原子層沉積(ALD,atomic layer deposition)Al2O3鈍化層效益獲得最佳成效,優於其他製程如PECVD和材料如SiO2的改善效益;鈍化層與改善組件光萃取率(LEE)的反射層(reflector)組合搭配也成為重要的研發主題;平臺蝕刻後的缺陷移除製程目前常以KOH或NH4S等進行化學處理;N2 plasma處理也是平臺蝕刻後的缺陷修復製程之一。 Micro-LED dies face low EQE problems, mainly due to sidewall defects caused by wafer platform etching (mesa etch). At present, the most important improvement plan is to make up for the defects caused by platform etching through subsequent defect removal or repair processes such as passivation layer coating or chemical treatment of sidewall surfaces. Among them, the passivation layer coating currently uses atomic layer deposition (ALD, atomic layer deposition) Al 2 O 3 passivation layer to achieve the best results, which is better than the improvement benefits of other processes such as PECVD and materials such as SiO2; the passivation layer is related to improving the optical properties of the component. The combination of reflector for extraction efficiency (LEE) has also become an important research and development topic; the defect removal process after platform etching is currently often chemically treated with KOH or NH4S; N 2 plasma treatment is also a defect repair after platform etching One of the manufacturing processes.

然而,前述各種技術方案都是等側壁缺陷已經形成之後,再以後續的額外製程進行缺陷移除或修復,都是增加工序、讓製程更複雜的方案,只會對於製造良率和產出效率造成進一步限制。如何提前避免平臺蝕刻造成側壁缺陷及損傷,而徹底消除EQE下降的問題,才能真正達到釜底抽薪的技術效果。 However, the various technical solutions mentioned above wait until the sidewall defects have been formed, and then use subsequent additional processes to remove or repair the defects. They are all solutions that increase the number of steps and make the process more complex, which will only affect the manufacturing yield and output efficiency. resulting in further restrictions. How to avoid sidewall defects and damage caused by platform etching in advance and completely eliminate the problem of EQE decline can truly achieve the technical effect of removing fuel from the bottom of the cauldron.

以下在實施方式中詳細敘述本發明之詳細特徵以及優點,其內容足以使任何熟習相關技藝者瞭解本發明之技術內容並據以實施,且根據本說明書所揭露之內容、申請專利範圍及圖式,任何熟習相關技藝者可輕易地理解本發明相關之目的及優點。 The detailed features and advantages of the present invention are described in detail below in the implementation mode. The content is sufficient to enable anyone skilled in the relevant art to understand the technical content of the present invention and implement it according to the content disclosed in this specification, the patent scope and the drawings. , anyone familiar with the relevant art can easily understand the relevant objectives and advantages of the present invention.

本發明之一目的在於提供一種具有介電質邊框的微發光二極體,藉由先成型介電質邊框,並在介電質邊框之中磊晶,藉此完全避免平臺蝕刻所造成Micro LED側壁的缺陷及損傷,而解決外部量子效率(EQE)急速下降的問題,進而提高Micro LED的發光效率。 One object of the present invention is to provide a micro-light emitting diode with a dielectric frame. By first forming the dielectric frame and epitaxying the dielectric frame, the Micro LED caused by platform etching can be completely avoided. Defects and damage on the side wall can be solved to solve the problem of rapid decline in external quantum efficiency (EQE), thereby improving the luminous efficiency of Micro LED.

本發明另一目的在於提供一種具有介電質邊框的微發光二極體,藉由先成型具有預定布局的介電質邊框,讓同一基板上的不同的框架內可磊晶不同色Micro LED晶粒,使單一基板上可形成多色晶粒,構成全彩畫素。 Another object of the present invention is to provide a micro-light emitting diode with a dielectric frame. By preforming the dielectric frame with a predetermined layout, different colors of Micro LED wafers can be epitaxially placed in different frames on the same substrate. grains, so that multi-color grains can be formed on a single substrate to form full-color pixels.

本發明再一目的在於提供一種具有介電質邊框的微發光二極體,可選擇內壁由上而下向內傾斜的介電質邊框,讓該多重量子井層及p型摻雜層於磊晶時的應力得到紓解。 Another object of the present invention is to provide a micro-light emitting diode with a dielectric frame. The dielectric frame can be selected with an inner wall that slopes inward from top to bottom, so that the multiple quantum well layer and the p-type doped layer can be The stress during epitaxy is relieved.

本發明又一目的在於提供一種具有介電質邊框的微發光二極體,可採用外側由上而下向外傾斜的介電質邊框,以提升光萃取效率(Light Extraction Efficiency)。 Another object of the present invention is to provide a micro-light-emitting diode with a dielectric frame, which can use a dielectric frame with an outer side tilting outward from top to bottom to improve light extraction efficiency (Light Extraction Efficiency).

本發明又另一目的在於提供一種具有介電質邊框的微發光二極體的製備方法,完全避免平臺蝕刻所造成Micro LED側壁的缺陷及損傷。 Yet another object of the present invention is to provide a method for preparing a micro-light emitting diode with a dielectric frame, which completely avoids defects and damage to the side walls of the Micro LED caused by platform etching.

本發明提供一種具有介電質邊框的微發光二極體,是供成形於一磊晶基板上,該微發光二極體包括:一n型摻雜層,磊晶於該磊晶基板上;一介電質邊框,形成於該磊晶基板及該n型摻雜層其中之一者上;一多重量子井層,成長於上述介電質邊框中,並且位於該n型摻雜層上;一p型摻雜層,成長於上述介電質邊框中,並且位於該多重量子井層上;一第一金屬電極,供導通電流至該p型摻雜層;一第二金屬電極,導接於該n型摻雜層及該磊晶基板其中之一者;以及一保護層,覆於該介電質邊框及該透明電流分散層之外表面,並曝露出該第一金屬電極及該第二金屬電極。 The invention provides a micro-luminescent diode with a dielectric frame, which is formed on an epitaxial substrate. The micro-luminescent diode includes: an n-type doped layer epitaxially formed on the epitaxial substrate; A dielectric frame is formed on one of the epitaxial substrate and the n-type doped layer; a multiple quantum well layer is grown in the dielectric frame and is located on the n-type doped layer ; A p-type doping layer, grown in the above-mentioned dielectric frame and located on the multiple quantum well layer; a first metal electrode for conducting current to the p-type doping layer; a second metal electrode for conducting current Connected to one of the n-type doped layer and the epitaxial substrate; and a protective layer covering the outer surface of the dielectric frame and the transparent current dispersion layer, and exposing the first metal electrode and the Second metal electrode.

該具有介電質邊框的微發光二極體之製備方法,其步驟包括:a)形成一介電質邊框和一n型摻雜層於一磊晶基板之上;b)於上述n型摻雜層上成長一多重量子井層,並且上述多重量子井層是位於介電質邊框中;c)於上述多重量子井層上成長一p型摻雜層,並且上述p型摻雜層是位於介電質邊框中;d)形成一第一金屬電極供導通電流至該p型摻雜層,且形成一第二金屬電極於該n型摻雜層及該磊晶基板其中之一者;以及形成一保護層,該保護層是覆於該介電質邊框及該透明電流分散層之外表面,並曝露出該第一金屬電極及該第二金屬電極。 The method for preparing a micro-light emitting diode with a dielectric frame includes the following steps: a) forming a dielectric frame and an n-type doped layer on an epitaxial substrate; b) adding the n-type doped layer to A multiple quantum well layer is grown on the doped layer, and the multiple quantum well layer is located in the dielectric frame; c) a p-type doped layer is grown on the multiple quantum well layer, and the p-type doped layer is located in the dielectric frame; d) forming a first metal electrode for conducting current to the p-type doped layer, and forming a second metal electrode on one of the n-type doped layer and the epitaxial substrate; and forming a protective layer covering the outer surface of the dielectric frame and the transparent current dispersion layer and exposing the first metal electrode and the second metal electrode.

依照本發明所揭露的具有介電質邊框的微發光二極體及其製備方法,其利用非晶質介電層如二氧化矽(SiO2)或氮化矽(Si3N4)先製作出適當的非晶質介電層邊框(frame),再於邊框內依序進行磊晶,故可以取代平臺蝕刻方式製造出的Micro-LED結構,而避免平臺蝕刻缺陷的效應產生,從源頭解 決Micro-LED之EQE急速下降的問題,不僅解決EQE急速下降的問題,有效提高Micro LED的發光效率,而且製程上的改良也使得產品良率和產出效率獲得提升,還可以在單一基板上形成多色晶粒,構成全彩畫素;尤其可以選擇介電質邊框形狀,同步解決製造和使用過程中的應力問題,並提升光萃取的效率。 According to the micro-light emitting diode with a dielectric frame and its preparation method disclosed in the present invention, an amorphous dielectric layer such as silicon dioxide (SiO2) or silicon nitride (Si3N4) is used to first produce an appropriate amorphous The crystalline dielectric layer frame is then sequentially epitaxyed within the frame, so it can replace the Micro-LED structure manufactured by platform etching, thereby avoiding the effects of platform etching defects and solving the problem from the source. Solving the problem of rapid decline in EQE of Micro-LED not only solves the problem of rapid decline in EQE and effectively improves the luminous efficiency of Micro LED, but also improves the product yield and output efficiency, and can also improve the product yield and output efficiency on a single substrate. Multi-color crystal grains are formed to form full-color pixels; in particular, the shape of the dielectric frame can be selected to simultaneously solve stress problems during manufacturing and use, and improve the efficiency of light extraction.

1、2、3、4:微發光二極體 1, 2, 3, 4: Micro-luminescent diodes

11、11’、21、31、41:磊晶基板 11, 11’, 21, 31, 41: Epitaxial substrate

12、12’、22、32、42:介電質邊框 12, 12’, 22, 32, 42: dielectric frame

13、13’、23、33、43:n型摻雜層 13, 13’, 23, 33, 43: n-type doped layer

14、14’、24、34、44:多重量子井層 14, 14’, 24, 34, 44: multiple quantum well layers

15、15’、25、35、45:p型摻雜層 15, 15’, 25, 35, 45: p-type doped layer

16、16’、26、36、46:透明電流分散層 16, 16’, 26, 36, 46: Transparent current dispersion layer

17、17’、27、37、47:第一金屬電極 17, 17’, 27, 37, 47: first metal electrode

18、18’、28、38、48:第二金屬電極 18, 18’, 28, 38, 48: second metal electrode

19、19’、29、39、49:保護層 19, 19’, 29, 39, 49: protective layer

51~57、51’~57’:步驟 51~57, 51’~57’: steps

120:凹穴 120:dent

圖1為本發明具有介電質邊框的微發光二極體之製備方法的第一較佳實施例的流程圖。 FIG. 1 is a flow chart of a first preferred embodiment of a method for manufacturing a micro-light emitting diode with a dielectric frame according to the present invention.

圖2A至圖2E為圖1實施例具有介電質邊框的微發光二極體製備過程中,各步驟的結構剖視示意圖。 2A to 2E are schematic structural cross-sectional views of each step in the preparation process of the micro-light emitting diode with a dielectric frame according to the embodiment of FIG. 1 .

圖3為本發明具有介電質邊框的微發光二極體之製備方法的第二較佳實施例的流程圖。 FIG. 3 is a flow chart of a second preferred embodiment of the method for manufacturing a micro-light emitting diode with a dielectric frame according to the present invention.

4A至圖4F為圖3實施例具有介電質邊框的微發光二極體製備過程中,各步驟的結構剖視示意圖。 4A to 4F are schematic structural cross-sectional views of each step in the preparation process of the micro-light emitting diode with a dielectric frame according to the embodiment of FIG. 3 .

圖5為本發明第三較佳實施例具有介電質邊框的微發光二極體的結構剖視示意圖。 FIG. 5 is a schematic cross-sectional view of the structure of a micro-light emitting diode with a dielectric frame according to the third preferred embodiment of the present invention.

圖6為本發明第四較佳實施例具有介電質邊框的微發光二極體的結構剖視示意圖。 6 is a schematic cross-sectional view of the structure of a micro-light emitting diode with a dielectric frame according to the fourth preferred embodiment of the present invention.

圖7為本發明第五較佳實施例具有介電質邊框的微發光二極體的結構剖視示意圖。 7 is a schematic cross-sectional view of the structure of a micro-light emitting diode with a dielectric frame according to the fifth preferred embodiment of the present invention.

藉由具體實施例說明本發明之實施方式,熟悉此技藝之人士可由說明書所揭示內容輕易瞭解本發明其他優點及功效。附圖繪示之結構、比例、大小等,均僅用以配合說明書所揭示內容,供熟悉此技藝人士瞭解與閱 讀,並非用以限定本發明實施之限定條件,不具技術上實質意義,任何結構修飾、比例關係改變或大小調整,在不影響本發明所能產生功效及所能達成目的下,均應仍落在本發明之內容的涵蓋範圍內。本說明書中所引用如“一”、“兩”、“上”等用語,亦僅為便於明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,亦視為本發明可實施之範疇。 Specific examples are used to illustrate the implementation of the present invention, and those familiar with the art can easily understand other advantages and effects of the present invention from the content disclosed in the specification. The structures, proportions, sizes, etc. shown in the accompanying drawings are only used to match the content disclosed in the instructions and are for the understanding and reading of those familiar with this art. are not intended to limit the implementation of the present invention and have no technical substantive significance. Any structural modifications, changes in proportions, or size adjustments should still fall within the scope of the present invention without affecting the effectiveness and purpose of the present invention. within the scope of the present invention. Terms such as "one", "two", and "top" cited in this specification are only for convenience of understanding and are not used to limit the scope of the present invention. Changes or adjustments in their relative relationships will not cause substantial changes. Under the technical content, it is also regarded as the scope within which the present invention can be implemented.

如圖1所示,本發明第一實施例具有介電質邊框微發光二極體1的製備方法及製備過程如下,首先在圖2A以藍寶石(sapphire)為例的磊晶基板11上於步驟51形成一n型氮化鎵(GaN)或n型氮化銦鎵(InGaN)之n型摻雜層13,以及在步驟52如圖2B所示,於n型摻雜層13上再形成一層例如SiO2或氮化矽(Si3N4)的介電質層,並如圖2C所示,蝕刻上述介電質層而形成凹穴120,由於介電質層被蝕刻出凹穴後,殘留的部分會構成用以限位後續磊晶架構的周壁,因此蝕刻後的介電質層被定名為介電質邊框12。 As shown in Figure 1, the preparation method and preparation process of the micro-light emitting diode 1 with a dielectric frame in the first embodiment of the present invention is as follows. First, on the epitaxial substrate 11 taking sapphire as an example in Figure 2A, the steps 51 forms an n-type doped layer 13 of n-type gallium nitride (GaN) or n-type indium gallium nitride (InGaN), and in step 52, as shown in Figure 2B, another layer is formed on the n-type doped layer 13 For example, a dielectric layer of SiO 2 or silicon nitride (Si 3 N 4 ), and as shown in FIG. 2C , the dielectric layer is etched to form a cavity 120 . After the cavity is etched out of the dielectric layer, The remaining portion will form the peripheral wall for limiting the subsequent epitaxial structure, so the etched dielectric layer is named dielectric frame 12 .

隨後在步驟53時,依照介電質邊框12的外框限制,在上述n型摻雜層13上、於凹穴120中磊晶成長例如氮化銦鎵(InGaN)系材料的一多重量子井層14作為主要的發光層;步驟54同樣受限於介電質邊框12的限制,如圖2D所示,於上述多重量子井層14上成長一p型氮化鎵(GaN)或p型氮化銦鎵(InGaN)作為一p型摻雜層15,此時的p型摻雜層15在高度方向是齊平於介電質邊框12。為使電流水平分散,使得電子電洞對復合位置不會過於集中在第一金屬電極17下方而造成遮光問題,步驟55在p型摻雜層15上方形成例如氧化銦錫(ITO)之一透明電流分散層16於該p型摻雜層15上。 Subsequently, in step 53, according to the outer frame constraints of the dielectric frame 12, a multiple quantum layer of a material such as indium gallium nitride (InGaN) is epitaxially grown on the n-type doped layer 13 in the cavity 120. The well layer 14 serves as the main light-emitting layer; step 54 is also limited by the dielectric frame 12. As shown in FIG. 2D, a p-type gallium nitride (GaN) or p-type gallium nitride (GaN) is grown on the multiple quantum well layer 14. Indium gallium nitride (InGaN) is used as a p-type doped layer 15. At this time, the p-type doped layer 15 is flush with the dielectric frame 12 in the height direction. In order to disperse the current horizontally so that the electron-hole pair recombination position will not be too concentrated under the first metal electrode 17 and cause light shielding problems, step 55 forms a transparent layer such as indium tin oxide (ITO) above the p-type doped layer 15 The current dispersion layer 16 is on the p-type doped layer 15 .

接著步驟56在上述疊層旁的介電質邊框12處形成另一凹穴(未標號)使得n型摻雜層13暴露,並填充金屬構成一導接至n型摻雜層13的第二金屬電極18,以及在透明電流分散層16上形成一第一金屬電極17,藉此構成一個 完整的LED迴路。最後在步驟57形成一個覆蓋介電質邊框12及透明電流分散層16上方的外表面的保護層19,並且曝露出第一金屬電極17及第二金屬電極18的頂端供導接。保護層19可以包括一鈍化層或一反射層,鈍化層的材料為氧化鋁(Al2O3)及二氧化矽(SiO2)其中一者,而反射層為一分散式布拉格反射器(DBR),用來提升微發光二極體1的光輸出效率。 Next, step 56 forms another cavity (not numbered) at the dielectric frame 12 next to the stack to expose the n-type doped layer 13, and fills it with metal to form a second cavity connected to the n-type doped layer 13. The metal electrode 18 and a first metal electrode 17 are formed on the transparent current dispersion layer 16, thereby forming a complete LED circuit. Finally, in step 57, a protective layer 19 is formed to cover the outer surface above the dielectric frame 12 and the transparent current dispersion layer 16, and the tops of the first metal electrode 17 and the second metal electrode 18 are exposed for conduction. The protective layer 19 may include a passivation layer or a reflective layer. The passivation layer is made of one of aluminum oxide (Al 2 O 3 ) and silicon dioxide (SiO 2 ), and the reflective layer is a distributed Bragg reflector (DBR). ), used to improve the light output efficiency of the micro-light emitting diode 1.

明顯地,由於多重量子井層和p型摻雜層都是被介電質邊框所框限而進行磊晶,因此排除平臺蝕刻技術以及附帶的側壁缺陷,從而克服EQE降低的技術難題,有效提升微發光二極體的發光效率。 Obviously, since the multiple quantum well layer and the p-type doping layer are bounded by the dielectric frame for epitaxy, the platform etching technology and the accompanying sidewall defects are eliminated, thereby overcoming the technical problem of reduced EQE and effectively improving Luminous efficiency of microluminescent diodes.

當然,如熟悉本技術領域人士所能輕易理解,在後續加工過程中,若有隔絕/鈍化/機械強度等需求,需要保留較寬的介電質邊框作為支持;但如圖3和圖4A至4F所示,本發明第二實施例具有與前一實施例相同的磊晶基板11’、n型摻雜層13’、介電質邊框12’、多重量子井層14’、p型摻雜層15’、透明電流分散層16’、第一金屬電極17’、第二金屬電極18’和保護層19’等結構,僅在步驟55’時,增加一進一步蝕刻介電質邊框12’的製程,使得介電質邊框12’的寬度較前一實施例的介電質邊框更窄,保護層19’因而包覆至介電質邊框12’外側,且第二金屬電極18’因而在高度方向延伸較低。 Of course, as those familiar with this technical field can easily understand, during subsequent processing, if there are requirements for isolation/passivation/mechanical strength, etc., a wider dielectric frame needs to be retained as support; however, as shown in Figure 3 and Figure 4A to As shown in 4F, the second embodiment of the present invention has the same epitaxial substrate 11', n-type doped layer 13', dielectric frame 12', multiple quantum well layer 14', p-type doped layer as the previous embodiment. layer 15', transparent current dispersion layer 16', first metal electrode 17', second metal electrode 18' and protective layer 19' and other structures, only in step 55', a step of further etching the dielectric frame 12' is added. The manufacturing process makes the width of the dielectric frame 12' narrower than that of the previous embodiment, so the protective layer 19' is covered to the outside of the dielectric frame 12', and the second metal electrode 18' is therefore at a height The direction extends lower.

此外,前述實施例中,介電質邊框是成形於n型摻雜層之上,但熟悉本技術領域人士所能輕易理解,如圖5本發明具有介電質邊框的微發光二極體2第三較佳實施例所示,介電質邊框22也同樣可以直接成型於例如藍寶石的磊晶基板21之上,並且讓n型摻雜層23和後續磊晶其上的多重量子井層24、以及p型摻雜層25,同樣磊晶成長於上述介電質邊框22所界定的環繞範圍中;透明電流分散層26則位於該p型摻雜層25上,且同樣高於上述介電質邊框22;第一金屬電極27是導接成型於該透明電流分散層26上;第二金屬電極28則導 接於該n型摻雜層23;以及一保護層29,覆於該介電質邊框22及該透明電流分散層26之外表面,並曝露出該第一金屬電極27及該第二金屬電極28。 In addition, in the foregoing embodiments, the dielectric frame is formed on the n-type doped layer, but people familiar with the art can easily understand that, as shown in Figure 5 of the micro-light emitting diode 2 with a dielectric frame of the present invention As shown in the third preferred embodiment, the dielectric frame 22 can also be directly formed on an epitaxial substrate 21 such as sapphire, and allow the n-type doping layer 23 and subsequent epitaxial multiple quantum well layers 24 thereon. , and the p-type doped layer 25, also epitaxially grows in the surrounding range defined by the above-mentioned dielectric frame 22; the transparent current dispersion layer 26 is located on the p-type doped layer 25, and is also higher than the above-mentioned dielectric frame 22 The solid frame 22; the first metal electrode 27 is conductively formed on the transparent current dispersion layer 26; the second metal electrode 28 is conductively formed. Connected to the n-type doped layer 23; and a protective layer 29 covering the outer surface of the dielectric frame 22 and the transparent current dispersion layer 26, and exposing the first metal electrode 27 and the second metal electrode 28.

請再參考圖6,本發明第四實施例具有介電質邊框的微發光二極體3,包括:一砷化鎵(GaAs)導電基板作為磊晶基板31;一n型摻雜層33,磊晶於該磊晶基板31上;一介電質邊框32,形成於該磊晶基板31上,且該n型摻雜層33位於該介電質邊框32中;一多重量子井層34,成長於上述介電質邊框32中,並且位於該n型摻雜層33上;一p型摻雜層35,成長於上述介電質邊框32中,並且位於該多重量子井層34上;一透明電流分散層36,位於該p型摻雜層35上;一第一金屬電極37,導接於該透明電流分散層36;一第二金屬電極38,導接於該磊晶基板31;以及一保護層39,覆於該介電質邊框32及該透明電流分散層36之外表面,並曝露出該第一金屬電極37及該第二金屬電極38。本例中,介電質邊框32的內壁是由上而下向內傾斜,藉此,讓該多重量子井層34及p型摻雜層35於磊晶時的應力得到紓解。 Please refer to Figure 6 again. The fourth embodiment of the present invention has a micro-light emitting diode 3 with a dielectric frame, including: a gallium arsenide (GaAs) conductive substrate as the epitaxial substrate 31; an n-type doped layer 33. Epitaxy is formed on the epitaxial substrate 31; a dielectric frame 32 is formed on the epitaxial substrate 31, and the n-type doping layer 33 is located in the dielectric frame 32; a multiple quantum well layer 34 , grown in the above-mentioned dielectric frame 32 and located on the n-type doped layer 33; a p-type doped layer 35, grown in the above-mentioned dielectric frame 32 and located on the multiple quantum well layer 34; A transparent current dispersion layer 36 is located on the p-type doped layer 35; a first metal electrode 37 is connected to the transparent current dispersion layer 36; a second metal electrode 38 is connected to the epitaxial substrate 31; And a protective layer 39 covers the outer surface of the dielectric frame 32 and the transparent current dispersion layer 36, and exposes the first metal electrode 37 and the second metal electrode 38. In this example, the inner wall of the dielectric frame 32 is inclined inward from top to bottom, thereby relieving the stress of the multiple quantum well layer 34 and the p-type doped layer 35 during epitaxy.

請再參考圖7,本發明第五實施例具有介電質邊框的微發光二極體4,包括:一磊晶基板41;一n型摻雜層43,磊晶於該磊晶基板41上;一介電質邊框42,形成於該n型摻雜層43上;一多重量子井層44,成長於上述介電質邊框42中,並且位於該n型摻雜層43上;一p型摻雜層45,成長於上述介電質邊框42中,並且位於該多重量子井層44上;一透明電流分散層46,位於該p型摻雜層45上;一第一金屬電極47,導接於該透明電流分散層46;一第二金屬電極48,導接於該n型摻雜層43;以及一保護層49,覆於該介電質邊框42、該n型摻雜層43及該透明電流分散層46之外表面,並曝露出該第一金屬電極47及該第二金屬電極48,本例中,不僅介電質邊框42的內壁是由上而下向內傾斜,可讓多重量子井層44及p型摻雜層45於磊晶時的應力得到紓解,且介電質邊框42的外側也是由上而下向外傾斜,藉此,有利於光萃取效率的提升。 Please refer to FIG. 7 again. The micro-light emitting diode 4 with a dielectric frame according to the fifth embodiment of the present invention includes: an epitaxial substrate 41; an n-type doped layer 43, which is epitaxially epitaxially formed on the epitaxial substrate 41. ; A dielectric frame 42 is formed on the n-type doped layer 43; a multiple quantum well layer 44 is grown in the dielectric frame 42 and is located on the n-type doped layer 43; a p Type doped layer 45 is grown in the dielectric frame 42 and is located on the multiple quantum well layer 44; a transparent current dispersion layer 46 is located on the p-type doped layer 45; a first metal electrode 47, Connected to the transparent current dispersion layer 46; a second metal electrode 48 connected to the n-type doped layer 43; and a protective layer 49 covering the dielectric frame 42 and the n-type doped layer 43 and the outer surface of the transparent current dispersion layer 46, and expose the first metal electrode 47 and the second metal electrode 48. In this example, not only the inner wall of the dielectric frame 42 is inclined inward from top to bottom, The stress of the multiple quantum well layer 44 and the p-type doped layer 45 during epitaxy can be relieved, and the outside of the dielectric frame 42 is also tilted outward from top to bottom, thereby benefiting the light extraction efficiency. promote.

雖然上述實施例中,在p型摻雜層上均形成有透明電流分散層,但熟悉本技術領域者可以輕易理解,當第一金屬電極本身就可以讓電流分布均勻且分散,亦可無須設置上述透明電流分散層,仍屬於本發明的權利範圍。且上述Micro LED晶粒在磊晶基板上製造完成後,亦可藉由雷射剝離(laser lift off,LLO)、磊晶基板研磨或濕蝕刻方式讓晶粒與磊晶基板分離,而後將原形成於磊晶基板上的Micro LED晶粒或Micro LED晶粒陣列進行移轉,因此,本發明所請求的範圍同時包括存在於磊晶基板上或已經從磊晶基板轉移後的Micro LED晶粒;此外亦可在Si3N4介電質邊框底部預先形成SiO2作為邊框蝕刻的停止層,然後再以濕蝕刻去除邊框內的SiO2以降低n磊晶層的乾式蝕刻損傷,凡是基於增進元件發光效能或特性的各項磊晶製程範圍內的相關措施均能相容於本發明的介電質邊框製程,例如超晶格(super lattice)、電子阻擋層(electron blocking layer,EBL)、融覆層(cladding layer)等,或多重量子井結構中導入特殊異質材料層作為應力作用或能帶工程(band engineering)之目的,此類變化仍均包括於本發明下列申請專利範圍中。 Although in the above embodiments, a transparent current dispersion layer is formed on the p-type doped layer, those familiar with the art can easily understand that the first metal electrode itself can make the current distribution uniform and dispersed, and there is no need to provide The above-mentioned transparent current dispersion layer still belongs to the scope of rights of the present invention. After the above-mentioned Micro LED chips are manufactured on the epitaxial substrate, the chips can also be separated from the epitaxial substrate by laser lift off (LLO), grinding of the epitaxial substrate, or wet etching, and then the original chips can be separated. The Micro LED dies or Micro LED die arrays formed on the epitaxial substrate are transferred. Therefore, the scope claimed by the present invention also includes the Micro LED dies that exist on the epitaxial substrate or have been transferred from the epitaxial substrate. ; In addition, SiO2 can be pre-formed at the bottom of the Si3N4 dielectric frame as a stop layer for the frame etching, and then the SiO2 in the frame can be removed by wet etching to reduce dry etching damage to the n-epitaxial layer. This is usually based on improving the luminous efficiency or characteristics of the device. Relevant measures within the scope of the epitaxial process are all compatible with the dielectric frame process of the present invention, such as super lattice, electron blocking layer (EBL), cladding layer layer, etc., or the introduction of special heterogeneous material layers into multiple quantum well structures for the purpose of stress or band engineering. Such changes are still included in the scope of the following patent applications of the present invention.

綜上所述,本發明具有介電質邊框的微發光二極體及其製備方法其具有該介電質邊框,因此能避免平臺蝕刻造成微發光二極體側壁的缺陷及損傷,而解決外部量子效率急速下降的問題,進而提高微發光二極體的發光效率。此外,該介電質邊框的內壁由上而下向內傾斜,如此可讓該多重量子井層及該p型摻雜層於磊晶時的應力得到紓解,且該介電質邊框的外側由上而下向外傾斜,則有利於光萃取效率的提升。 In summary, the micro-light-emitting diode with a dielectric frame and its preparation method of the present invention have the dielectric frame, so it can avoid defects and damage to the side walls of the micro-light-emitting diode caused by platform etching, and solve the problem of external The problem of rapid decline in quantum efficiency, thereby improving the luminous efficiency of micro-light-emitting diodes. In addition, the inner wall of the dielectric frame is inclined inward from top to bottom, which can relieve the stress of the multiple quantum well layer and the p-type doped layer during epitaxy, and the The outer side is tilted outward from top to bottom, which is beneficial to improving the light extraction efficiency.

上述實施例僅為例示性說明本發明的原理及其功效,而非用於限制本發明。即使是,因此任何熟悉此項技藝的人士可在不違背本發明的精神及範疇下,對上述實施例進行修改。因此本發明的權利保護範圍,應如後述申請專利範圍所列。 The above embodiments are only illustrative of the principles and effects of the present invention, but are not intended to limit the present invention. Even so, anyone skilled in the art can make modifications to the above embodiments without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention should be as listed in the patent application scope mentioned below.

1:發光二極體 1: Light emitting diode

11:晶基板 11: Crystal substrate

12:介電質邊框 12: Dielectric frame

13:n型摻雜層 13:n-type doped layer

14:多重量子井層 14:Multiple quantum well layers

15:p型摻雜層 15: p-type doped layer

16:透明電流分散層 16:Transparent current dispersion layer

17:第一金屬電極 17: First metal electrode

18:第二金屬電極 18: Second metal electrode

19:保護層 19:Protective layer

Claims (9)

一種具有介電質邊框的微發光二極體,是供成形於一磊晶基板上,該微發光二極體包括:一n型摻雜層,磊晶於該磊晶基板上;一介電質邊框,形成於該磊晶基板及該n型摻雜層其中之一者上;一多重量子井層,成長於上述介電質邊框中,並且位於該n型摻雜層上;一p型摻雜層,成長於上述介電質邊框中,並且位於該多重量子井層上;一第一金屬電極,供導通電流至該p型摻雜層;一位於該p型摻雜層和該第一金屬電極間之透明電流分散層,用以將上述第一金屬電極的電流分散至該p型摻雜層一第二金屬電極,導接於該n型摻雜層及該磊晶基板其中之一者;以及一保護層,覆於該介電質邊框及該透明電流分散層之外表面,並曝露出該第一金屬電極及該第二金屬電極。 A micro-luminescent diode with a dielectric frame is formed on an epitaxial substrate. The micro-luminescent diode includes: an n-type doped layer epitaxially formed on the epitaxial substrate; a dielectric A mass frame formed on one of the epitaxial substrate and the n-type doped layer; a multiple quantum well layer grown in the above-mentioned dielectric frame and located on the n-type doped layer; a p A doped layer grows in the dielectric frame and is located on the multiple quantum well layer; a first metal electrode is used to conduct current to the p-type doped layer; a first metal electrode is located between the p-type doped layer and the The transparent current dispersion layer between the first metal electrodes is used to disperse the current of the first metal electrode to the p-type doping layer and the second metal electrode, and is connected between the n-type doping layer and the epitaxial substrate. one; and a protective layer covering the outer surface of the dielectric frame and the transparent current dispersion layer, and exposing the first metal electrode and the second metal electrode. 如請求項1所述之具有介電質邊框的微發光二極體,其中該介電質邊框是設置於該磊晶基板上,以及該n型摻雜層是位於該介電質邊框中。 The micro-light emitting diode with a dielectric frame as claimed in claim 1, wherein the dielectric frame is disposed on the epitaxial substrate, and the n-type doped layer is located in the dielectric frame. 如請求項1所述之具有介電質邊框的微發光二極體,其中該第二金屬電極導接於該n型摻雜層時,該磊晶基板為一藍寶石(sapphire)基板,且該n型摻雜層的材料為n型氮化鎵(GaN)及n型氮化銦鎵(InGaN)其中之一者,該多重量子井層的材料為氮化銦鎵(InGaN),且該p型摻雜層的材料為p型氮化鎵(GaN)及p型氮化銦鎵(InGaN)其中之一者。 The micro-light emitting diode with a dielectric frame as described in claim 1, wherein when the second metal electrode is connected to the n-type doped layer, the epitaxial substrate is a sapphire substrate, and the The material of the n-type doped layer is one of n-type gallium nitride (GaN) and n-type indium gallium nitride (InGaN), the material of the multiple quantum well layer is indium gallium nitride (InGaN), and the p The material of the doped layer is one of p-type gallium nitride (GaN) and p-type indium gallium nitride (InGaN). 如請求項1所述之具有介電質邊框的微發光二極體,其中該第二金屬電極導接於該磊晶基板時,該磊晶基板為一砷化鎵(GaAs)導電基板,且 該n型摻雜層的材料為n型磷化鋁鎵銦(AlGaInP),該多重量子井層的材料為磷化鋁鎵銦(AlGaInP),且該p型摻雜層的材料為p型磷化鋁鎵銦(AlGaInP)。 The micro-light emitting diode with a dielectric frame as claimed in claim 1, wherein when the second metal electrode is connected to the epitaxial substrate, the epitaxial substrate is a gallium arsenide (GaAs) conductive substrate, and The material of the n-type doping layer is n-type aluminum gallium indium phosphide (AlGaInP), the material of the multiple quantum well layer is aluminum gallium indium phosphide (AlGaInP), and the material of the p-type doping layer is p-type phosphorus Aluminum gallium indium (AlGaInP). 如請求項1所述之具有介電質邊框的微發光二極體,其中該介電質邊框的內壁由上而下向內傾斜。 The micro-light emitting diode with a dielectric frame as described in claim 1, wherein the inner wall of the dielectric frame is inclined inward from top to bottom. 如請求項1所述之具有介電質邊框的微發光二極體,其中該介電質邊框的材料為二氧化矽(SiO2)及氮化矽(Si3N4)其中至少一者,該透明電流分散層的材料為氧化銦錫(ITO),該保護層包括一鈍化層或一反射層,該鈍化層的材料為氧化鋁(Al2O3)及二氧化矽(SiO2)其中之一者,且該反射層為一分散式布拉格反射器(DBR)。 The micro-light emitting diode with a dielectric frame as described in claim 1, wherein the material of the dielectric frame is at least one of silicon dioxide (SiO 2 ) and silicon nitride (Si 3 N 4 ), The transparent current dispersion layer is made of indium tin oxide (ITO). The protective layer includes a passivation layer or a reflective layer. The passivation layer is made of aluminum oxide (Al 2 O 3 ) and silicon dioxide (SiO 2 ). One of them, and the reflective layer is a distributed Bragg reflector (DBR). 一種具有介電質邊框的微發光二極體之製備方法,其步驟包括:a)形成一介電質邊框和一n型摻雜層於一磊晶基板之上;b)於上述n型摻雜層上成長一多重量子井層,並且上述多重量子井層是位於介電質邊框中;c)於上述多重量子井層上成長一p型摻雜層,並且上述p型摻雜層是位於介電質邊框中;以及d)形成一第一金屬電極供導通電流至該p型摻雜層,且形成一第二金屬電極於該n型摻雜層及該磊晶基板其中之一者;以及形成一保護層,該保護層是覆於該介電質邊框及該透明電流分散層之外表面,並曝露出該第一金屬電極及該第二金屬電極。 A method for preparing a micro-light emitting diode with a dielectric frame, the steps include: a) forming a dielectric frame and an n-type doped layer on an epitaxial substrate; b) forming the above n-type doped layer A multiple quantum well layer is grown on the doped layer, and the multiple quantum well layer is located in the dielectric frame; c) a p-type doped layer is grown on the multiple quantum well layer, and the p-type doped layer is located in the dielectric frame; and d) forming a first metal electrode for conducting current to the p-type doped layer, and forming a second metal electrode on one of the n-type doped layer and the epitaxial substrate ; and forming a protective layer that covers the outer surface of the dielectric frame and the transparent current dispersion layer and exposes the first metal electrode and the second metal electrode. 如請求項7所述之具有介電質邊框的微發光二極體之製備方法,其中上述步驟a)更包括a1)形成上述n型摻雜層於上述磊晶基板上,以及a2)形成該介電質邊框於該n型摻雜層上的次步驟。 The method for preparing a micro-light emitting diode with a dielectric frame as claimed in claim 7, wherein the above step a) further includes a1) forming the n-type doped layer on the epitaxial substrate, and a2) forming the A sub-step of placing a dielectric frame on the n-type doped layer. 如請求項7所述之具有介電質邊框的微發光二極體之製備方法,更包括在上述步驟c)和上述步驟d)之間,形成一透明電流分散層於該p型摻雜層上的步驟e),使得該透明電流分散層是介於該p型摻雜層和該第一金屬電極之間一,用以將上述第一金屬電極的電流分散至該p型摻雜層。 The method for preparing a micro-light-emitting diode with a dielectric frame as described in claim 7 further includes forming a transparent current dispersion layer on the p-type doped layer between the above-mentioned step c) and the above-mentioned step d). In step e) above, the transparent current dispersion layer is interposed between the p-type doped layer and the first metal electrode to disperse the current of the first metal electrode to the p-type doped layer.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200908369A (en) * 2007-08-03 2009-02-16 Chi Mei Lighting Tech Corp Light-emitting diode and manufacturing method thereof
TW202015254A (en) * 2018-06-26 2020-04-16 美商亮銳公司 Led utilizing internal color conversion with light extraction enhancements

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200908369A (en) * 2007-08-03 2009-02-16 Chi Mei Lighting Tech Corp Light-emitting diode and manufacturing method thereof
TW202015254A (en) * 2018-06-26 2020-04-16 美商亮銳公司 Led utilizing internal color conversion with light extraction enhancements

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