TWI822634B - Wafer level chip size packaging method - Google Patents

Abstract

The invention is a wafer-level chip size packaging method for producing a package. The package includes: a die, a dielectric layer and a bottom metal layer; wherein the die has a base and an active A plurality of welding pads are provided on the active surface, and there is a welding layer on the surface of each welding pad; the dielectric layer covers the upper part of the four side surfaces of the die, but does not cover the upper parts of each side surface. Lower part; the bottom metal layer is formed on the bottom surface of the substrate. The bottom metal layer can provide protection for the bottom surface of the die, and the heat energy generated by the die can also be dissipated to the outside through the bottom metal layer. The bottom metal layer has a better anti-electromagnetic interference (EMI) effect and can reduce the external environment. The interference of noise on the crystal grains.

Description

Wafer level chip size packaging method

The present invention relates to a wafer-level packaging component, in particular to a wafer-level chip-size package with better heat dissipation effect and anti-electromagnetic interference.

Please refer to the existing manufacturing method of Wafer Level Chip Scale Package (WLCSP) components shown in Figures 6A to 6F. In Figure 6A, a plurality of dies 502 (as shown by the dotted lines) are produced on the front side of a wafer 500. ), each die 502 is provided with a plurality of conductive bumps 504. The wafer 500 is first cut along the periphery of each die 502 to form a scribe line 506 that does not completely penetrate the wafer 500 .

In FIG. 6B , molding compound 508 is filled in each dicing lane 506 , and the molding compound 508 surrounds the conductive bumps 504 of each die 502 and covers the lower half of each conductive bump 504 . After the molding compound 508 is filled, a support film 510 is attached to the front side of the wafer 500 .

In FIG. 6C , the wafer 500 to which the support film 510 has been attached is turned over, and the backside of the wafer 500 is ground to reduce the thickness of the wafer 500 until the molding compound 50 filled in each dicing lane 506 is exposed. , as shown in the figure, the polishing thickness removed by polishing the wafer 500 is L.

In FIG. 6D , a backside protective layer 512 is attached to the backside of the polished wafer 500 to protect the backside of each die 502 . After the back protective layer 512 is attached, the support film 510 is removed.

In FIG. 6E , after the support film 510 is removed, a second cutting is performed along the periphery of each die 502 to completely cut through the molding compound 508 to obtain a plurality of wafer-level chip-sized packaging components 600 . Please refer to FIG. 6F . The wafer-level chip-size package component 600 obtained according to the above manufacturing method has a six-sided protective layer, that is, the molding compound 508 on the four peripheral surfaces of the die 502, the molding compound 508 on the top surface of the die 502, and a backside protective layer 512 on the bottom surface of die 502 .

Although there are protective layers on six sides of the die 502, because the molding compound 508 or the back protective layer 512 is made of insulating material epoxy resin, the heat dissipation effect is not good, and the heat energy generated by the die 502 is It is not easy to dissipate heat.

The present invention mainly provides a wafer-level chip-size package, which can have better heat dissipation effect and anti-electromagnetic interference effect.

In order to achieve the aforementioned objectives, the wafer-level chip size package of the present invention includes: A die has a base and an active surface, a plurality of soldering pads are provided on the active surface, and a soldering layer is provided on the surface of each soldering pad; A dielectric layer covering the upper portion of the four side surfaces of the die but not covering the lower portion of each side surface; the dielectric layer also covers the active surface of the die, and the dielectric layer The surface of the electrical layer is flush with the surface of the soldering pad; A bottom metal layer is formed on the bottom surface of the substrate.

The wafer-level chip size packaging method of the present invention includes: Provide a substrate on which a plurality of die are formed, wherein a plurality of bonding pads are formed on an active surface of each die; Forming a bottom metal layer on the bottom surface of the substrate; Perform a first cut on the substrate along the periphery of each grain to form a cutting track that does not completely penetrate the substrate; Filling the inside of each cutting lane with a dielectric material layer, and making the dielectric material layer cover the active surface of each die and be flush with the surface of the plurality of bonding pads; Perform a second cutting along the cutting lanes around each die, and cut through the substrate and the bottom metal layer to obtain a plurality of separated wafer-level chip-size packages, wherein the cutting width during the second cutting is less than The width of the dicing lane is such that the dielectric material layer remains on the four peripheral surfaces of each wafer-level chip-scale package, and the bottom surface of each wafer-level chip-scale package has the bottom metal layer.

The wafer-level chip-size package of the present invention has a bottom metal layer that can provide protection for the bottom surface of the die, and the heat energy generated by the die is dissipated outward through the bottom metal layer. Furthermore, compared with dielectric materials such as resin, the bottom metal layer can provide better anti-electromagnetic interference (EMI) effects and reduce the interference of external noise on the crystal grains.

Regarding the first embodiment of the manufacturing method of the present invention, please refer to Figures 1A to 1H. First, in Figure 1A, a substrate 10 is provided. The thickness of the substrate 10 is h. A plurality of crystals are produced on the substrate 10. Chip 12 (active device die/chip, as shown in the dotted box), wherein the substrate 10 is a wafer substrate, the material of which can be a silicon substrate or a substrate of other semiconductor materials, and an epitaxial layer 11 is formed on its surface , the component area of the die 12 can be fabricated in the epitaxial layer 11, wherein the surface of the epitaxial layer 11 serves as an active surface of the die 12, and several bonding pads 13 are formed on the active surface. .

As shown in FIG. 1B , a first metal layer 20 is formed on the back side of the substrate 10 . In one embodiment, the first metal layer 20 can be a metal layer of a single material (such as a copper layer) or a composite metal. The first metal layer 20 can be formed on the back side of the substrate 10 by deposition or electroplating. Taking the composite metal layer as an example, the composite metal layer includes a titanium layer 21 formed on the back side of the substrate 10 and a copper layer 22 formed on the titanium layer 21 in sequence.

As shown in FIG. 1C , a support film 200 is disposed on the bottom surface of the substrate 10 , and a first cutting operation is performed on the substrate 10 . The cutting technology may include dry etching, wet etching, and anisotropic using appropriate etchants. Etching or plasma etching; or the cutting technique may include a laser; or the cutting technique may include a mechanical process, such as using a knife to cut to a desired depth. During cutting, cutting is performed along the periphery of each die 12 but without completely cutting through the substrate 10 . The longitudinal depth d of the formed cutting track 14 may be smaller than the thickness h of the substrate 10 (d<h). In one embodiment, the width of the cutting lane 14 produced during the first cutting is W, for example, 40 μm.

As shown in FIGS. 1D and 1E , a hot-pressed layer 30 is bonded to the front side of the substrate 10 . The hot-pressed layer 30 has a multi-layer structure and includes a dielectric layer 31 and an isolation layer 32 . During lamination, the dielectric layer 31 faces the front side of the substrate 10 , and the isolation layer 32 is attached to the other surface of the dielectric layer 31 . The material of the dielectric layer 31 can be polypropylene (PP). , Ajinomoto build-up film (ABF), etc., the isolation layer 32 can be copper foil.

A second metal layer 40, such as copper, is bonded to the back side of the substrate 10. According to the manufacturing requirements of the product, the thickness of the second metal layer 40 is greater than the thickness of the aforementioned copper layer 22. For example, the thickness of the second metal layer 40 is 20~200 μm. In the figures shown after FIG. 1E , since the second metal layer 40 and the copper layer 22 are both made of copper material, a single second metal layer 40 is simplified in the figures.

As shown in FIG. 1F , after the front and back sides of the substrate 10 are bonded to the hot pressing layer 30 and the second metal layer 40 respectively, the substrate 10 is placed in a laminating equipment with appropriate pressure and temperature. 10 is heated and pressed on both sides, so that the dielectric layer 31 is melted and then flows and filled inside each cutting lane 14 and covers the active surface of each die 12 . During the hot pressing process, the uppermost isolation layer 32 can isolate the dielectric layer 31 to prevent the dielectric layer 31 from sticking to the pressing equipment, and can limit the overflow direction of the dielectric layer 31 so that it can flow into each cutting. Inside Lane 14.

As shown in FIG. 1G , after the hot pressing is completed, the isolation layer 32 on the surface of the substrate 10 is removed, for example, through a wet etching process to expose the bonding pad 13 of each die 12 . After the isolation layer 32 is removed, the surface of the dielectric layer 31 on the active surface of the die 12 is substantially flush with the surface of the bonding pad 13; and adjacent bonding pads 13 are insulated and isolated by the dielectric layer 31.

As shown in FIG. 1H , a soldering layer 50 is formed on the surface of each soldering pad 13 . In this embodiment, the soldering layer 50 is a metal protective film, such as through electroless plating (E'less) or electroless nickel plating. The metal protective film is formed on the surface of each soldering pad 13 by a manufacturing method such as immersion gold (ENIG). In another embodiment, the soldering layer 50 is a conductive solder ball electrically connected to the soldering pad 13 , as shown in FIG. 3 .

As shown in FIGS. 1I and 1J , another support film 200 is attached to the back of the substrate 10 and the substrate 10 is cut for a second time to obtain multiple individual wafer-level chip-size packages 100 . The second cutting operation cuts along the cutting lane 14 and completely cuts through the substrate 10 . The cutting width during the second cutting is smaller than the width W of the dicing lane 14 . For example, a tool with a width of 20 μm is used to cut along the center of the 40 μm dicing lane 14 , so that the surrounding edges of each wafer-level chip size package 100 The dielectric layer 31 with a thickness of nearly 10 μm is retained, and the dielectric layer 31 can completely protect the epitaxial layer 11 in the die.

As shown in Figure 2, the structure of each wafer-level package 100 includes:

A die 12 has a base 10 and an active surface. A plurality of soldering pads 13 are provided on the active surface, and a soldering layer 50 is formed on the surface of each soldering pad 13;

A dielectric layer 31 partially covers the four side surfaces of the substrate 10 and the active surface. The dielectric layer 31 located on each side surface covers the upper part of the side surfaces. The dielectric layer 31 is not The lower part of each side surface is covered, and the side surface of the dielectric layer 31 is flush with the side surface of the uncovered substrate 10; the surface of the dielectric layer 31 located on the active surface is flush with the surface of the soldering pad 13 flush; flush;

A bottom metal layer 70 is formed on the bottom surface of the die 12 , and the area is equal to the area of the bottom surface of the die 12 .

The bottom metal layer 70 may be a metal layer of a single material; or in another embodiment, the bottom metal layer 70 may be a composite metal layer, such as a titanium layer 21 and a copper layer 40 formed sequentially on the bottom surface of the substrate 10 . The bottom metal layer 70 not only serves as a substrate for carrying the die 12 , but also provides protection for the bottom surface of the die 12 , and the heat energy generated by the die 12 during operation is also more easily conducted to the bottom metal layer 70 through the bottom metal. Layer 70 dissipates heat to the outside. Furthermore, compared with dielectric materials such as resin, the bottom metal layer 70 can provide better anti-electromagnetic interference effect and reduce the interference of external noise on the die 12 .

Regarding the second embodiment of the manufacturing method of the present invention, the manufacturing process is shown in Figures 4A to 4K. The steps shown in Figures 4A to 4E are the same as the steps in Figures 1A to 1E in the first embodiment, so they will not be described again. After completing the steps of FIG. 4E , the substrate 10 that has been bonded with the hot pressing layer 30 and the second metal layer 40 is called a wafer unit A.

In Figure 4F, the present invention attaches two pieces of the wafer units A to each other in a back-to-back manner, and double-side bonds the second metal layer 40 of each wafer unit A through an adhesive bonding layer 60, wherein, The bonding layer 60 can be a thermal release film. After two pieces of the wafer unit A are relatively bonded, a thermal pressing operation is performed as shown in FIG. 4G , so that the dielectric layer 31 of each wafer unit A flows and fills the inside of each dicing lane 14 after being heated. And covers the active surface of each die 12 . In this embodiment, since the overall thickness can be increased by laminating the two wafer units A first, the chance of cracking of the wafer unit A can be reduced during the lamination operation in Figure 4G and the manufacturing quality of the product can be improved. Rate.

In FIG. 4H , after the hot pressing is completed, the two originally bonded wafer units A are separated and the bonding layer 60 is removed. In FIG. 4I , the isolation layer 32 of each wafer unit A is removed. For example, the isolation layer 32 is removed through a wet etching process and the bonding pad 13 of each die 12 is exposed. Similarly, on the wafer unit A, the isolation layer 32 is removed and the bonding pad 13 of each die 12 is exposed. The surface of the dielectric layer 31 on the active surface of the particle 12 will be approximately flush with the surface of the bonding pad 13 .

In FIG. 4J , a soldering layer 50 is formed on the surface of the bonding pad 13 of each chip 12 . In this embodiment, the soldering layer 50 is a metal protective film, such as through electroless plating (E'less) or electroless nickel plating. The soldering layer 50 is made on the surface of each soldering pad 13 by a manufacturing method such as immersion gold (ENIG); in other embodiments, the soldering layer 50 may be a conductive solder ball as shown in FIG. 3 . As shown in FIG. 4K , another support film is attached to the back of the substrate 10 and a second cutting operation is performed on the substrate 10 to obtain a plurality of wafer-level chip-size packages 100 . The second cutting operation is along the Cutting is performed at the position of the dicing lane 14 and completely cuts through the substrate 10 . The width of the knife used in the second cutting is smaller than the width W of the dicing lane 14 , so that each wafer-level chip size package 100 remains surrounded by The structure of the dielectric layer 31 and the wafer-level chip-scale package 100 is also as shown in FIG. 2 or FIG. 3 .

The third embodiment of the manufacturing method of the present invention is shown in Figures 5A to 5J. In Figure 5A, a substrate 10 is prepared. The thickness of the substrate 10 is h. A plurality of active device die/chips 12 (as shown in the dotted box) are produced on the substrate 10. Among them, in the An epitaxial layer 11 may be first formed on the surface of the substrate 10 , and the die 12 is fabricated on the epitaxial layer 11 . Several bonding pads 13 are formed on the active surface of each die 12 .

As shown in FIG. 5B , a first metal layer 20 is formed on the back side of the substrate 10 . In one embodiment, the first metal layer 20 is a composite metal layer, including a layer of metal layers formed on the back side of the substrate 10 in sequence. Titanium layer 21 and a copper layer 22, wherein the first metal layer 20 can be formed on the back of the substrate 10 by deposition or electroplating, and the thickness of the first metal layer 20 can be made into 20~200µm according to requirements. Copper layer 22.

As shown in FIG. 5C , a support film is provided on the bottom surface of the substrate 10 , and the first cutting operation is performed on the substrate 10 . During the cutting, the cutting is performed along the periphery of each crystal grain 12 but does not completely cut through the substrate 10 . , the depth d of the formed cutting track 14 may be smaller than the thickness h of the substrate 10 (d<h).

As shown in FIG. 5D , a hot-pressed layer 30 is bonded to the front side of the substrate 10 . The hot-pressed layer 30 includes a dielectric layer 31 and a release film layer 33 . During bonding, the dielectric layer 31 is Facing the front side of the substrate 10 , the release film layer 33 is attached to the surface of the dielectric layer 31 . The material of the dielectric layer 31 is Ajinomoto build-up film (ABF). Compared with the aforementioned first and second embodiments, this embodiment does not require a second metal layer on the back side of the substrate 10 .

As shown in FIG. 5E , the substrate 10 to which the hot pressing layer 30 has been bonded is defined as a wafer unit B.

In FIG. 5F , two pieces of the wafer units B are bonded to each other in a back-to-back manner, and the copper layer 22 of each wafer unit B is bonded on both sides through an adhesive bonding layer (thermal release film) 60 . After two pieces of the wafer unit B are relatively bonded, a heat pressing operation is performed as shown in FIG. 5G , so that the dielectric layer 31 of each piece of the wafer unit B flows and fills in each dicing lane 14 after being heat-melted. inside and covering the active surface of each die 12 . Because the overall thickness of the two wafer units B can be increased after being bonded first, the chance of cracking of each wafer unit B can be reduced during the lamination operation.

In FIG. 5H , after the hot pressing is completed, the two originally bonded wafer units B are separated and the bonding layer 60 is removed, and the release film layer 33 of each wafer unit B is torn off, and each wafer unit B is exposed. Similarly, the surface of the dielectric layer 31 on the active surface of the die 12 will be approximately flush with the surface of the bonding pad 13 .

In FIG. 5I , a soldering layer 50 is formed on the surface of the bonding pad 13 of each chip 12 . In this embodiment, the soldering layer 50 is a metal protective film, such as through electroless plating (E'less) or electroless nickel plating. The soldering layer 50 is made on the surface of each soldering pad 13 by a manufacturing method such as immersion gold (ENIG); in other embodiments, the soldering layer 50 may be a conductive solder ball as shown in FIG. 3 . As shown in FIG. 5JK , another support film is attached to the back of the substrate 10 and a second cutting operation is performed on the substrate 10 to obtain a plurality of wafer-level chip size packages 100 . The second cutting operation is along the Cutting is performed at the position of the dicing lane 14 and completely cuts through the substrate 10 . The width of the knife used in the second cutting is smaller than the width W of the dicing lane 14 , so that each wafer-level chip size package 100 remains surrounded by The structure of the dielectric layer 31 and the wafer-level chip-scale package 100 is also as shown in FIG. 2 or FIG. 3 .

In summary, the present invention can produce the "wafer-level chip size package 100" as shown in Figures 2 and 3 using the above-mentioned different manufacturing method embodiments. The bottom metal layer 70 can be produced by lamination, electroplating, Deposition or other methods can provide protection to the bottom surface of the die 12 , and the heat energy generated by the die 12 can be dissipated outward through the bottom metal layer 70 . Furthermore, compared with dielectric materials such as resin, the bottom metal layer 70 can provide better anti-electromagnetic interference (EMI) effects and reduce the interference of external noise on the die 12; and the surrounding sides and active surfaces of the die 12 The dielectric layer 31 can be covered and protected.

Although the present invention has been disclosed using the above-mentioned preferred embodiments, they are not intended to limit the invention. Anyone skilled in the art can make various changes and modifications to the above-described embodiments without departing from the spirit and scope of the invention. The technical scope protected by the invention, therefore, the scope of protection of the invention shall be determined by the appended patent application scope.

10: Base 11: Epitaxial layer 12:Grain 13: Solder pad 14: Cutting lane 20: First metal layer 21:Titanium layer 22: Copper layer 30:Hot pressed layer 31: Dielectric layer 32:Isolation layer 33: Release film layer 40: Second metal layer 50:Welding layer 60:Jointing layer 70: Bottom metal layer 100: Wafer level chip size package 200: Support film h: Thickness d: depth W: cutting width A,B:wafer unit 500:wafer 502:Grain 504: Conductive bumps 506: Cutting Road 508: Molding compound 510: Support film 512:Back protective layer 600: Wafer level chip size package L: grinding thickness

Figure 1A~Figure 1J: A schematic diagram of the manufacturing process of the first preferred embodiment of the present invention. Figure 2: A schematic three-dimensional cross-sectional view of the "wafer-level chip size package" of the present invention. Figure 3: A schematic cross-sectional view of another embodiment of the "wafer-level chip-scale package" of the present invention. Figure 4A ~ Figure 4K: A schematic diagram of the manufacturing process of the second preferred embodiment of the present invention. Figure 5A~Figure 5J: A schematic diagram of the manufacturing process of the third preferred embodiment of the present invention. Figure 6A ~ Figure 6F: Flow chart of the existing manufacturing method of wafer-level chip scale packaging (WLCSP) components.

100: Wafer level chip size package

10: Base

13: Solder pad

21:Titanium layer

31: Dielectric layer

40: Second metal layer

50:Welding layer

70: Bottom metal layer

Claims (7)

A wafer-level chip size packaging method includes: Make a wafer unit, including: Provide a substrate on which a plurality of die are formed, wherein a plurality of bonding pads are formed on an active surface of each die; forming a first metal layer on the bottom surface of the substrate; performing a first cut on the substrate along the periphery of each die to form a scribe line that does not completely penetrate the substrate; and A hot pressing layer and a second metal layer are respectively bonded to both sides of the substrate to form a wafer unit, wherein the hot pressing layer faces the dicing lane and includes a dielectric material layer; Two wafer units are relatively attached, wherein a bonding layer is used to bond the two wafer units between the second metal layers of the two wafer units; The two bonded wafer units are thermally pressed together, so that the dielectric material layer of each wafer unit is thermally melted and then filled in the dicing lane and covers the active surface of each die and is connected to the plurality of bonding pads. The surface is flush; Separate the two wafer units that have been thermally pressed; For each wafer unit, perform a second cutting along the cutting lane around each die, and cut through the substrate, the first metal layer, and the second metal layer to obtain a plurality of separated wafer-level chip sizes. Packages, in which the cutting width during the second cutting is smaller than the width of the cutting lane, so that the dielectric material layer is retained on the four peripheral surfaces of each wafer-level chip size package, and each wafer-level chip size package retains the dielectric material layer The bottom surface of the component has the first metal layer and the second metal layer. The wafer level die size packaging method as described in claim 1, wherein: The first metal layer is electroplated or deposited on the bottom surface of the substrate, and the first metal layer includes a titanium layer and a copper layer; The second metal layer is a copper layer; The hot-pressed layer includes the dielectric material layer and an isolation layer. In the step of hot-pressing the hot-pressed layer and the second metal layer, the dielectric material layer faces the dicing lane, and the isolation layer is a copper foil; Before performing a second cutting along the cutting lane around each die, it further includes etching to remove the isolation layer. The wafer level die size packaging method as described in claim 1, wherein: Before performing the second cutting along the cutting lane around each die, it further includes: forming a soldering layer on the surface of each soldering pad. The wafer-level chip size packaging method according to claim 3, wherein the soldering layer is a metal protective film or a conductive solder ball. A wafer-level chip size packaging method includes: Make a wafer unit, including: Provide a substrate on which a plurality of die are formed, wherein a plurality of bonding pads are formed on an active surface of each die; forming a first metal layer on the bottom surface of the substrate; performing a first cut on the substrate along the periphery of each die to form a scribe line that does not completely penetrate the substrate; and Laminating a hot-pressed layer on the substrate to form one of the wafer units, wherein the hot-pressed layer faces the dicing lane and includes a dielectric material layer; Two wafer units are relatively attached, wherein a bonding layer is used to bond the two wafer units between the first metal layers of the two wafer units; The two bonded wafer units are thermally pressed together, so that the dielectric material layer of each wafer unit is thermally melted and then filled in the dicing lane and covers the active surface of each die and is connected to the plurality of bonding pads. The surface is flush; Separate the two wafer units that have been thermally pressed; For each wafer unit, perform a second cutting along the cutting lane around each die, and cut through the substrate and the first metal layer to obtain a plurality of separated wafer-level chip-size packages, wherein the second The cutting width during the first cutting is smaller than the width of the cutting lane, so that the dielectric material layer is retained on the four side surfaces of each wafer-level chip-sized package, and the bottom surface of each wafer-level chip-sized package has the third A metal layer. The wafer level chip size packaging method as described in claim 5, wherein: The first metal layer is electroplated or deposited on the bottom surface of the substrate, and the first metal layer includes a titanium layer and a copper layer; The hot-pressed layer includes the dielectric material layer and a release film layer. In the step of hot-pressing the hot-pressed layer, the dielectric material layer faces the cutting lane and the dielectric material layer is Ajinomoto accumulation film (ABF); Before performing the second cutting along the cutting lane around each die, the method further includes: tearing off the release film layer. The wafer level chip size packaging method as described in claim 5, wherein: Before performing the second cutting along the cutting lane around each die, it further includes: forming a soldering layer on the surface of each soldering pad.