TWI818638B - 替代埋入式電源軌 - Google Patents
替代埋入式電源軌 Download PDFInfo
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- TWI818638B TWI818638B TW111127693A TW111127693A TWI818638B TW I818638 B TWI818638 B TW I818638B TW 111127693 A TW111127693 A TW 111127693A TW 111127693 A TW111127693 A TW 111127693A TW I818638 B TWI818638 B TW I818638B
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- 239000004065 semiconductor Substances 0.000 claims abstract description 81
- 238000000034 method Methods 0.000 claims description 46
- 238000005530 etching Methods 0.000 claims description 20
- 239000000853 adhesive Substances 0.000 claims description 16
- 230000001070 adhesive effect Effects 0.000 claims description 16
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- 239000010949 copper Substances 0.000 claims description 4
- 230000005669 field effect Effects 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
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- 238000000151 deposition Methods 0.000 claims description 3
- 229910052707 ruthenium Inorganic materials 0.000 claims description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
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- 229910052682 stishovite Inorganic materials 0.000 description 14
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 8
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- 238000000231 atomic layer deposition Methods 0.000 description 2
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- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
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Classifications
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/743—Making of internal connections, substrate contacts
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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Abstract
本文中所揭示之實施例描述一種半導體結構。該半導體結構可包括具有一第一源極/汲極(S/D)及一第二S/D之一裝置區。該半導體結構亦可包括在該裝置區下方之一埋入式電源軌(BPR)。該BPR之一臨界尺寸可大於該第一S/D與該第二S/D之間的一距離。該半導體結構亦可包括在該BPR與該S/D之間的一通路接觸件至埋入式電源軌(VBPR)。
Description
本發明大體上係關於半導體裝置製造之領域,且更特定地係關於藉由在較早製造階段時形成具有小尺寸之虛設埋入式電源軌且在稍後製造階段時移除虛設埋入式電源軌之後增大尺寸來形成臨界尺寸增大之埋入式電源軌。
在製造半導體裝置時,數百萬個裝置可一起位於單一基板上。對此等數百萬個裝置之有用的控制依賴於將電信號施加至特定裝置,同時使電信號絕緣以免與任何其他者(例如其他裝置)形成短路。在標準邏輯單元內,後段製程(BEOL)金屬層中之電源軌將電流遞送至給個別裝置(例如電晶體)供電之源極/汲極。電源軌相比於標準路由軌道/信號線載運較高電流以維持適當的電源分配目標,且因此需要單元中之較大空間。在許多設計中,電源軌可比正常路由線大四倍。
減小電源軌之側向尺寸且將豎直尺寸較深地延伸至單元中可使電源軌中之總金屬體積保持高,同時為其他組件騰出空間。然而,增大電源軌之深度可造成較高通路電阻,或可使信號線在BEOL中之軌道之間載運增大之電容。在實體裝置(例如電晶體)底下埋入電源軌會使電源軌之深度能夠獨立於BEOL中之信號線而增大。埋入式電源軌(BPR)經由電源軌提供顯著較低的電阻,而不會給BEOL中之通路電阻或電容帶來任何負面影響。
根據本發明之一個實施例,揭示一種半導體結構。該半導體結構可包括具有一第一源極/汲極(S/D)及一第二S/D之一裝置區。該半導體結構亦可包括在該裝置區下方之一埋入式電源軌(BPR)。該BPR之一臨界尺寸可大於該第一S/D與該第二S/D之間的一距離。該半導體結構亦可包括在該BPR與該S/D之間的一通路接觸件至埋入式電源軌(via-contact-to-buried power rail;VBPR)。
根據本發明之一個實施例,揭示一種方法。該方法可包括:在一第一鰭片場效電晶體(FET)與一第二鰭片FET之間的一絕緣體層中形成一虛設埋入式電源軌(BPR);形成電連接至該第一鰭片FET之一第一源極/汲極(S/D)及電連接至該第二鰭片FET之一第二S/D;形成接觸該虛設BPR及該第一S/D之一頂部表面之一通路接觸件至埋入式電源軌(VBPR);自與該頂部表面相對之一底部表面選擇性地蝕刻該虛設BPR以形成一BPR溝槽;加寬該BPR溝槽;及金屬化該BPR溝槽以形成一BPR。
根據本發明之一個實施例,揭示一種半導體結構。該半導體結構可包括:一背側電源遞送網路(BSPDN);一埋入式電源軌(BPR),其耦接至該BSPDN;一通路接觸件至埋入式電源軌(VBPR),其耦接至該BPR,其中該BPR環繞該VBPR之一底部;一第一源極/汲極(S/D),其耦接至該VBPR之一中部;及一後段製程層,其耦接至該VBPR之一頂部。
在以下詳細描述中,參考隨附圖式,該等隨附圖式展示本發明之實施例之特定實例。足夠詳細地描述此等實施例以使熟習此項技術者能夠實踐該等實施例,且應理解,在不脫離所描述之實施例的情況下,可利用其他實施例且可進行結構、邏輯及電改變。因此,以下詳細描述不應被視為限制性意義,且所包括之實施例由所附申請專利範圍界定。
本文中揭示所主張之結構及方法之詳細實施例;然而,應理解,所揭示之實施例僅說明可以各種形式體現之所主張之結構及方法。另外,結合各種實施例給出之實例中之各者意欲為說明性而非限制性的。此外,各圖未必按比例,可誇示一些特徵以展示特定組件之細節。因此,本文中所揭示之特定結構及功能細節不應被解譯為限制性的,而僅為用於教示熟習此項技術者以各種方式使用本發明之方法及結構的代表性基礎。亦應注意,相同及對應元件由相同附圖標號指代。
在以下描述中,闡述眾多特定細節,諸如特定結構、組件、材料、尺寸、處理步驟及技術,以便提供對本申請案之各種實施例的理解。然而,一般熟習此項技術者應瞭解,可在無此等特定細節的情況下實踐本申請案之各種實施例。在其他例項中,尚未詳細地描述熟知的結構或處理步驟以避免混淆本申請案。
本說明書中對「一個實施例」、「一實施例」、「一實例實施例」等之參考指示所描述之實施例可包括特定特徵、結構或特性。此外,此類片語未必係指同一實施例。此外,當結合一實施例來描述一特定特徵、結構或特性時,應主張,無論是否予以明確描述,結合其他實施例實現此類特徵、結構或特性係在熟習此項技術者之認識範圍內。
在下文中出於描述之目的,術語「右側」、「左側」、「豎直」、「水平」、「頂部」、「底部」及其衍生詞應與所揭示之結構及方法相關,如繪圖中所定向。術語「上覆」、「頂上」、「定位於……上」或「定位於……頂上」意謂諸如第一結構之第一元件存在於諸如第二結構之第二元件上,其中諸如界面結構之介入元件可存在於第一元件與第二元件之間。術語「直接接觸」意謂諸如第一結構之第一元件與諸如第二結構之第二元件在兩個元件之界面處無任何中介導電、絕緣或半導體層的情況下連接。
應理解,當諸如層、區或基板之元件被稱為在另一元件「上」或「上方」時,其可直接在另一元件上或亦可存在介入元件。與此對比,當一元件被稱為「直接在另一元件上」或「直接在另一元件上方」時,不存在介入元件。亦應理解,當一元件被稱為在另一元件「之下」或「下方」時,該元件可直接在另一元件之下或下方,或可存在介入元件。與此對比,當一元件被稱為「直接在另一元件之下」或「直接在另一元件下方」時,不存在介入元件。
關於電晶體及積體電路之製造,主表面係指半導體層之例如在平面製程中在其中及其周圍製造有複數個電晶體的表面。如本文中所使用,術語「豎直」意謂相對於主表面實質上正交,且「水平」意謂實質上平行於主表面。通常,主表面沿著製造有電晶體裝置之單晶矽層之平面。
對於積體電路,裝置組件之遮蔽、圖案化及蝕刻使得有可能在微米及奈米尺度下製造半導體裝置。然而,隨著裝置、組件及層之大小及間距不斷地減小,過去已使用之蝕刻技術可造成非預期結果。作為一特定實例,半導體結構之埋入式電源軌可遭受在退火製程期間造成之熱不穩定性。埋入式電源軌中存在之任何金屬可在後續FEOL熱處理期間遇到問題,諸如金屬遷移及金屬擴散,同時半導體結構經加熱以進行退火。另外或替代地,半導體結構可歸因於在加熱期間金屬之膨脹及收縮而對晶圓施加應力及/或使晶圓曲折。此非想要的應力/曲折可能會在後續遮罩層級中引起微影未對準誤差。
下文所揭示之裝置及方法解決了與使半導體結構及埋入式電源軌退火相關聯之問題。因此,本文中所揭示之實施例製造稍後在製造製程中由經金屬化埋入式電源軌替代之虛設埋入式電源軌,而非就在鰭片形成之後形成具有金屬之埋入式電源軌。
圖1為根據本發明之一個實施例的半導體結構100之示意性橫截面側視圖。示意圖展示列102,其可包括被製造為最終變成場效電晶體(FET)區(例如n型FET (NFET)及p型FET (PFET))之部分的鰭片104。半導體結構100之所繪示實施例包括四個FET區:第一NFET區106a、第二NFET區106b、第一PFET區106c及第二PFET區106d。鰭片104製造於基板108及BOX SiO2層110上,且包括用於經由半導體結構100之裝置區控制信號的層112。層112可藉由在介電層110上方之最底部半導體層上方依序地形成磊晶半導體層而製造。在一個實施例中,起始晶圓為絕緣體上矽(SOI)晶圓。基板108可為矽,且在基板108上方存在BOX SiO2層110。在某些實施例中,額外矽層(未圖示)可製造於BOX SiO2層110上方。首先,將上方之額外矽層薄化至約5 nm至10 nm,接著生長SiGe層且進行SiGe冷凝製程以將BOX上方之最底部半導體層轉換成SiGe。此後,移除SiGe上方之氧化物,接著移除替代性Si層且進行SiGe層生長。此後,沈積硬式遮罩114。將圖案化製程應用於硬式遮罩以藉由習知微影及蝕刻製程來界定主動區。接著,可蝕刻掉不受硬式遮罩114保護之層112之區域以形成鰭片104。儘管未繪示,但可在垂直於所繪示方向之方向上側向地切割層112,使得半導體結構100可包括沿著行(亦即,進入頁面及離開頁面)之若干鰭片104。接著將鰭片104之間的開放空間填充有諸如SiO2之介電質116,或SiN及SiO2層之組合。接著可例如運用化學機械平坦化(CMP)來平坦化半導體結構100。
圖2為根據本發明之一個實施例的在後續製造階段時圖1之半導體結構100之示意性橫截面側視圖。圖2展示經蝕刻通過半導體結構100之長度(亦即,進入頁面及離開頁面)的埋入式電源軌(BPR)溝槽118a、118b。由於BPR溝槽118a、118b沿著半導體結構100之長度為連續的,故BPR溝槽118a、118b可經圖案化為沿著進入頁面及離開頁面之方向通過若干或所有鰭片104的線形狀。BPR溝槽118a、118b可使用習知微影及蝕刻製程而圖案化,且可使用不同硬式遮罩(未繪示)而圖案化。首先,可圖案化(例如使用微影及蝕刻製程)硬式遮罩,使得隨後可經由蝕刻製程形成BPR溝槽118a、118b。在一些實施例中,此蝕刻可使用諸如反應性離子蝕刻(RIE)之異向性蝕刻來執行。BPR溝槽118a、118b可經蝕刻通過氧化物116、BOX SiO2層110,且可部分地切割至基板108中。BPR溝槽118a、118b不需要大寬度120。較窄BPR溝槽118a、118b有助於保護鰭片104免受BPR圖案化製程的損壞,甚至在微影未對準之最差情況下亦如此。
BPR溝槽118a、118b形成於FET區106a至106d之間。在圖2之所繪示實施例中,第一BPR溝槽118a形成於兩者均為NFET區之第一FET區106a與第二FET區106b之間。同樣地,第二BPR溝槽118b形成於兩者均為PFET區之第三FET區106c與第四FET區106d之間。可構想BPR溝槽118a、118b形成於在裝置類型方面不同之FET區之間的其他實施例。
圖3為根據本發明之一個實施例的在後續製造階段時圖1之半導體結構100之示意性橫截面側視圖。半導體結構100在各BPR溝槽118a、118b內包括虛設埋入式電源軌(BPR) 122a、122b。虛設BPR 122a、122b可由犧牲材料形成,諸如非晶矽,其可相對於BOX SiO2層110及氧化物116而被選擇性地蝕刻。虛設BPR 122a、122b可使用化學氣相沈積(CVD)、電漿增強型化學氣相沈積(PECVD)、原子層沈積(ALD)或濺鍍而形成。在沈積之後,虛設BPR 122a、122b可部分地凹入,使得頂部表面124a、124b在低於BOX SiO2層110之頂部的高度處。可使用選擇性蝕刻來蝕刻虛設BPR 122a、122b。在本申請案之內容背景中的選擇性意謂蝕刻製程蝕刻一種材料顯著地快於蝕刻另一材料。在圖3中所繪示之例項中,選擇性蝕刻製程蝕刻虛設BPR 122a、122b之非晶矽顯著地快於蝕刻氧化物116、硬式遮罩114或BOX SiO2層110之經曝露部分。虛設BPR 122之凹入量可取決於實施例而改變,且大於或小於所繪示實施例之凹處126將不背離本文中所揭示之實施例。
圖4為根據本發明之一個實施例的在後續製造階段時圖1之半導體結構100之示意性橫截面側視圖。圖4展示填充有覆蓋虛設BPR 122a、122b之填充物128的凹處126。填充物128可包括與BOX SiO2層110相同或類似的材料,且可將凹處126填充至硬式遮罩114之頂部,使得半導體結構100接著可被平坦化(例如CMP)。在平坦化之後,執行FIN顯露製程以使介電質116、128選擇性地凹入(例如稀釋氫氟酸(DHF)或經緩衝氧化蝕刻(BHF)濕式蝕刻;或可使用SiCoNi/COR乾式蝕刻製程),使得完全曝露奈米薄片堆疊(包含替代性SiGe及Si),同時使虛設BPR 122保持被覆蓋。此後,可選擇性地移除硬式遮罩層114。
圖5A及圖5B為根據本發明之一個實施例的在後續製造階段時圖1之半導體結構100之示意性橫截面側視圖。圖5A展示圖1至圖4中所繪示之位置的橫截面位置,且圖5B展示垂直於圖1至圖4之視圖的第二視角。圖5B中之線A-A展示圖1至圖4、圖5A及圖6至圖13之位置。
圖5A及圖5B展示在運用硬式遮罩134、間隔件132、內部間隔件135及在裝置區136中之S/D磊晶成形來形成虛設閘極130之後的製程階段。可使用習知奈米薄片製造製程來實現閘極、間隔件及內部間隔件成形。在經曝露奈米薄片之間,半導體結構100具有源極/汲極(S/D) 138,該等源極/汲極以磊晶方式形成以將結晶層形成至BOX SiO2層110上及閘極之間。S/D 138之磊晶層可自氣態或液態前驅物生長。磊晶矽可使用氣相磊晶(VPE)、分子束磊晶(MBE)、液相磊晶(LPE)或其他合適製程而生長。磊晶矽、矽鍺及/或碳摻雜矽(Si:C)矽可在沈積期間藉由添加摻雜劑或雜質而摻雜以形成矽化物。取決於電晶體之類型,矽可摻雜有n型摻雜劑(例如磷或砷)或p型摻雜劑(例如硼或鎵)。
形成S/D 138之磊晶層可使用合適生長製程而生長,例如CVD、液相(LP)或減壓化學氣相沈積(RPCVD)、氣相磊晶(VPE)、分子束磊晶(MBE)、液相磊晶(LPE)、金屬有機化學氣相沈積(MOCVD)或其他合適製程。
圖6為根據本發明之一個實施例的圖1之半導體結構100之示意性橫截面側視圖。圖6展示由層間介電質(ILD) 140覆蓋之裝置區136。裝置區136可具有在形成ILD 140之前完成之若干階段。在形成ILD 140之後,進一步執行若干習知製程以製造裝置。舉例而言,閘極切割及單擴散中斷可經圖案化且填充有介電質,CMP製程可用以拋光ILD且移除閘極硬式遮罩134以曝露虛設閘極,且Si薄片之間的虛設閘極130及犧牲SiGe可經蝕刻掉且由高k金屬閘極替代。製造高k閘極介電質及S/D 138之步驟通常可涉及用於諸如退火之步驟的熱處理,且虛設BPR 122a、122b之非晶矽藉由擴散或藉由屈曲而並不抑制退火製程。亦即,不同於金屬BPR,虛設BPR 122a、122b在退火製程期間不具有散佈或擴散之原子。且由於膨脹係數較小且較接近於半導體結構100之其餘部分(及製造有半導體結構100之晶圓),故虛設BPR 122a、122b將不會在製造製程之加熱階段期間向半導體結構100施加應力或使其曲折。
圖7為根據本發明之一個實施例的圖1之半導體結構100之示意性橫截面側視圖。圖7展示接觸件142a、142b,當完成半導體結構100時,經由該等接觸件發送控制信號。接觸件142a、142b包括S/D接觸件142a及通路接觸件至埋入式電源軌(VBPR) 142b。接觸件142a、142b係使用習知微影及蝕刻製程經由ILD 140而形成。在某些實施例中,運用一個遮罩形成用於S/D接觸件142a之開口,接著針對VBPR 142b之開口運用不同遮罩。在其他實施例中,可使用同一遮罩形成用於S/D接觸件142a及VBPR 142b之開口。在S/D接觸件142a、142b經蝕刻通過ILD 140以曝露S/D 138及/或虛設BPR 122a、122b之後,該等開口經金屬化以形成接觸件142a、142b。VBPR 142b在頂部表面144處接觸虛設BPR 122a、122b。
圖8為根據本發明之一個實施例的圖1之半導體結構100之示意性橫截面側視圖。圖8展示添加了中段製程(MOL)及/或後段製程(BEOL)層146及接合至BEOL層146之頂部表面150的載體晶圓148。MOL/BEOL層146包括用於經由接觸件142a、142b控制裝置區136中之電晶體的信號及電源線。MOL/BEOL層146包括用於晶片至封裝連接之接觸件、絕緣層(介電質)、金屬層級及接合位點。雖然所繪示之實施例未按比例繪製,但用於製造MOL/BEOL層146之現代製程可包括多於十個金屬層。載體晶圓148經接合以實現晶圓翻轉及背側處理,包括下文所說明之步驟。在某些實施例中,載體晶圓148可經由介電質-介電質接合或Cu-Cu接合而接合至BEOL層146。
圖9為根據本發明之一個實施例的圖1之半導體結構100之示意性橫截面側視圖。圖9展示經翻轉以完成用於電源遞送之步驟的半導體結構100。載體晶圓148支撐半導體結構100,同時自底部表面152移除基板108,此顯露虛設BPR 122a、122b。接著自與頂部表面150相對之底部表面152選擇性地蝕刻虛設BPR 122a、122b,使BOX SiO2層110及VBPR 142b完好且形成BPR溝槽154。
圖10為根據本發明之一個實施例的圖1之半導體結構100之示意性橫截面側視圖。圖10展示經加寬之BPR溝槽154。BPR溝槽154可使用同向性蝕刻來加寬,該同向性蝕刻可經控制以均一地蝕刻BPR溝槽154內部之表面。蝕刻製程可對BOX SiO2層110具有選擇性,使得VBPR 142b不受影響,且突出至BPR溝槽154中。BPR溝槽154之較長蝕刻曝露VBPR 142b之較多部分,而較短蝕刻將曝露VBPR 142b之較少部分。
圖11為根據本發明之一個實施例的圖1之半導體結構100之示意性橫截面側視圖。圖11展示經填充以形成BPR 158之BPR溝槽154。BPR溝槽154可填充有諸如銅、鈷、鎢及釕之金屬。在金屬填充之前,沈積金屬黏著襯裏166,諸如薄TiN或TaN襯裏。BPR 158填充有一或多種金屬,使得電源可以最少量之電阻流過。BPR 158因此能夠沿著長度(亦即,進入/離開頁面)將電壓供應至數個S/D 138,而不會在功率損耗方面消耗太多。此可轉變為半導體結構100之較冷操作及利用半導體結構100之裝置之較長電池壽命。
為了進一步增大BPR 158之效率,本文中所揭示之實施例具有大於BPR 158上方之S/D 138之間的距離162之臨界尺寸160。臨界尺寸160係由BPR溝槽154之蝕刻量判定。歸因於自底部表面152進行蝕刻,而非嘗試在形成接觸件142a、142b之前蝕刻BPR溝槽154,因此較大臨界尺寸160係可能的。
BPR 158亦在VBPR 142b上方形成環繞式接觸件,其增大了VBPR與BPR之間的接觸面積,此緩解了VBPR 142b底部CD過小而可能在VBPR與BPR之間導致不良接觸的問題。
雖然某些實施例可包括直接接觸VBPR 142b之BPR 158,但所繪示之實施例包括BPR 158與BOX SiO2層110之間的黏著襯裏166。黏著襯裏166可由氮化鈦及氮化鉭形成,或由幫助BPR 158較佳地黏著至BOX SiO2層110而不會劣化、擴散或與半導體結構100之其他組件形成短路的類似材料形成。如所繪示,黏著襯裏166可環繞VBPR 142b,且BPR 158可環繞黏著襯裏166而非直接環繞VBPR 142b。
圖12為根據本發明之一個實施例的圖1之半導體結構100之示意性橫截面側視圖。圖12展示耦接至BPR 158且含有半導體結構100所需之電源遞送組件的背側電源遞送網路(BSPDN) 170。BSPDN 170之目標係以最高效方式將電源及參考電壓提供至裝置區136中之S/D 138及其他裝置。BSPDN 170為與裝置區136之相對側上含有之MOL/BEOL層146分離的互連件網路。傳統上,電源組件及信號組件係經由前側(亦即,在圖12中所繪示之組態中的接觸件142a、142b下方)上之後段製程(BEOL)處理來製造。將BSPDN 170分離至背側(亦即,與前側相對,因此裝置區136在前側與背側之間)使得能夠向裝置區136進行直接電源遞送,此增強了系統效能、增大了晶片面積利用率且降低了MOL/BEOL層146中之複雜度。
由本文中所描述之製程產生的積體電路晶片可由製造者以原始晶圓形式(亦即,作為具有多個未封裝晶片之單一晶圓)、作為裸晶粒或以封裝形式進行分銷。在後一情況下,晶片安裝於單晶片封裝(諸如塑膠載體,具有附連至主機板或其他較高層級載體之引線)中或多晶片封裝(諸如陶瓷載體,其具有表面互連件或埋入式互連件中之任一者或兩者)中。在任何情況下,晶片接著與其他晶片、離散電路元件及/或其他信號處理裝置整合作為以下各者之部分:(a)諸如主機板之中間產品;或(b)最終產品。最終產品可為包括積體電路晶片之任何產品,其範圍為自玩具及其他低端應用至具有顯示器、鍵盤或其他輸入裝置及中央處理器之進階電腦產品。
本文中所使用之術語僅出於描述特定實施例之目的且並不意欲限制本發明。如本文中所使用,除非上下文另有清楚指示,否則單數形式「一(a/an)」及「該」意欲亦包括複數形式。應進一步理解,術語「包含(comprises及/或comprising)」在本說明書中使用時指定所陳述之特徵、整數、步驟、操作、元件及/或組件之存在,但不排除一或多個其他特徵、整數、步驟、操作、元件、組件及/或其群組之存在或添加。
雖然本申請案已關於其較佳實施例而被特定地展示及描述,但熟習此項技術者應理解,可在不脫離本申請案之精神及範疇的情況下進行形式及細節上之前述及其他改變。因此希望本申請案不限於所描述及說明之精確形式及細節,但屬於隨附申請專利範圍之範疇內。
本發明之各種實施例之描述已出於說明之目的而呈現,但並不意欲為詳盡的或限於所揭示之實施例。在不脫離所描述實施例之範疇及精神的情況下,許多修改及變化對一般熟習此項技術者而言將顯而易見。本文中所使用之術語經選擇以最佳地解釋實施例之原理、實際應用或對市場中發現之技術的技術改良,或使其他一般熟習此項技術者能夠理解本文中所揭示之實施例。
100:半導體結構
102:列
104:鰭片
106a:第一NFET區/FET區/第一FET區
106b:第二NFET區/FET區/第二FET區
106c:第一PFET區/FET區/第三FET區
106d:第二PFET區/FET區/第四FET區
108:基板
110:BOX SiO2層/介電層
112:層
114:硬式遮罩
116:介電質/氧化物
118a:埋入式電源軌溝槽/BPR溝槽/第一BPR溝槽
118b:埋入式電源軌溝槽/BPR溝槽/第二BPR溝槽
120:大寬度
122a:虛設埋入式電源軌/虛設BPR
122b:虛設埋入式電源軌/虛設BPR
124a:頂部表面
124B:頂部表面
126:凹處
128:填充物/介電質
130:虛設閘極
132:間隔件
134:硬式遮罩/閘極硬式遮罩
135:內部間隔件
136:裝置區
138:源極/汲極/S/D
142a:接觸件/S/D接觸件
142b:接觸件/通路接觸件至埋入式電源軌/VBPR
144:頂部表面
146:中段製程及/或後段製程層/BEOL層/MOL/BEOL層
148:載體晶圓
150:頂部表面
152:底部表面
154:BPR溝槽
158:BPR
160:臨界尺寸
162:距離
166:金屬黏著襯裏/黏著襯裏
170:背側電源遞送網路/BSPDN
圖1為根據本發明之一個實施例的半導體結構之示意性橫截面側視圖;
圖2為根據本發明之一個實施例的在後續製造階段時圖1之半導體結構之示意性橫截面側視圖;
圖3為根據本發明之一個實施例的在後續製造階段時圖1之半導體結構之示意性橫截面側視圖;
圖4為根據本發明之一個實施例的在後續製造階段時圖1之半導體結構之示意性橫截面側視圖;
圖5A及圖5B為根據本發明之一個實施例的在後續製造階段時圖1之半導體結構之示意性橫截面側視圖;
圖6為根據本發明之一個實施例的在後續製造階段時圖1之半導體結構之示意性橫截面側視圖;
圖7為根據本發明之一個實施例的在後續製造階段時圖1之半導體結構之示意性橫截面側視圖;
圖8為根據本發明之一個實施例的在後續製造階段時圖1之半導體結構之示意性橫截面側視圖;
圖9為根據本發明之一個實施例的在後續製造階段時圖1之半導體結構之示意性橫截面側視圖;
圖10為根據本發明之一個實施例的在後續製造階段時圖1之半導體結構之示意性橫截面側視圖;
圖11為根據本發明之一個實施例的在後續製造階段時圖1之半導體結構之示意性橫截面側視圖;且
圖12為根據本發明之一個實施例的在後續製造階段時圖1之半導體結構之示意性橫截面側視圖。
100:半導體結構
102:列
104:鰭片
106a:第一NFET區/FET區/第一FET區
106b:第二NFET區/FET區/第二FET區
106c:第一PFET區/FET區/第三FET區
106d:第二PFET區/FET區/第四FET區
108:基板
110:BOX SiO2層/介電層
112:層
114:硬式遮罩
116:介電質/氧化物
Claims (20)
- 一種半導體結構,其包含:一裝置區,其包含一第一源極/汲極(S/D)及一第二S/D;一埋入式電源軌(BPR),其在該裝置區下方,其中該BPR之一臨界尺寸大於該第一S/D與該第二S/D之間的一距離;一通路接觸件至埋入式電源軌(VBPR),其在該BPR與該S/D之間。
- 如請求項1之半導體結構,其中該BPR環繞該VBPR。
- 如請求項1之半導體結構,其進一步包含在該BPR與一絕緣體之間的一黏著襯裏。
- 如請求項3之半導體結構,其中該黏著襯裏環繞該VBPR,且該BPR環繞該黏著襯裏。
- 如請求項3之半導體結構,其中(i)該BPR包含自由以下各者組成之群組的一選擇:銅、鈷、鎢及釕;且(ii)該黏著襯裏包含自由以下各者組成之群組的一選擇:氮化鈦及氮化鉭。
- 如請求項1之半導體結構,其進一步包含電耦接至該BPR之一背側電源遞送網路(BSPDN)。
- 如請求項6之半導體結構,其進一步包含電耦接至該VBPR之後段製程(BEOL)層,其中該裝置區在該BSPDN與該等BEOL層之間。
- 一種用於製造半導體結構之方法,其包含:在一第一鰭片場效電晶體(FET)與一第二鰭片FET之間的一絕緣體層中形成一虛設埋入式電源軌(BPR);形成電連接至該第一鰭片FET之一第一源極/汲極(S/D)及電連接至該第二鰭片FET之一第二S/D;形成接觸該虛設BPR及該第一S/D之一頂部表面之一通路接觸件至埋入式電源軌(VBPR);自與該頂部表面相對之一底部表面選擇性地蝕刻該虛設BPR以形成一BPR溝槽;加寬該BPR溝槽;及金屬化該BPR溝槽以形成一BPR。
- 如請求項8之方法,其進一步包含:在形成該虛設BPR之前形成一第一摻雜類型之該第一鰭片場效電晶體(FET);及在形成該虛設BPR之前形成該第一摻雜類型之該第二鰭片FET。
- 如請求項8之方法,其中形成該虛設BPR包含將非晶矽沈積至該第一鰭片FET與該第二鰭片FET之間的一虛設BPR溝槽中。
- 如請求項8之方法,其中加寬該BPR溝槽包含在不蝕刻該VBPR的情況下選擇性地蝕刻該絕緣體層。
- 如請求項8之方法,其中加寬該BPR溝槽包含加寬至大於該第一S/D與該第二S/D之間的一距離之一臨界尺寸。
- 如請求項8之方法,其進一步包含在金屬化該BPR溝槽之前在該BPR溝槽內形成一黏著襯裏。
- 如請求項13之方法,其中該黏著襯裏環繞該VBPR,且該BPR環繞該黏著襯裏。
- 一種半導體結構,其包含:一背側電源遞送網路(BSPDN);一埋入式電源軌(BPR),其耦接至該BSPDN;一通路接觸件至埋入式電源軌(VBPR),其耦接至該BPR,其中該BPR環繞該VBPR之一底部;一第一源極/汲極(S/D),其耦接至該VBPR之一中部;及一後段製程層,其耦接至該VBPR之一頂部。
- 如請求項15之半導體結構,其進一步包含一第二S/D,其中該BPR之一臨界尺寸大於該第一S/D與該第二S/D之間的一距離。
- 如請求項16之半導體結構,其中該VBPR在該第一S/D與該第二S/D之間通過以連接至該BPR。
- 如請求項15之半導體結構,其進一步包含在該BPR與一絕緣體之間的一黏著襯裏。
- 如請求項18之半導體結構,其中該黏著襯裏環繞該VBPR,且該BPR環繞該黏著襯裏。
- 如請求項18之半導體結構,其中(i)該BPR包含自由以下各者組成之群組的一選擇:銅、鈷、鎢及釕;且(ii)該黏著襯裏包含自由以下各者組成之群組的一選擇:氮化鈦及氮化鉭。
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US20210202385A1 (en) * | 2019-12-29 | 2021-07-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and Method for Transistors Having Backside Power Rails |
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US20210202385A1 (en) * | 2019-12-29 | 2021-07-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and Method for Transistors Having Backside Power Rails |
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