TWI721041B - Drive circuit, display device and electronic device - Google Patents

Abstract

One of the objectives of an embodiment of the present invention is to provide a novel circuit, a circuit with low power consumption, a circuit with a reduced area, or a circuit with high versatility. The driving circuit has a function of supplying image signals to a plurality of pixel groups and is shared by the plurality of pixel groups. In addition, power is supplied to the line that generates the image signal, and the power supply to the line that does not generate the image signal is stopped. Therefore, even when the drive circuit is shared by a plurality of pixel groups, it is possible to stop supplying power to circuits that are not used when generating the image signal, and thereby it is possible to achieve both reduction in the area of the drive circuit and reduction in power consumption.

Description

Drive circuit, display device and electronic device

One embodiment of the present invention relates to a driving circuit, a display device, and an electronic device.

Note that one embodiment of the present invention is not limited to the above-mentioned technical field. As an example of the technical field of an embodiment of the present invention disclosed in this specification and the like, there are drive circuits, semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, display systems, electronic devices, and lighting equipment. , Input device, input/output device, its driving method or its manufacturing method.

Note that in this specification and the like, semiconductor devices refer to all devices that can operate by utilizing semiconductor characteristics. Transistors, semiconductor circuits, arithmetic devices, drive circuits, memory devices, etc. are all embodiments of semiconductor devices. In addition, imaging devices, electro-optical devices, power generating devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices sometimes include semiconductor devices.

Flat panel displays represented by liquid crystal display devices and light-emitting display devices are widely used for image display. Silicon semiconductors are mainly used as transistors used in these display devices. However, in recent years, the technology of using metal oxides exhibiting semiconductor characteristics for transistors instead of silicon semiconductors has attracted attention. For example, Patent Documents 1 and 2 have disclosed a technique of using a transistor using zinc oxide or In-Ga-Zn oxide as a semiconductor layer for a pixel of a display device.

[Patent Document 1] Japanese Patent Application Publication No. 2007-96055

[Patent Document 2] Japanese Patent Application Publication No. 2007-123861

One of the objectives of one embodiment of the present invention is to provide a novel circuit or display device. In addition, one of the objectives of an embodiment of the present invention is to provide a circuit or display device with low power consumption. In addition, one of the objectives of an embodiment of the present invention is to provide a circuit or display device with a small area. In addition, one of the objectives of one embodiment of the present invention is to provide a circuit or display device with high versatility.

Note that an embodiment of the present invention does not need to achieve all the above-mentioned objects, as long as it can achieve at least one object. In addition, the description of the above purpose does not prevent the existence of other purposes. It can be clearly seen from the description, the scope of patent application, drawings, etc., that the purpose other than the above is derived.

One embodiment of the present invention is a driving circuit including: a shift register; a decoding circuit; a level shifter circuit; a DA conversion circuit; and an amplifier circuit, wherein the shift register includes a first circuit and a second circuit. The decoding circuit includes a third circuit and a fourth circuit, the level shifter circuit includes a fifth circuit and a sixth circuit, the DA conversion circuit includes a seventh circuit and an eighth circuit, and the amplifying circuit includes a ninth circuit and a tenth circuit, The ninth circuit is electrically connected to the first wiring, and the tenth circuit is electrically connected to the second wiring. The first circuit, the third circuit, the fifth circuit, the seventh circuit, and the ninth circuit constitute the first line. The circuit, the sixth circuit, the eighth circuit, and the tenth circuit constitute a second line. The first line has a function of generating a first image signal supplied to the first wiring, and the second line has a function of generating a second image supplied to the second wiring. The function of the signal is to stop the supply of power to the circuits constituting the first line during the period when the first video signal is not generated, and to stop the supply of power to the circuits constituting the second line during the period when the second video signal is not generated.

In addition, in the driving circuit of one embodiment of the present invention, the first circuit and the second circuit may also include a flip-flop, the third circuit and the fourth circuit may also include a decoder, and the fifth circuit and the sixth circuit may also Including the level shifter, the seventh circuit and the eighth circuit may also include a selection circuit, and the ninth circuit and the tenth circuit may also include an amplifier.

In addition, in the drive circuit of one embodiment of the present invention, the first circuit and the second circuit may include a first switch and a second switch, and the first terminal of the first switch may be electrically connected to the flip-flop, and the first The second terminal of the switch can also be electrically connected to the wiring that is supplied with the power supply potential, the first terminal of the second switch can also be electrically connected to the input terminal of the flip-flop, and the second terminal of the second switch can also be connected to the flip-flop The output terminal is electrically connected, and the second switch may also have a function of becoming an on state while the first switch is in the off state.

In addition, in the drive circuit of one embodiment of the present invention, the DA conversion circuit may include a first potential generation circuit and a second potential generation circuit, and the first potential generation circuit may have a device for supplying the first reference potential to the seventh circuit. Function, the second potential generation circuit may also have the function of supplying the second reference potential to the eighth circuit. During the period when the first image signal is not being generated, the supply of the first reference potential may also be stopped, and during the period when the second image signal is not being generated , You can also stop the supply of the second reference potential.

In addition, one embodiment of the present invention is a display device including: the above-mentioned driving circuit; and a pixel portion, wherein the pixel portion includes a first pixel and a second pixel, the first pixel includes a reflective liquid crystal element, and the second pixel includes a light emitting In addition, the driving circuit has a function of supplying a first image signal to the first pixel and a function of supplying a second image signal to the second pixel.

In addition, one embodiment of the present invention is an electronic device including a display system, the display system including: a control unit including the above-mentioned driving circuit; a display unit; and a processor, wherein the display unit includes a first display unit, a second display Unit and touch sensor unit, the first display unit includes a first pixel with a reflective liquid crystal element, the second display unit includes a second pixel with a light-emitting element, the processor has the function of sending image data to the control unit, and controls The part has a function of generating a first image signal and a second image signal according to the image data, and the driving circuit supplies the first image signal to the first display unit and supplies the second image signal to the second display unit.

According to an embodiment of the present invention, a novel circuit or display device can be provided. In addition, according to an embodiment of the present invention, a circuit or display device with low power consumption can be provided. In addition, according to an embodiment of the present invention, a circuit or display device with a small area can be provided. In addition, according to an embodiment of the present invention, a circuit or display device with high versatility can be provided.

Note that the description of the above effects does not prevent the existence of other effects. In addition, an embodiment of the present invention does not need to have all the above-mentioned effects. Effects other than the above can be clearly seen and derived from the description of the specification, the scope of patent application, and the drawings.

10‧‧‧Display device

20‧‧‧Pixel

21‧‧‧Pixel unit

30‧‧‧Pixel Group

31‧‧‧ pixels

40‧‧‧Drive circuit

50‧‧‧Drive circuit

51‧‧‧Shift register

52‧‧‧Decoding circuit

53‧‧‧Level shifter circuit

54‧‧‧DA conversion circuit

55‧‧‧Amplifying circuit

56‧‧‧Holding circuit

60‧‧‧Liquid crystal element

61‧‧‧Reflective electrode

62‧‧‧Liquid crystal layer

63‧‧‧Transparent electrode

64‧‧‧Light

65‧‧‧Open

70‧‧‧Light-emitting element

71‧‧‧Light

110‧‧‧register

120‧‧‧Latch circuit

130‧‧‧Decoder

131‧‧‧Conversion circuit

140‧‧‧Latch circuit

150‧‧‧Level shifter

151‧‧‧Conversion circuit

160‧‧‧Selection circuit

161N‧‧‧Circuit

161P‧‧‧Circuit

170‧‧‧Potential generating circuit

170a‧‧‧Potential generating circuit

170b‧‧‧Potential generating circuit

180‧‧‧Amplifier

190‧‧‧Sample and Hold Circuit

412‧‧‧Liquid crystal layer

413‧‧‧electrode

417‧‧‧Insulation layer

421‧‧‧Insulation layer

431‧‧‧Color layer

432‧‧‧Shading layer

433‧‧‧Orientation film

434‧‧‧Color layer

435‧‧‧Polarizer

441‧‧‧Adhesive layer

442‧‧‧Adhesive layer

451‧‧‧Open

470‧‧‧Light-emitting element

480‧‧‧Liquid crystal element

491‧‧‧electrode

492‧‧‧EL floor

493‧‧‧electrode

494‧‧‧Insulation layer

501‧‧‧Transistor

503‧‧‧Transistor

504‧‧‧Connecting part

505‧‧‧Transistor

506‧‧‧Transistor

507‧‧‧Connecting part

511‧‧‧Insulation layer

512‧‧‧Insulation layer

513‧‧‧Insulation layer

514‧‧‧Insulation layer

516‧‧‧Insulation layer

517‧‧‧Insulation layer

518‧‧‧Insulation layer

520‧‧‧Insulation layer

521‧‧‧Conductive layer

522‧‧‧Conductive layer

523‧‧‧Conductive layer

531‧‧‧Semiconductor layer

540‧‧‧Transistor

542‧‧‧Connecting layer

543‧‧‧Connector

552‧‧‧Connecting part

561‧‧‧Semiconductor layer

563‧‧‧Conductive layer

580‧‧‧Transistor

581‧‧‧Transistor

584‧‧‧Transistor

585‧‧‧Transistor

586‧‧‧Transistor

600‧‧‧Display device

600A‧‧‧Display device

600B‧‧‧Display device

601‧‧‧Display device

611‧‧‧electrode

640‧‧‧Liquid crystal element

651‧‧‧Substrate

660‧‧‧Light-emitting element

661‧‧‧Substrate

662‧‧‧Display

664‧‧‧Circuit

665‧‧‧Wiring

672‧‧‧FPC

673‧‧‧IC

690‧‧‧pixel unit

691‧‧‧ pixels

801‧‧‧Transistor

811‧‧‧Insulation layer

812‧‧‧Insulation layer

813‧‧‧Insulation layer

814‧‧‧Insulation layer

815‧‧‧Insulation layer

816‧‧‧Insulation layer

817‧‧‧Insulation layer

818‧‧‧Insulation layer

819‧‧‧Insulation layer

820‧‧‧Insulation layer

821‧‧‧Metal Oxide Film

822‧‧‧Metal Oxide Film

823‧‧‧Metal Oxide Film

824‧‧‧Metal Oxide Film

830‧‧‧Oxide layer

850‧‧‧Conductive layer

851‧‧‧Conductive layer

852‧‧‧Conductive layer

853‧‧‧Conductive layer

900‧‧‧Display System

910‧‧‧Display

911‧‧‧Display unit

912‧‧‧Touch Sensor Unit

920‧‧‧Control Department

921‧‧‧Interface

922‧‧‧Frame memory

923‧‧‧Decoder

924‧‧‧Sensing Controller

925‧‧‧controller

926‧‧‧Clock generation circuit

930‧‧‧Image Processing Department

931‧‧‧Gamma correction circuit

932‧‧‧Dimming circuit

933‧‧‧Toning circuit

934‧‧‧EL correction circuit

941‧‧‧Memory Device

942‧‧‧Timing Controller

943‧‧‧register

950‧‧‧Drive circuit

961‧‧‧Touch Sensor Controller

970‧‧‧Host

980‧‧‧Light Sensor

981‧‧‧External Light

1000‧‧‧Display Module

1001‧‧‧Top cover

1002‧‧‧Lower cover

1003‧‧‧FPC

1004: Touch panel

1005: FPC

1006: display device

1009: frame

1010: printed circuit board

1011: battery

2000: Portable Information Terminal

2001: Shell

2002: Shell

2003: Display

2004: Display Department

2005: Hinge

2010: Portable Information Terminal

2011: shell

2012: Display

2013: Operation buttons

2014: External port

2015: speakers

2016: microphone

2017: camera

2020: camera

2021: shell

2022: Display

2023: Operation button

2024: Shutter button

2026: lens

In the drawings: FIGS. 1A and 1B are diagrams showing a structural example of a display device; FIG. 2 is a diagram showing a structural example of a display device; FIG. 3 is a diagram showing a structural example of a driving circuit; FIG. 4 is Figs. 5A and 5B are diagrams showing structural examples of the register; Figs. 6A to 6C are diagrams showing structural examples of the register; Fig. 7 is Fig. 8 is a diagram showing a structure example of a level shifter circuit; Fig. 9 is a diagram showing a structure example of a latch circuit and a level shifter; Fig. 10 is a diagram showing Fig. 11 is a diagram showing a configuration example of a potential generation circuit; Fig. 12 is a diagram showing a configuration example of an amplifier circuit; Fig. 13 is a diagram showing a configuration example of an amplifier; Fig. 14 is a diagram showing a configuration example of an amplifier 15A and 15B are diagrams showing a structure example of a switch; FIG. 16 is a diagram showing a structure example of a driving circuit; FIG. 17 is a diagram showing a structure example of a holding circuit; 18 is a diagram showing a structural example of a display device; FIG. 19 is a diagram showing a structural example of a display device; FIG. 20 is a diagram showing a structural example of a display device; FIG. 21 is a diagram showing a structural example of a display device 22A, 22B1, 22B2, 22B3, and 22B4 are diagrams showing structural examples of display devices; FIG. 23 is a diagram showing a structural example of a pixel; FIGS. 24A and 24B are diagrams showing a structure of a pixel Fig. 25 is a diagram showing a structural example of a display module; Figs. 26A to 26C are diagrams showing a structural example of a transistor; Fig. 27 is a diagram showing an energy band structure; Fig. 28 is a diagram showing A diagram showing a structural example of the system; FIGS. 29A to 29D are diagrams showing a structural example of an electronic device.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the description in the following embodiments, but a person skilled in the art can easily understand the fact that its mode and details can be modified without departing from the spirit and scope of the present invention. Transform into various forms. Therefore, the present invention should not be interpreted as being limited to the content described in the embodiments shown below.

In addition, one embodiment of the present invention includes all devices, such as semiconductor devices, memory devices, display devices, imaging devices, and RF (Radio Frequency) tags, within its category. In addition, display devices include liquid crystal display devices, light-emitting devices each pixel having light-emitting elements represented by organic light-emitting elements, electronic paper, DMD (Digital Micromirror Device: Digital Micromirror Device), and PDR (Plasma Display). Panel; Plasma display panel), FED (Field Emission Display; Field Emission Display), etc.

In this specification and the like, metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (Oxide Semiconductor, also abbreviated as OS), and the like. For example, when a metal oxide is used for the channel formation region of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, in the case where the metal oxide has at least one of an amplification function, a rectification function, and a switching function, the metal oxide may be referred to as a metal oxide semiconductor, or it may be abbreviated as an OS. Hereinafter, a transistor containing a metal oxide in the channel formation region is also referred to as an OS transistor.

In addition, in this specification and the like, a metal oxide containing nitrogen may also be referred to as a metal oxide. In addition, a metal oxide containing nitrogen may also be referred to as a metal oxynitride (metal oxynitride). The details of the metal oxide will be described later.

In this specification and the like, when it is clearly stated as "X and Y are connected", it means that the following cases are disclosed in this specification and the like: the case where X is electrically connected to Y; the case where X and Y are functionally connected; and X When directly connected to Y. Therefore, it is not limited to the connection relationship shown in the drawings or the text. For example, other connection relationships are also included in the scope of the drawings or the text. Here, both X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

As an example of a case where X and Y are directly connected, there is no element (such as switches, transistors, capacitors, inductors, resistors, diodes, Display elements, light-emitting elements, loads, etc.), and X and Y do not have components that can electrically connect X and Y (such as switches, transistors, capacitors, inductors, resistors, diodes, display elements, light-emitting elements, and Load, etc.) Connection status.

As an example of the case where X and Y are electrically connected, one or more elements (such as switches, transistors, capacitors, inductors, resistors, diodes, Display elements, light-emitting elements, loads, etc.). In addition, the switch has the function of controlling opening and closing. In other words, the switch has a function of controlling whether or not to allow current to flow when it becomes a conductive state (on state) or a non-conductive state (off state). Alternatively, the switch has the function of selecting and switching the current path. In addition, the case where X and Y are electrically connected includes the case where X and Y are directly connected.

As an example of the case where X and Y are functionally connected, more than one circuit capable of functionally connecting X and Y (for example, logic circuit (inverter, NAND circuit, NOR circuit) can be connected between X and Y. Etc.), signal conversion circuit (DA conversion circuit, AD conversion circuit, γ (gamma) correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), change signal potential level Level converter circuits, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase signal amplitude or current, etc., operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.) Etc.), signal generating circuit, memory circuit, control circuit, etc.). Note that, for example, even if there are other circuits between X and Y, when the signal output from X is transmitted to Y, it can be said that X and Y are functionally connected. In addition, the case where X and Y are functionally connected includes the case where X and Y are directly connected and the case where X and Y are electrically connected.

In addition, when it is clearly stated that "X and Y are electrically connected", the following is disclosed in this specification and the like: the case where X and Y are electrically connected (in other words, X and Y are connected with other elements or other circuits in between. The case of Y); the case where X and Y are functionally connected (in other words, the case where X and Y are functionally connected with other circuits in between); and the case where X and Y are directly connected (in other words, the case where there is no middle (When connecting X and Y with other components or other circuits). In other words, when it is explicitly described as "electrically connected", the same content as when it is explicitly described as "connected" is disclosed in this specification and the like.

In addition, even if it is shown that independent components are electrically connected to each other in the drawings, there are cases where one component has the functions of multiple components. For example, when a part of the wiring is used as an electrode, one conductive film has the functions of two components of the wiring and the electrode. Therefore, the category of "electrical connection" in this specification also includes the case where a single conductive film has the function of a plurality of components.

Embodiment 1

In this embodiment, a display device according to an embodiment of the present invention will be described.

<Example of the structure of the display device>

FIG. 1A shows an example of the structure of the display device 10. The display device 10 includes a pixel unit 20, a plurality of driving circuits 40, and a driving circuit 50. In addition, the pixel unit 20 includes a plurality of pixel groups 30. Hereinafter, although the structure of the display device 10 including two pixel groups 30 (30a, 30b) and two drive circuits 40 (40a, 40b) is described as an example, the number of pixel groups 30 and drive circuits 40 may also be 3 or more. .

The pixel unit 20 has a function of displaying images. The pixel group 30a is composed of a plurality of pixels 31a, and the pixel group 30b is composed of a plurality of pixels 31b. The pixels 31a and 31b both include display elements, and both have the function of displaying locked gray scales. The types or characteristics of the display elements included in the pixel 31a and the display elements included in the pixel 31b may be the same or different. In addition, the circuit structure of the pixel 31a and the pixel 31b may be the same or different. Since the plurality of pixels 31a or the plurality of pixels 31b display the locked gray scale, the pixel section 20 displays the locked image.

As an example of a display element, a liquid crystal element, a light emitting element, etc. can be mentioned. As the liquid crystal element, a transmissive liquid crystal element, a reflective liquid crystal element, a semi-transmissive liquid crystal element, etc. can be used. In addition, as display elements, shutter-type MEMS (Micro Electro Mechanical Systems: Micro Electro Mechanical Systems) elements, optical interference-type MEMS elements, applied microcapsule method, electrophoresis method, electrowetting method, electronic powder fluid (Japanese The registered trademark) method and other display components.

In addition, as light-emitting elements, for example, OLED (Organic Light Emitting Diode)-LED (Light Emitting Diode), QLED (Quantum-dot Light Emitting Diode: Quantum Dot Light Emitting Diode), semiconductor laser, etc. self-luminous性light-emitting elements.

When displaying an image, both the pixel group 30a and the pixel group 30b may be used, or only one of them may be used. In the case of using both, the pixel group 30a and the pixel group 30b can display one image or different images respectively.

When only one of the pixel group 30a and the pixel group 30b is used to display an image, the pixel group 30 for displaying the image can be automatically or manually switched. Here, by disposing different display elements in the pixel 31a and the pixel 31b, the characteristics or quality of the image displayed by the pixel group 30a can be different from the image displayed by the pixel group 30b. In this case, the pixel group 30 to be displayed can be selected according to the surrounding environment, display content, and the like. Hereinafter, as an example, a structure in which a reflective liquid crystal element is provided in the pixel 31a and a light-emitting element is provided in the pixel 31b will be described.

FIG. 1B is a schematic diagram illustrating the structure of the pixel portion 20 that performs display using the reflective liquid crystal element 60 and the light-emitting element 70. The liquid crystal element 60 includes a reflective electrode 61, a liquid crystal layer 62, and a transparent electrode 63.

By controlling the transmittance of the liquid crystal layer 62 to the light 64 reflected by the reflective electrode 61 according to the alignment of the liquid crystal, the gray scale of the liquid crystal element 60 is controlled. The light 64 reflected by the reflective electrode 61 passes through the liquid crystal layer 62 and the transparent electrode 63 and is emitted to the outside. In addition, the reflective electrode 61 has an opening 65, and the light-emitting element 70 is provided at a position overlapping the opening 65. By controlling the current flowing through the light-emitting element 70, the intensity of the light 71 emitted by the light-emitting element 70 is controlled, thereby controlling the gray scale of the light-emitting element 70. The light 71 emitted by the light emitting element 70 passes through the opening 65, the liquid crystal layer 62, and the transparent electrode 63 to be emitted to the outside. The direction in which the light 64 and the light 71 are emitted is the display surface of the display device 10.

By adopting the above structure, the reflective liquid crystal element 60 and the light emitting element 70 can be used to display an image in the pixel portion 20. In this case, for example, in an environment with strong external light such as outdoors on a sunny day and a day, only a reflective liquid crystal element is used for display without causing the light-emitting element to emit light, thereby reducing power consumption. On the other hand, in an environment with weak external light such as night or dark places, the light-emitting element is made to emit light for display, thereby making it possible to display a highly visible image.

In addition, when a reflective liquid crystal element is used to display an image, the color tone can be corrected by using the light emitted by the light-emitting element. For example, in the case of displaying an image in a red environment at dusk, when only a reflective liquid crystal element is used for display, the B (blue) component may be insufficient. At this time, the color tone can be corrected by causing the light-emitting element to emit light.

In addition, because the reflective liquid crystal element does not require a light source other than external light during display, it can display images with low power consumption. On the other hand, since the operating speed of the light emitting element is faster than that of the liquid crystal element, the display can be switched at high speed. In addition, for example, it is possible to display a static image or text as a background in a reflective liquid crystal element and display a moving image or the like in a light-emitting element. Therefore, the reduction of power consumption and the display of high-quality images can be achieved at the same time. The above-mentioned structure is suitable for the case where the display device is used for teaching materials such as textbooks or notebooks.

Furthermore, when a reflective liquid crystal element is used to display an image, the frequency of image rewriting can be reduced, and the operation of the driving circuit 40a and part of the operation of the driving circuit 50 can be stopped during the period when the image is not being rewritten. Therefore, power consumption can be further reduced.

Note that in FIG. 1B, although a case where a reflective liquid crystal element is provided in the pixel 31a and a light-emitting element is provided in the pixel 31b is described as an example, there are no particular restrictions on the display elements provided in the pixels 31a and 31b, and You can choose freely. For example, a transmissive liquid crystal element may be provided in one of the pixels 31a and 31b, and a reflective liquid crystal element may be provided in the other of the pixels 31a and 31b. In this case, the pixels 31a and 31b can be used to realize a semi-transmissive liquid crystal element. In addition, different types of light-emitting elements may be provided in the pixels 31a and 31b, respectively.

In addition, the display device 10 may have a structure capable of switching between the first task for displaying using both the pixel group 30a and the pixel group 30b and the second task for displaying using one of them according to the resolution of the displayed image. For example, the first job can be used when displaying high-precision images or photos, and the second job can be used when displaying background or text. Thus, the resolution can be changed according to the displayed image, and a display device with high versatility can be realized.

The driving circuit 40 has a function of supplying a signal for selecting the pixel 31 (hereinafter, also referred to as a selection signal) to the pixel group 30. Specifically, the driving circuit 40a has a function of supplying a selection signal to the wiring GLa connected to the pixel 31a, and the wiring GLa has a function of transmitting the selection signal output from the driving circuit 40a. The driving circuit 40b has a function of supplying a selection signal to the wiring GLb connected to the pixel 31b, and the wiring GLb has a function of transmitting the selection signal output from the driving circuit 40b.

The driving circuit 50 has a function of generating a signal for displaying an image (hereinafter also referred to as an image signal) and supplying it to the pixel groups 30a and 30b. Specifically, the driving circuit 50 has a function of supplying an image signal to the wiring SLa connected to the pixel 31a and a function of supplying an image signal to the wiring SLb connected to the pixel 31b. The image signal supplied to the wiring SLa, SLb is written to the pixels 31a, 31b selected by the drive circuits 40a, 40b.

In one embodiment of the present invention, the drive circuit 50 has a function of supplying image signals to both the pixel groups 30a and 30b, and is shared by the pixel groups 30a and 30b. Therefore, it is not necessary to provide the driving circuit 50 in the pixel groups 30a and 30b, respectively, and the area of the display device 10 can be reduced.

Next, a more specific configuration example of the display device 10 will be described. FIG. 2 shows a configuration example of the pixel section 20 and the driving circuit 50.

The pixel portion 20 includes m columns and n rows (m and n are integers of 2 or more) of pixels 31a and 31b. The pixel 31a in the i-th column and j-th row (i is an integer from 1 to m, and j is an integer from 1 to n) is connected to the wiring SLa[i] and the wiring GLa[j], and the i-th column is the jth row The pixel 31b of φ is connected to the wiring SLb[i] and the wiring GLb[j]. The wirings GLa[1] to [n] are connected to the drive circuit 40a, and the wirings GLb[1] to [m] are connected to the drive circuit 40b. The wiring SLa[1] to [m] and the wiring SLb[1] to [m] are connected to the drive circuit 50. Here, the pixels 31 a and the pixels 31 b are alternately arranged in the row direction (the up and down direction on the paper), and the pixels 31 a and the pixels 31 b constitute the pixel unit 21. In this way, the pixels 31 a and the pixels 31 b may be mixed in the same area of the pixel portion 20.

Here, it is preferable to use OS transistors as the pixels 31a and 31b. Compared with semiconductors such as silicon, metal oxides have a large energy gap and low minority carrier density, so the off-state current of OS transistors is extremely small. Therefore, when OS transistors are used for the pixels 31a and 31b, compared to the case of using a transistor having silicon in the channel formation region (hereinafter, also referred to as Si transistor), the pixels 31a, 31b In 31b, the video signal can be maintained for a long period of time. Therefore, the frequency of writing video signals to the pixels 31a and 31b can be greatly reduced, thereby reducing power consumption. For example, the writing frequency of the image signal can be more than once a day and less than 0.1 times per second, preferably more than once an hour and less than once per second, more preferably more than once every 30 seconds and low Once in 1 second. In addition, the detailed structure of the pixel 31 using the OS transistor will be described in the third embodiment.

In addition, the drive circuit 50 has a function of generating image signals to be supplied to both the wiring SLa and SLb. Therefore, it is possible to avoid the extension of the wiring SLa and SLb and the complication of the layout that may occur when the drive circuits that generate the image signals supplied to the wiring SLa and SLb are installed in different areas, thereby preventing the interference of the image signals. .

The driving circuit 50 includes a shift register 51, a decoding circuit 52, a level shifter circuit 53, a digital-to-analog (DA) conversion circuit 54, and an amplifier circuit 55.

The shift register 51 has a function of generating sampling pulses using the start pulse SP, the clock signal CLK, and the reset signal RST. The sampling pulse generated by the shift register 51 is output to the decoding circuit 52. In addition, the high power supply potential VDD and the low power supply potential VSS are supplied to the shift register 51.

The decoding circuit 52 has a function of decoding a signal SD that is a video signal input from the outside. Specifically, it has a function of generating a control signal for controlling the operation of the DA conversion circuit 54 based on the signal SD. The signal decoded by the decoding circuit 52 is output to the level shifter circuit 53. In addition, the high power supply potential VDD and the low power supply potential VSS are supplied to the decoding circuit 52.

The level shifter circuit 53 has a function of converting the level of the signal input from the decoding circuit 52. Specifically, the level shifter circuit 53 has a function of converting the potential input from the decoding circuit 52 into a potential for controlling the operation of the DA conversion circuit 54. When a negative potential is used for the operation of the DA conversion circuit 54, the negative potential is generated by the level shifter circuit 53. In addition, the high power supply potentials VDDH, VDD (VDDH>VDD) and the low power supply potential VSS are supplied to the level shifter circuit 53. The high power supply potential VDDH is used when converting the input potential to a higher potential.

The DA conversion circuit 54 has a function of generating an analog signal corresponding to the signal SD. Specifically, it has a function of converting the signal SD, which is a digital signal, into a potential of an analog value. The signal SD decoded by the decoding circuit 52 and converted by the level shifter circuit 53 is used for the operation of the DA conversion circuit 54. In addition, a plurality of reference potentials VR are supplied to the DA conversion circuit 54.

The amplifier circuit 55 has a function of amplifying the potential generated by the DA conversion circuit 54 and outputting it to the wiring SLa and SLb. The potential supplied from the amplifier circuit 55 to the wiring SLa, SLb corresponds to the image signal supplied to the pixels 31a, 31b. In addition, the high power supply potential VDDH and the low power supply potential VSS are supplied to the amplifier circuit 55.

The driving circuit 50 has a function of supplying image signals to both the wiring SLa and SLb, and is shared by the pixels 31a and 31b. Therefore, when supplying an image signal to at least one of the pixel 31a and the pixel 31b, the drive circuit 50 needs to be operated. Here, when the driving circuit 50 is operated as a whole even when the image signal is supplied to only one of the pixels 31a and 31b, the power of the circuits that are not actually used when generating the image signal is also consumed. The power consumption of the driving circuit 50 is increased.

Here, in one embodiment of the present invention, it is possible to selectively supply electric power to a circuit actually used when generating a video signal among the circuits included in the drive circuit 50. Therefore, even when the drive circuit 50 is shared by the pixels 31a and 31b, it is possible to stop supplying power to circuits that are not used when generating the video signal, thereby reducing the power consumption of the drive circuit 50. Next, a specific configuration example of the driving circuit 50 will be described.

<Example of the structure of the drive circuit>

FIG. 3 shows an example of the structure of the driving circuit 50. The shift register 51 includes a plurality of registers 110. The decoding circuit 52 includes a plurality of latch circuits 120 and a plurality of decoders 130. The level shifter circuit 53 includes a plurality of latch circuits 140 and a plurality of level shifters 150. The DA conversion circuit 54 includes a plurality of selection circuits 160 and potential generation circuits 170a and 170b. The amplifier circuit 55 includes a plurality of amplifiers 180. Note that the drive circuit 50 is a semiconductor device.

The numbers of the register 110, the latch circuit 120, the decoder 130, the latch circuit 140, the level shifter 150, the selection circuit 160, and the amplifier 180 are the same as those of the wiring SL, respectively. Hereinafter, a circuit group that generates an image signal to be supplied to one wiring SL is referred to as a line L. That is, the same number of lines L as the wiring SL are provided in the driving circuit 50. The line L is composed of a register 110, a latch circuit 120, a decoder 130, a latch circuit 140, a level shifter 150, a selection circuit 160, and an amplifier 180.

The line La shown in FIG. 3 is connected to the wiring SLa, and the line Lb is connected to the wiring SLb. The line connected to the wiring SLa[i] is represented as La[i], and the line connected to the wiring SLb[i] is represented as Lb[i].

Here, the signal SELa is supplied to the line La, and the signal SELb is supplied to the line Lb. The signals SELa and SELb are selection signals for selecting a line for generating a video signal. Specifically, when a video signal is generated in the line La, a signal SELa showing the selected state is supplied to the line La, and when a video signal is generated in the line Lb, a signal SELb showing the selected state is supplied to the line Lb. In addition, the signal SELa is supplied to the potential generating circuit 170a, and the signal SELb is supplied to the potential generating circuit 170b.

When an image is displayed using the pixel group 30a shown in FIGS. 1A and 1B, the line La is selected and the image signal is supplied to the wiring SLa. On the other hand, the line Lb becomes a non-selected state, and the line Lb does not generate a video signal. At this time, the power supply to the circuits belonging to the line Lb is stopped. Similarly, when an image is displayed using the pixel group 30b shown in FIGS. 1A and 1B, the line Lb is selected and the power supply to the circuits belonging to the line La is stopped. In this way, by selectively supplying power to the line L that generates the image signal, the power consumption of the driving circuit 50 can be reduced. In addition, in the case of displaying an image using both the pixel groups 30a and 30b, both of the lines La and Lb are selected.

In addition, in the line L in the non-selected state, a circuit for stopping the power supply can be freely selected. In other words, the circuit for stopping the power supply may be all the circuits included in the line L in the non-selected state, or may be a part of the circuit.

The following describes the specifics of the register 110, the latch circuit 120, the decoder 130, the latch circuit 140, the level shifter 150, the selection circuit 160, the potential generation circuit 170, and the amplifier 180 that can control the supply of electric power. Structural examples.

[Structure example of scratchpad]

FIG. 4 shows an example of the structure of the shift register 51 including a plurality of registers 110. The register 110 is a circuit having a function of generating sampling pulses and outputting them to the latch circuit 120. Note that although the registers 110 belonging to the lines La[1], Lb[1], La[2], and Lb[2] are shown here, other registers 110 may also have the same structure.

The register 110 includes a switch SW1, a switch SW2, and a flip-flop FF1. The first terminal of the switch SW1 is connected to the flip-flop FF1, and the second terminal is connected to the wiring supplied with the high power supply potential VDD. The first terminal of the switch SW2 is connected to the input terminal of the flip-flop FF1, and the second terminal is connected to the output terminal of the flip-flop FF1. The input terminal of the flip-flop FF1 is connected to the output terminal of the upstream flip-flop FF1, and the output terminal is connected to the latch circuit 120 belonging to the same line L. In addition, the clock signal CLK and the reset signal RST are supplied to the flip-flop FF1. In addition, the start pulse SP is supplied to the input terminal of the flip-flop FF1 on the line La[1].

The conduction state of the switches SW1 and SW2 included in the line La is controlled by the signal SELa, and the conduction state of the switches SW1 and SW2 included in the line Lb is controlled by the signal SELb. 5A and 5B show working examples in which the conduction states of the switches SW1 and SW2 are controlled by the signals SELa and SELb.

FIG. 5A is an example of the structure of the register 110 when the line La is in the selected state and the line Lb is in the non-selected state. At this time, the signal SELa (here, a low level) of the selection line La is supplied to the line La, and the signal SELa is supplied to the switch SW1 and the switch SW2 included in the line La.

Here, the switch SW1 is turned on when the signal SEL is a signal indicating a selected state, and is turned off when the signal SEL is a signal indicating a non-selected state. In addition, the switch SW2 is turned on when the signal SEL is a signal indicating a non-selected state, and is turned off when the signal SEL is a signal indicating a selected state. That is, the conduction states of the switch SW1 and the switch SW2 are opposite to each other.

When the low level signal SELa is supplied to the switch SW1 of the line La, the switch SW1 is turned on, and the power supply potential is supplied to the flip-flop FF1. As a result, the flip-flop FF1 is in an operating state. In addition, when the low level signal SELa is supplied to the switch SW2 of the line La, the switch SW2 is turned off, and the input terminal and the output terminal of the flip-flop FF1 are turned into a non-conducting state. Therefore, the register 110 can output sampling pulses.

On the other hand, the line Lb in the non-selected state is supplied with a signal SELb (here, a high level) for turning the line Lb into the non-selected state, and the signal SELb is supplied to the switches SW1 and SW2 included in the line Lb.

When the high level signal SELb is supplied to the switch SW1 of the line Lb, the switch SW1 is turned off, and the power supply potential to the flip-flop FF1 is stopped. As a result, the flip-flop FF1 is in a stopped state. In addition, when the high level signal SELb is supplied to the switch SW2 of the line Lb, the switch SW2 is turned on, and the input terminal and the output terminal of the flip-flop FF1 are turned on. Therefore, it is possible to connect the output terminal of the flip-flop FF1 of the line La of the upper stage and the input terminal of the flip-flop FF1 (not shown) of the line La of the next stage, thereby forming a series connection of the flip-flop FF1 of the line La Shift register.

FIG. 5B is an example of the structure of the register 110 when the line La is in the non-selected state and the line Lb is in the selected state. At this time, a signal SELa showing a non-selected state is supplied to the line La, and a signal SELb showing a selected state is supplied to the line Lb. Therefore, it constitutes a shift register that stops the power supply to the line La and connects the flip-flop FF1 of the line Lb in series.

The specific structure of the switches SW1 and SW2 is not particularly limited, and can be appropriately set. 6A to 6C show structural examples of the switches SW1 and SW2.

Fig. 6A is an example of the structure when the p-channel transistor Tr1 is used as the switch SW1 and the analog switch AS1 is used as the switch SW2. The gate of the transistor Tr1 is connected to the wiring supplied with the signal SELa or the signal SELb, one of the source and drain is connected to the flip-flop FF1, and the other of the source and drain is connected to the one supplied with the high power supply potential VDD. Wiring connection. The first terminal of the analog switch AS1 is connected to the input terminal of the flip-flop FF1, and the second terminal is connected to the output terminal of the flip-flop FF1.

The signal SELa or the signal SELb and its inverted signal are input to the analog switch AS1. When the transistor Tr1 is turned on, the analog switch AS1 is turned off, and when the transistor Tr1 is turned off, the analog switch AS1 is turned on. The inverted signal of the signal SELa or the inverted signal of the signal SELb is output from the inverter INV1.

In addition, as shown in FIG. 6B, an n-channel transistor Tr2 can also be used instead of the analog switch AS1. The gate of the transistor Tr2 is connected to the wiring of the supplied signal SELa or the signal SELb, one of the source and drain is connected to the input terminal of the flip-flop FF1, and the other of the source and drain is connected to the flip-flop FF1 The output terminal is connected.

In addition, as the transistor Tr2, an OS transistor can be used. In this case, since the off-state current of the transistor Tr2 can be reduced, the misoperation of the register 110 can be prevented. In addition, by using a p-channel type transistor as the transistor Tr2, the gate electrode of the transistor Tr2 may be supplied with an inverted signal of the signal SELa or an inverted signal of the signal SELb.

In addition, although the switch SW1 is provided between the flip-flop FF1 and the wiring supplied with the high power supply potential VDD in FIGS. 4, 5A, and 5B, the switch SW1 may also be provided between the flip-flop FF1 and the wiring supplied with the low power supply potential. Between the wiring of VSS. In this case, as shown in FIG. 6C, it is preferable to use an n-channel type transistor Tr3 as the switch SW1. Note that the polarities of the signals SELa and SELb shown in FIG. 6C are opposite to those of the signals SELa and SELb shown in FIG. 6A.

As the transistor Tr3, an OS transistor is preferably used. In this case, while the register 110 is in the non-selected state, the power supplied to the flip-flop FF1 can be suppressed to be extremely small. Therefore, the power consumption of the register 110 can be further reduced.

In addition, n-channel type transistors may be used as the transistor Tr1, and p-channel type transistors may also be used as the transistors Tr2 and Tr3.

As described above, by selectively supplying power to the register 110 included in the line L that supplies the image signal to the wiring SL, the power consumption of the shift register 51 can be reduced.

[Structural example of latch circuit and decoder]

FIG. 7 shows an example of the structure of a plurality of latch circuits 120 and a decoding circuit 52 including a plurality of decoders 130. The latch circuit 120 has a function of holding the input signal SD and outputting the signal SD to the decoder 130 at a locked timing. The decoder 130 has a function of decoding the signal SD and outputting it to the latch circuit 140. Note that although the latch circuit 120 and the decoder 130 belonging to the lines La[1], Lb[1], La[2], and Lb[2] are shown here, other latch circuits 120 and decoders 130 may also be used. Have the same structure.

The latch circuit 120 includes a switch SW3 and a flip-flop FF2. The first terminal of the switch SW3 is connected to the flip-flop FF2, and the second terminal is connected to the wiring supplied with the high power supply potential VDD. The output terminal of the flip-flop FF2 is connected to the decoder 130 belonging to the same line L. The signal SD as a video signal is supplied to the input terminal of the flip-flop FF2. In addition, the signal output from the register 110 belonging to the same line L and the reset signal RST are supplied to the flip-flop FF2. The timing of the signal output from the latch circuit 120 is controlled by the sampling pulse input from the register 110.

The decoder 130 includes a switch SW4 and a conversion circuit 131. The conversion circuit 131 has a function of converting the signal input from the latch circuit 120 into a control signal for controlling the operation of the selection circuit 160. The first terminal of the switch SW4 is connected to the switching circuit 131, and the second terminal is connected to the wiring to which the high power supply potential VDD is supplied. The input terminal of the conversion circuit 131 is connected to the latch circuit 120 belonging to the same line L, and the output terminal is connected to the latch circuit 140 belonging to the same line L.

The conduction state of the switches SW3 and SW4 included in the line La is controlled by the signal SELa, and the conduction state of the switches SW3 and SW4 included in the line Lb is controlled by the signal SELb. In the line L selected by the signal SELa or SELb, the switch SW3 and the switch SW4 are turned on, and the power supply potential is supplied to the flip-flop FF2 and the conversion circuit 131. On the other hand, in the line L in the non-selected state, the switch SW3 and the switch SW4 are turned off, and the supply of the power supply potential to the flip-flop FF2 and the conversion circuit 131 is stopped. In this way, by selectively supplying power to the latch circuit 120 and the decoder 130 included in the line L for generating the image signal, the power consumption of the decoding circuit 52 can be reduced.

In addition, as the switches SW3 and SW4, p-channel type transistors connected to the wiring to which the high power supply potential VDD is supplied can be used (see FIGS. 6A and 6B). In addition, as the switches SW3 and SW4, n-channel transistors connected to the wiring to which the low power supply potential VSS is supplied may be used (see FIG. 6C).

[Structural example of latch circuit and level shifter]

FIG. 8 shows an example of the structure of the level shifter circuit 53 including a plurality of latch circuits 140 and a plurality of level shifters 150. The latch circuit 140 has a function of holding the input signal and outputting the signal to the level shifter 150 at a locked timing. The level shifter 150 has a function of converting the level of the signal input from the latch circuit 140 and outputting it to the selection circuit 160. Note that although the latch circuit 140 and the level shifter 150 belonging to the lines La[1], Lb[1], La[2], and Lb[2] are shown here, the other latch circuits 140 and level shifters The device 150 may also have the same structure.

The latch circuit 140 includes a switch SW5 and a flip-flop FF3. The first terminal of the switch SW5 is connected to the flip-flop FF3, and the second terminal is connected to the wiring supplied with the high power supply potential VDD. The input terminal of the flip-flop FF3 is connected to the decoder 130 belonging to the same line L, and the output terminal is connected to the level shifter 150 belonging to the same line L. In addition, the signal LS and the reset signal RST are supplied to the flip-flop FF3. The timing of the signal output from the latch circuit 140 is controlled by the signal LS.

The level shifter 150 includes a switch SW6 and a conversion circuit 151. The conversion circuit 151 has a function of converting the potential input from the latch circuit 140 into a potential for controlling the operation of the selection circuit 160 using the high power supply potential VDDH. The first terminal of the switch SW6 is connected to the switching circuit 151, and the second terminal is connected to the wiring to which the low power supply potential VSS is supplied. The input terminal of the conversion circuit 151 is connected to the latch circuit 140 belonging to the same line L, and the output terminal is connected to the selection circuit 160 belonging to the same line L.

The conduction state of the switch SW5 included in the line La is controlled by the signal SELa, and the conduction state of the switch SW5 included in the line Lb is controlled by the signal SELb. In addition, the conduction state of the switch SW6 included in the line La is controlled by a signal that uses an inverter INV2a to invert the signal SELa, and the conduction state of the switch SW6 included in the line Lb is controlled by a signal that uses an inverter INV2b to invert the signal SELb. control.

In the line L selected by the signal SELa or SELb, the switch SW5 and the switch SW6 are turned on, and the power supply potential is supplied to the flip-flop FF3 and the conversion circuit 151. On the other hand, in the line L in the non-selected state, the switch SW5 and the switch SW6 are turned off, and the supply of the power supply potential to the flip-flop FF3 and the conversion circuit 151 is stopped. In this way, by selectively supplying power to the latch circuit 140 and the level shifter 150 included in the line L generating the image signal, the power consumption of the level shifter circuit 53 can be reduced.

Here, when a transistor is used as the switch SW6, the switch SW6 is preferably provided between the switching circuit 151 and the wiring to which the low power supply potential VSS is supplied. FIG. 9 shows a structure in which a p-type transistor Tr4 is used as the switch SW5 and an n-type transistor Tr5 is used as the switch SW6. When a p-channel type transistor is provided between the switching circuit 151 and the wiring supplied with the high power supply potential VDDH as the switch SW6, the high power supply potential VDDH is supplied to one of the source and drain of the transistor. Therefore, in order to turn the transistor into the off state, it is necessary to supply a high potential to the gate, and sometimes it is necessary to shift the levels of the signals SELa and SELb. On the other hand, as shown in FIG. 9, when an n-type transistor Tr5 is provided between the switching circuit 151 and the wiring to which the low power supply potential VSS is supplied as the switch SW6, and the reverse of the signals SELa and SELb is supplied to the gate of the transistor Tr5 When the signal is turned, there is no need to separately set the potential for controlling the conduction state of the transistor Tr5, so that the power supply to the conversion circuit 151 can be easily controlled.

[Structure example of selection circuit and potential generation circuit]

FIG. 10 shows an example of the structure of the selection circuit 160. The selection circuit 160 has a function of outputting a potential corresponding to the video signal (signal SD) based on the control signal generated by the decoder 130 and the level shifter 150. Here, as an example, it is described that the signals P[0] to [6] and the inverted signals PB[0] to [6] and the signal PB[7] are input from the level shifter 150 as the control signal and generated from the potential The circuit 170 inputs 256 kinds of reference potentials Vref (Vref[0] to [255]). However, the number of control signals input from the level shifter 150 and the number of potentials input from the potential generating circuit 170 can be appropriately set according to the number of gray scales displayed by the pixels. Note that among the potentials input from the potential generation circuit 170, the lowest is Vref[0], which increases in the order from Vref[0] to Vref[255].

The selection circuit 160 includes a circuit 161P composed of a p-channel type transistor and a circuit 161N composed of an n-channel type transistor. The reference potentials Vref[0] to [127] are input to the circuit 161N, and the reference potentials Vref[128] to [255] are input to the circuit 161P. The selection circuit 160 selects any of the reference potentials Vref[0] to [255] according to the control signal input from the level shifter 150, and outputs it to the amplifier 180. That is, the selection circuit 160 has a function of outputting a potential (analog value) corresponding to a control signal generated based on the signal SD as a video signal. Therefore, it is possible to perform DA conversion of the video signal.

The structure shown in FIG. 10 can be applied to the selection circuit 160 belonging to either of the lines La and Lb. However, since the reference potential Vref is set according to the structure of the pixel to which the image signal is supplied or the type of display element, etc., when the structure of the pixel 31a and the pixel 31b (refer to FIGS. 1A, 1B, and 2) are different, The selection circuit 160 belonging to the line La and the selection circuit 160 belonging to the line Lb are respectively supplied with different reference potentials Vref. In addition, the reference potential Vref supplied to the selection circuit 160 belonging to the line La is generated by the potential generation circuit 170a, and the reference potential Vref supplied to the selection circuit 160 belonging to the line Lb is generated by the potential generation circuit 170b.

FIG. 11 shows an example of the structure of the potential generation circuit 170. The potential generation circuit 170 has a function of generating a reference potential Vref supplied to the selection circuit 160 using the reference potential VR. Here, although an example is shown in which the reference potentials Vref[0] to [255] are generated from the reference potentials VR[0] to [8], the number of reference potentials VR is appropriately set according to the number of generated reference potentials Vref.

The reference potentials VR[0] to [8] are respectively supplied to the selection circuit 160 through the switches SW7[0] to [8] and used as the reference potential Vref. The reference potentials VR[0] to [8] in FIG. 11 are used as the reference potentials Vref[0], [32], [64], [96], [128], [160], [192], [ 224], [255]. In addition, a resistor R1 connected in series is provided between the wirings supplied with the reference potentials VR[0] to [8]. By dividing the difference between the two adjacent reference potentials VR by the resistor R1, the potential between the two reference potentials VR can be generated and these potentials can be used as reference potentials Vref other than the above nine kinds. Therefore, the reference potentials Vref[0] to [255] can be generated. Note that the number of resistors R1 is set according to the number of generated reference potentials Vref.

The structure shown in FIG. 11 can be applied to either of the potential generating circuits 170a and 170b. However, when the reference potential Vref used by the selection circuit 160 belonging to the line La and the selection circuit 160 belonging to the line Lb are different, different reference potentials VR are supplied to the potential generating circuits 170a and 170b, respectively.

In addition, the conduction state of the switches SW7[0] to [8] of the potential generation circuit 170a is controlled by the signal SELa, and the conduction state of the switches SW7[0] to [8] of the potential generation circuit 170b is controlled by the signal SELb. The switch SW7 has a function of controlling whether to generate the reference potential Vref. When the signal SELa or the signal SELb for turning the switch SW7 into an on state is supplied to the switch SW7, the reference potential Vref is generated based on the reference potential VR. On the other hand, when the signal SELa or the signal SELb for turning the switch SW7 into the off state is supplied to the switch SW7, the reference potential Vref is not generated. Therefore, the reference potential Vref can be selectively supplied to the selection circuit 160 included in the line L generating the image signal, and the power consumption of the DA conversion circuit 54 can be reduced.

As the switch SW7, a transistor that supplies a signal SEL to the gate and a reference potential VR to one of the source and drain can be used. In addition, an analog switch can also be used as the switch SW7.

[Example of the structure of the amplifier]

FIG. 12 shows a configuration example of the amplifying circuit 55 including a plurality of amplifiers 180. The amplifier 180 is a circuit having a function of amplifying the potential input from the selection circuit 160 and supplying it to the wiring SL. Note that although the amplifiers 180 belonging to the lines La[1], Lb[1], La[2], and Lb[2] are shown here, other amplifiers 180 may also have the same structure.

The amplifier 180 includes a switch SW8, a switch SW9, an operational amplifier OP1, and an inverter INV3. The first terminal of the switch SW8 is connected to the operational amplifier OP1, and the second terminal is connected to the wiring supplied with the low power supply potential VSS. The first terminal of the switch SW9 is connected to the output terminal of the operational amplifier OP1, and the second terminal is connected to the wiring supplied with the fixed potential Vcom. The output terminal of the operational amplifier OP1 is connected to the inverting input terminal of the operational amplifier OP1 and the wiring SL. The potential supplied from the selection circuit 160 is input to the non-inverting input terminal of the operational amplifier OP1.

The operational amplifier OP1 has a function of supplying a potential corresponding to the signal input to the non-inverting input terminal to the wiring SL. Therefore, the image signal can be supplied to the wiring SL.

The conduction states of the switches SW8 and SW9 included in the amplifier 180 belonging to the line La are respectively controlled by the inverted signal of the signal SELa and the signal SELa supplied from the inverter INV3. The conduction states of the switches SW8 and SW9 included in the amplifier 180 belonging to the line Lb are respectively controlled by the inverted signal of the signal SELb and the signal SELb supplied from the inverter INV3.

In the line L selected by the signal SELa or SELb, the switch SW8 is turned on and the switch SW9 is turned off, and the power supply potential is supplied to the operational amplifier OP1. On the other hand, in the line L in the non-selected state, the switch SW8 is turned off, and the supply of the power supply potential to the operational amplifier OP1 is stopped. In this way, by selectively supplying power to the amplifier 180 included in the line L that supplies the image signal to the wiring SL, the power consumption of the amplifier circuit 55 can be reduced. In addition, in the line L in the non-selected state, the switch SW9 is turned on, and the fixed potential Vcom is supplied to the wiring SL. Therefore, the potential of the wiring SL during the period when the amplifier 180 is not selected can be prevented from fluctuating.

As the switches SW8 and SW9, transistors can be used. FIG. 13 shows a structure in which n-channel transistors Tr6 and Tr7 are used as switches SW8 and SW9, respectively.

The gate of the transistor Tr6 is connected to the output terminal of the inverter INV3, one of the source and drain is connected to the operational amplifier OP1, and the other of the source and drain is connected to the wiring supplied with the low power supply potential VSS. The gate of the transistor Tr7 is connected to the wiring supplied with the signal SEL, one of the source and drain is connected to the wiring SL, and the other of the source and drain is connected to the wiring supplied with the fixed potential Vcom.

As the transistors Tr6 and Tr7, OS transistors are preferably used. In the case of using the OS transistor as the transistor Tr6, the current flowing through the transistor Tr6 can be minimized while the amplifier 180 is in the non-selected state, and the power supply can be stopped more effectively. In addition, when the OS transistor is used as the transistor Tr7, the potential fluctuation of the wiring SL can be extremely small while the amplifier 180 is in the selected state.

As described above, the power supply to each of the register 110, the latch circuit 120, the decoder 130, the latch circuit 140, the level shifter 150, the selection circuit 160, and the amplifier 180 can be separately controlled. Therefore, in FIG. 3, it is possible to supply power to the line L that generates the image signal and stop the power supply to the line L that does not generate the image signal. Therefore, even when the driving circuit 50 shown in FIGS. 1A and 1B is shared by the pixel groups 30a and 30b, it is possible to stop supplying power to circuits that are not used when generating image signals, thereby realizing the area of the driving circuit at the same time. The reduction of power consumption and the reduction of power consumption.

This embodiment mode can be combined with descriptions of other embodiments as appropriate.

Embodiment 2

In this embodiment, a modified example of the drive circuit described in the above embodiment will be described.

<Modification example 1>

FIG. 14 shows an example of the structure of the driving circuit 50. The driving circuit 50 shown in FIG. 14 is different from FIG. 3 in that the signal output from the decoding circuit 52 is selectively supplied to the latch circuit 140 belonging to the line La and the latch circuit 140 belonging to the line Lb. One. That is, the driving circuit 50 shown in FIG. 14 has a structure in which the register 110, the latch circuit 120, and the decoder 130 are shared by the line La and the line Lb.

The driving circuit 50 includes a switch SW10 between the decoding circuit 52 and the level shifter circuit 53. The switch SW10 has a function of selecting the latch circuit 140 connected to the decoder 130. Specifically, the switch SW10 has a function of connecting one of the latch circuit 140 belonging to the line La and the latch circuit 140 belonging to the line Lb with the decoder 130.

FIG. 15A shows a specific structural example of the switch SW10. The switch SW10 includes an inverter INV4, an analog switch AS2, and an analog switch AS3. The first terminal of the analog switch AS2 is connected to the decoder 130, and the second terminal is connected to the latch circuit 140 belonging to the line La. The first terminal of the analog switch AS3 is connected to the decoder 130, and the second terminal is connected to the latch circuit 140 belonging to the line Lb. The signal SDEC and the signal SDEC inverted by the inverter INV4 are input to the analog switches AS2 and AS3, respectively. In addition, the signal SDEC has a function of selecting the line L connected to the decoder 130.

When the signal SDEC selects the line La, the analog switch AS2 is turned on and the analog switch AS3 is turned off, and the decoder 130 is connected to the latch circuit 140 belonging to the line La. On the other hand, when the signal SDEC selects the line Lb, the analog switch AS2 is turned off, the analog switch AS3 is turned on, and the decoder 130 is connected to the latch circuit 140 belonging to the line Lb. In this way, by using the switch SW10, the latch circuit 140 supplied with the signal output from the decoder 130 can be selected.

In addition, the second terminal of the analog switch AS2 is connected to a wiring supplied with a fixed potential through a resistor R2a, and the second terminal of the analog switch AS3 is connected to a wiring supplied with a fixed potential through a resistor R2b. As a result, it is possible to prevent the intermediate potential from being input to the latch circuit 140 when the analog switch AS2 or AS3 is in the closed state.

In addition, as shown in FIG. 15B, the switches SW20a and SW20b may be used instead of the resistors R2a and R2b. The conduction state of the switches SW20a and SW20b is controlled by the signal SDEC. The analog switch AS2 and the switch SW20a are controlled to be turned on in the opposite state, and the analog switch AS3 and the switch SW20b are controlled to be turned on to the opposite state.

The drive circuit 50 shown in FIG. 14 corresponds to a structure in which the functions of the respective circuits shown in FIG. 3 can be shared by the line La and the line Lb, the register 110, the latch circuit 120, and the decoder 130 in common. In this way, by sharing a circuit whose function can be used in common in the driving circuit 50, the area of the driving circuit 50 can be reduced.

Note that when both the line La and the line Lb are selected in FIG. 14, the register 110, the latch circuit 120, and the decoder 130 are preferably driven at double speed. Therefore, it is possible to display an image in the pixel portion 20 without reducing the frame frequency.

<Modification example 2>

FIG. 16 shows an example of the structure of the driving circuit 50. The drive circuit 50 shown in FIG. 16 is equivalent to the configuration in which the holding circuit 56 is provided in place of the amplifier circuit 55 in FIG. 14. The holding circuit 56 has a function of holding the potential input from the DA conversion circuit 54 and maintaining the potential output to the wiring SL.

The holding circuit 56 includes a plurality of sample holding circuits 190. The sample-and-hold circuit 190 has a function of holding the potential input from the selection circuit 160 and outputting the potential to the wiring SL. As a result, the image signal can be continuously supplied to the wiring SL while the sample-and-hold circuit 190 maintains the potential. FIG. 17 shows an example of the structure of the sample-and-hold circuit 190.

The sample-and-hold circuit 190 shown in FIG. 17 includes a transistor Tr8, a capacitor C1, and an operational amplifier OP2. Note that although the sample-and-hold circuits 190 belonging to the lines La[1], Lb[1], La[2], and Lb[2] are shown here, other sample-and-hold circuits 190 may have the same structure.

One of the source and drain of the transistor Tr8 is connected to the selection circuit 160 belonging to the same line L, and the other of the source and drain is connected to an electrode of the capacitor C1 and the non-inverting input terminal of the operational amplifier OP2 . The other electrode of the capacitor C1 is connected to a wiring supplied with a fixed potential. The output terminal of the operational amplifier OP2 is connected to the inverting input terminal of the operational amplifier OP2 and the wiring SL. In addition, the signal SSHa is supplied to the gate of the transistor Tr8 included in the sample-and-hold circuit 190 belonging to the line La, and the signal SSHb is supplied to the gate of the transistor Tr8 included in the sample-and-hold circuit 190 belonging to the line Lb.

When the high-level potential is supplied as the signal SSHa or the signal SSHb, the transistor Tr8 is turned on, and the potential input from the selection circuit 160 is supplied to the capacitor C1. Then, when the low-level potential is supplied as the signal SSHa or the signal SSHb, the transistor Tr8 is turned off, and the potential of one electrode of the capacitor C1 is stored.

While the transistor Tr8 is in the off state, the potential of one electrode of the capacitor C1 is output from the output terminal of the operational amplifier OP2. Therefore, even when the selection circuit 160 is not supplying a potential, the image signal can be supplied to the wiring SL, and thus the image displayed by the pixel group 30 can be maintained.

In addition, as the transistor Tr8, an OS transistor is preferably used. Therefore, the potential of one electrode of the capacitor C1 can be stored for a long period of time, so that the image displayed by the pixel group 30 can be maintained for a long period of time.

For example, when the image displayed by the pixel group 30a in FIGS. 1A and 1B is a still image, the potential of the wiring SLa can be maintained by maintaining the potential in the sample-and-hold circuit 190 belonging to the line La. Therefore, the frequency of the image signal generated in the line La can be reduced, and the power supply to the register 110, the latch circuit 120, the decoder 130, the latch circuit 140, the level shifter 150, and the selection circuit 160 belonging to the line La can be stopped. . As a result, the power consumption of the drive circuit 50 can be reduced.

In addition, the drive circuit 50 may include both the amplifier circuit 55 and the holding circuit 56.

This embodiment mode can be combined with descriptions of other embodiments as appropriate.

Embodiment 3

In this embodiment, a specific configuration example of a display device according to an embodiment of the present invention will be explained.

As described above, different display elements can be provided in the pixels 31a, 31b shown in FIGS. 1A and 1B, etc. Next, an example of the structure of the pixel portion when different display elements are provided in the pixels 31a and 31b will be described. Note that here, a configuration example of a display device in which a reflective liquid crystal element is provided in the pixel 31a and a light-emitting element is provided in the pixel 31b is described as an example.

The display device of this embodiment includes a first mode that uses reflective liquid crystal elements to display images, a second mode that uses light-emitting elements to display images, and a third mode that uses reflective liquid crystal elements and light-emitting elements to display images. The display device can automatically display images. Or manually switch these modes to use.

In the first mode, an image is displayed using a reflective liquid crystal element and external light. Because the first mode does not use a light source, the power consumption is extremely low. For example, when external light is sufficiently incident on the display device (under a bright environment, etc.), the light reflected by the reflective liquid crystal element can be used for display. For example, the first mode is effective when the external light is sufficiently strong and the external light is white light or similar light. The first mode is a mode suitable for displaying text. In addition, because the light that reflects external light is used in the first mode, it is possible to perform eye protection display and have the effect that the eyes are not easily tired.

In the second mode, the image is displayed using the light emission of the light-emitting element. As a result, it is possible to perform extremely vivid (high contrast and high color reproducibility) display regardless of the illuminance and the chromaticity of external light. For example, the second mode is effective when the illuminance is extremely low at night or in a dark room. In addition, when the surroundings are dark, the bright display sometimes makes the user feel dazzling. In order to prevent such a problem from occurring, it is preferable to perform display with suppressed brightness in the second mode. As a result, not only can the glare be suppressed, but also the power consumption can be reduced. The second mode is a mode suitable for displaying vivid images (still images and moving images), etc.

In the third mode, display is performed using both the reflected light of the reflective liquid crystal element and the light emission of the light emitting element. Not only can display more vividly than the first mode, but also can make the power consumption smaller than the second mode. For example, the third mode is effective in situations where the illuminance is low under indoor lighting, in the morning and evening, or in situations where the chromaticity of external light is not white. In addition, by using a mixture of reflected light and luminous light, it is possible to display an image as if seeing a painting.

By adopting the above structure, it is possible to realize a display device or an all-weather display device with high visibility and high convenience regardless of the surrounding brightness.

The display device of this embodiment includes a plurality of pixels 31a having reflective liquid crystal elements and a plurality of pixels 31b having light-emitting elements. As shown in FIG. 2, the pixels 31a and the pixels 31b are preferably arranged in a matrix.

The pixel 31a and the pixel 31b may each include more than one sub-pixel. For example, the pixel may adopt a structure with one sub-pixel (white (W), etc.), a structure with three sub-pixels (three colors of red (R), green (G) and blue (B), or yellow (Y), Three colors of cyan (C) and magenta (M), etc.), a structure with four sub-pixels (four colors of red (R), green (G), blue (B), white (W), etc.), or red ( R), green (G), blue (B), yellow (Y) four colors, etc.).

In the display device of this embodiment, it is possible to adopt a configuration in which both the pixels 31a and the pixels 31b perform full-color display. In addition, in the display device of this embodiment, a structure in which the pixel 31a performs black-and-white display or gray-scale display, and the pixel 31b performs full-color display may be adopted. The black-and-white display or gray-scale display using the pixels 31a is suitable for displaying information that does not require color display, such as displaying document information.

<Example of the structure of the display device>

An example of the structure of the display device of this embodiment will be described with reference to FIGS. 18 to 21.

[Structure example 1]

FIG. 18 is a schematic perspective view of the display device 600. The display device 600 has a structure in which a substrate 651 and a substrate 661 are bonded together. In FIG. 18, the substrate 661 is indicated by a broken line.

The display device 600 includes a display portion 662, a circuit 664, wiring 665, and the like. Fig. 18 shows an example in which an IC (Integrated Circuit) 673 and an FPC672 are mounted in the display device 600. As shown in Figs. Therefore, the structure shown in FIG. 18 can also be referred to as a display module including the display device 600, the IC673, and the FPC672.

As the circuit 664, for example, a scanning line driver circuit can be used.

The wiring 665 has a function of supplying signals and power to the display unit 662 and the circuit 664. This signal and power are input to the wiring 665 via FPC672 or IC673 from the outside.

FIG. 18 shows an example in which the IC673 is provided on the substrate 651 by a COG (Chip On Glass) method or a COF (Chip on Film) method or the like. As the IC 673, for example, an IC including a scanning line driver circuit, a signal line driver circuit, or the like can be used. Note that the display device 600 and the display module do not necessarily need to be provided with an IC. In addition, the IC can also be mounted on the FPC using the COF method or the like.

FIG. 18 shows an enlarged view of a part of the display portion 662. In the display portion 662, electrodes 611b included in a plurality of display elements are arranged in a matrix. The electrode 611b has a function of reflecting visible light, and is used as a reflective electrode of the liquid crystal element.

In addition, as shown in FIG. 18, the electrode 611b has an opening 451. Furthermore, the display portion 662 includes a light-emitting element on the side closer to the substrate 651 than the electrode 611b. The light from the light emitting element is emitted to the side of the substrate 661 through the opening 451 of the electrode 611b. The area of the light-emitting region of the light-emitting element and the area of the opening 451 may be the same. One of the area of the light-emitting region of the light-emitting element and the area of the opening 451 is preferably larger than the other because the room for dislocation can be increased. In particular, the area of the opening 451 is preferably larger than the area of the light-emitting region of the light-emitting element. When the opening 451 is small, a part of the light from the light-emitting element is sometimes shielded by the electrode 611b and cannot be extracted to the outside. When the opening 451 is sufficiently large, waste of light emission of the light-emitting element can be suppressed.

FIG. 19 shows an example of the cross section of a part of the area including the FPC 672, a part of the area including the circuit 664, and a part of the area including the display portion 662 of the display device 600 shown in FIG. 18.

The display device 600 shown in FIG. 19 includes a transistor 501, a transistor 503, a transistor 505, a transistor 506, a liquid crystal element 480, a light-emitting element 470, an insulating layer 520, a color layer 431, and a color layer between a substrate 651 and a substrate 661. Layer 434 and so on. The substrate 661 and the insulating layer 520 are bonded by the bonding layer 441. The substrate 651 and the insulating layer 520 are bonded by an adhesive layer 442.

The substrate 661 is provided with a color layer 431, a light shielding layer 432, an insulating layer 421, an electrode 413 used as a common electrode of the liquid crystal element 480, an alignment film 433b, an insulating layer 417, and the like. A polarizing plate 435 is included on the outer surface of the substrate 661. The insulating layer 421 may have a function of a planarization layer. By using the insulating layer 421, the surface of the electrode 413 can be made substantially flat, and the alignment state of the liquid crystal layer 412 can be made uniform. The insulating layer 417 is used as a spacer for maintaining the cell gap of the liquid crystal element 480. When the insulating layer 417 transmits visible light, the insulating layer 417 may overlap the display area of the liquid crystal element 480.

The liquid crystal element 480 is a reflective liquid crystal element. The liquid crystal element 480 has a laminated structure in which an electrode 611a used as a pixel electrode, a liquid crystal layer 412, and an electrode 413 are laminated. An electrode 611b that reflects visible light is provided in contact with the side of the substrate 651 of the electrode 611a. The electrode 611b has an opening 451. The electrode 611a and the electrode 413 transmit visible light. An alignment film 433a is provided between the liquid crystal layer 412 and the electrode 611a. An alignment film 433b is provided between the liquid crystal layer 412 and the electrode 413.

In the liquid crystal element 480, the electrode 611b has a function of reflecting visible light, and the electrode 413 has a function of transmitting visible light. The light incident from the side of the substrate 661 is polarized by the polarizer 435, passes through the electrode 413 and the liquid crystal layer 412, and is reflected by the electrode 611b. Then, it passes through the liquid crystal layer 412 and the electrode 413 again, and reaches the polarizing plate 435. At this time, the alignment of the liquid crystal can be controlled by the voltage applied between the electrode 611b and the electrode 413 to control the optical modulation of the light. In other words, the intensity of the light emitted through the polarizing plate 435 can be controlled. In addition, since light outside the specific wavelength region is absorbed by the color layer 431, the extracted light appears red, for example.

As shown in FIG. 19, the opening 451 is preferably provided with an electrode 611a that transmits visible light. As a result, the liquid crystal layer 412 is aligned in the region overlapping with the opening 451 in the same manner as in other regions, and it is possible to suppress the occurrence of unintended light leakage due to poor alignment of the liquid crystal in the boundary portion of the region.

In the connection portion 507, the electrode 611b is connected to the conductive layer 522a included in the transistor 506 via the conductive layer 521b. The transistor 506 has a function of controlling the driving of the liquid crystal element 480.

A connection part 552 is provided in the area where a part of the adhesive layer 441 is provided. In the connection portion 552, a conductive layer obtained by processing the same conductive film as the electrode 611a and a part of the electrode 413 are connected by the connector 543. Thereby, the signal or potential input from the FPC 672 connected to the side of the substrate 651 can be supplied to the electrode 413 formed on the side of the substrate 661 through the connection part 552.

For example, the connector 543 may use conductive particles. As the conductive particles, particles of organic resin or silicon dioxide whose surfaces are covered with a metal material can be used. As the metal material, nickel or gold is preferably used because it can reduce contact resistance. In addition, it is preferable to use particles in which two or more kinds of metal materials are covered in layers such as gold and the like on nickel. In addition, the connector 543 is preferably made of a material that can be elastically deformed or plastically deformed. At this time, the connector 543 of conductive particles may have a shape squashed in the longitudinal direction as shown in FIG. 19. By having this shape, the contact area between the connector 543 and the conductive layer electrically connected to the connector can be increased, thereby reducing the contact resistance and preventing the occurrence of problems such as poor contact.

The connector 543 is preferably configured to be covered by the adhesive layer 441. For example, the connectors 543 may be dispersed in the adhesive layer 441 before curing.

The light emitting element 470 is a bottom emission type light emitting element. The light-emitting element 470 has a laminated structure in which an electrode 491 used as a pixel electrode, an EL layer 492, and an electrode 493 used as a common electrode are laminated in this order from the insulating layer 520 side. The electrode 491 is connected to the conductive layer 522b included in the transistor 505 through an opening formed in the insulating layer 514. The transistor 505 has a function of controlling the driving of the light-emitting element 470. The insulating layer 516 covers the end of the electrode 491. The electrode 493 includes a material that reflects visible light, and the electrode 491 includes a material that transmits visible light. The insulating layer 494 is provided so as to cover the electrode 493. The light emitted by the light emitting element 470 is emitted to the side of the substrate 661 through the color layer 434, the insulating layer 520, the opening 451, the electrode 611a, and the like.

When the color of the color layer is changed between pixels, the liquid crystal element 480 and the light emitting element 470 can exhibit various colors. The display device 600 can perform color display using the liquid crystal element 480. The display device 600 can use the light-emitting element 470 to perform color display.

The transistor 501, the transistor 503, the transistor 505, and the transistor 506 are all formed on the surface of the insulating layer 520 on the side of the substrate 651. These transistors can be manufactured by the same manufacturing process.

The circuit electrically connected to the liquid crystal element 480 is preferably formed on the same surface as the circuit connected to the light emitting element 470. Thus, compared with the case where two circuits are formed on different surfaces, the thickness of the display device can be reduced. In addition, since two transistors can be manufactured by the same manufacturing process, the manufacturing process can be simplified compared with the case where two transistors are formed on different surfaces.

The pixel electrode of the liquid crystal element 480 is located at a position opposite to the gate insulating layer of the transistor and the pixel electrode of the light-emitting element 470.

Here, when an OS transistor is used as the transistor 506 or a memory element connected to the transistor 506 is used, the gray scale can be maintained even if the writing operation to the pixel is stopped when the liquid crystal element 480 is used to display a static image. In other words, the display can be maintained even if the frame frequency is extremely small. In one embodiment of the present invention, the frame frequency can be made extremely small and drive with low power consumption can be performed.

In addition to the transistor 503, a transistor used to control whether to select a pixel (also called a switching transistor or a selection transistor) can also be provided. The transistor 505 is a transistor (also referred to as a driving transistor) that controls the current flowing through the light-emitting element 470.

Insulating layers such as an insulating layer 511, an insulating layer 512, an insulating layer 513, and an insulating layer 514 are provided on the substrate 651 side of the insulating layer 520. A part of the insulating layer 511 is used as a gate insulating layer of each transistor. The insulating layer 512 is provided in such a way as to cover the transistor 506 and the like. The insulating layer 513 is provided so as to cover the transistor 505 and the like. The insulating layer 514 is used as a planarization layer. Note that there is no particular limitation on the number of insulating layers covering the transistor, and it may be one or two or more.

Preferably, a material that does not easily diffuse impurities such as water or hydrogen is used to cover at least one of the insulating layers of each transistor. Thus, the insulating layer can be used as a barrier film. By adopting this structure, the diffusion of impurities from the outside into the transistor can be effectively suppressed, so that a highly reliable display device can be realized.

Transistor 501, Transistor 503, Transistor 505, and Transistor 506 include: a conductive layer 521a used as a gate; an insulating layer 511 used as a gate insulating layer; and a conductive layer used as a source and drain 522a and conductive layer 522b; and semiconductor layer 531. Here, the same hatching is attached to a plurality of layers obtained by processing the same conductive film.

In addition to the structures of the transistor 503 and the transistor 506, the transistor 501 and the transistor 505 also include a conductive layer 523 used as a gate electrode.

As the transistor 501 and the transistor 505, a structure in which two gate electrodes sandwich the semiconductor layer including the channel formation region is adopted. By adopting this structure, the threshold voltage of the transistor can be controlled. In addition, it is also possible to connect two gates, and to drive the transistor by supplying the same signal to the two gates. Compared with other transistors, this type of transistor can increase the field effect mobility and increase the on-state current. As a result, a circuit capable of high-speed driving can be manufactured. Furthermore, the area occupied by the circuit section can be reduced. By using a transistor with a large on-state current, even if the number of wires increases due to an increase in the size or resolution of the display device, the signal delay of each wire can be reduced, and display unevenness can be suppressed.

Alternatively, by applying a potential for controlling the threshold voltage to one of the two gate electrodes and a potential for driving the other one, the threshold voltage of the transistor can be controlled.

There is no limitation on the structure of the transistor included in the display device. The transistor included in the circuit 664 and the transistor included in the display portion 662 may have the same structure or different structures. The multiple transistors included in the circuit 664 may all have the same structure, or may combine two or more structures. Similarly, the plurality of transistors included in the display portion 662 may all have the same structure, or two or more structures may be combined.

As the conductive layer 523, a conductive material containing oxide is preferably used. By forming a conductive film constituting the conductive layer 523 in an atmosphere containing oxygen, oxygen can be supplied to the insulating layer 512. Preferably, the ratio of oxygen gas in the deposition gas is 90% or more and 100% or less. The oxygen supplied into the insulating layer 512 is supplied to the semiconductor layer 531 by the subsequent heat treatment, whereby the reduction of oxygen defects in the semiconductor layer 531 can be achieved.

In particular, as the conductive layer 523, it is preferable to use a metal oxide with reduced resistance. At this time, it is preferable to use an insulating film that releases hydrogen to the insulating layer 513, such as a silicon nitride film. By the heat treatment during or after the film formation of the insulating layer 513, hydrogen is supplied to the conductive layer 523, thereby effectively reducing the resistance of the conductive layer 523.

A color layer 434 is provided in contact with the insulating layer 513. The color layer 434 is covered by an insulating layer 514.

The connection portion 504 is provided in a region of the substrate 651 that does not overlap the substrate 661. In the connection portion 504, the wiring 665 is connected to the FPC 672 via the connection layer 542. The connecting portion 504 has the same structure as the connecting portion 507. A conductive layer obtained by processing the same conductive film as the electrode 611a is exposed on the top surface of the connection portion 504. Therefore, the connection part 504 can be connected to the FPC 672 through the connection layer 542.

As the polarizing plate 435 provided on the outer surface of the substrate 661, either a linear polarizing plate or a circular polarizing plate may be used. As the circular polarizing plate, for example, a polarizing plate formed by stacking a linear polarizing plate and a quarter-wave retardation plate can be used. As a result, reflection of external light can be suppressed. In addition, by adjusting the cell gap, alignment, driving voltage, etc. of the liquid crystal element used for the liquid crystal element 480 according to the type of polarizing plate, a desired contrast can be achieved.

In addition, various optical members may be arranged on the outer surface of the substrate 661. As an optical member, a polarizing plate, a retardation plate, a light diffusion layer (diffusion film etc.), an anti-reflection layer, a condensing film, etc. can be used. In addition, an antistatic film that suppresses adhesion of dust, a water-repellent film that is not easily stained, a hard coat film that suppresses damage during use, and the like may be arranged on the outer surface of the substrate 661.

For the substrate 651 and the substrate 661, glass, quartz, ceramics, sapphire, organic resin, etc. can be used. By using flexible materials for the substrate 651 and the substrate 661, the flexibility of the display device can be improved.

When a reflective liquid crystal element is used, the polarizing plate 435 is arranged on the side of the display surface. In addition, when a light diffusion plate is additionally provided on one side of the display surface, the visibility can be improved, so it is preferable.

The front light source may be provided on the outer side of the polarizing plate 435. As the front light source, it is preferable to use an edge lighting type front light source. When a front light source equipped with LED (Light Emitting Diode) is used, power consumption can be reduced, so it is preferable.

[Structure example 2]

The main difference between the display device 600A shown in FIG. 20 and the display device 600 is that it does not include the transistor 501, the transistor 503, the transistor 505, and the transistor 506, but includes the transistor 581, the transistor 584, and the transistor 506. 585 and transistor 586.

The positions of the insulating layer 417 and the connecting portion 507 in FIG. 20 are also different from those in FIG. 19. Fig. 20 shows the end of the pixel. The insulating layer 417 is arranged to overlap the end of the color layer 431. The insulating layer 417 is arranged so as to overlap the end of the light shielding layer 432. In this way, the insulating layer may be provided in a portion that does not overlap with the display area (a portion that overlaps with the light shielding layer 432).

Like the transistor 584 and the transistor 585, the two transistors included in the display device may also be partially stacked. As a result, the area occupied by the pixel circuit can be reduced, and the fineness can be improved. In addition, the light-emitting area of the light-emitting element 470 can be increased, and the aperture ratio can be increased. When the aperture ratio of the light-emitting element 470 is high, the current density used to obtain the desired brightness can be reduced, so the reliability is improved.

The transistor 581, the transistor 584, and the transistor 586 include a conductive layer 521a, an insulating layer 511, a semiconductor layer 531, a conductive layer 522a, and a conductive layer 522b. The conductive layer 521a overlaps the semiconductor layer 531 with the insulating layer 511 interposed therebetween. The conductive layer 522a and the conductive layer 522b are electrically connected to the semiconductor layer 531. The transistor 581 includes a conductive layer 523.

The transistor 585 includes a conductive layer 522b, an insulating layer 517, a semiconductor layer 561, a conductive layer 523, an insulating layer 512, an insulating layer 513, a conductive layer 563a, and a conductive layer 563b. The conductive layer 522b overlaps the semiconductor layer 561 with the insulating layer 517 interposed therebetween. The conductive layer 523 overlaps the semiconductor layer 561 with the insulating layer 512 and the insulating layer 513 interposed therebetween. The conductive layer 563a and the conductive layer 563b are electrically connected to the semiconductor layer 561.

The conductive layer 521a is used as a gate electrode. The insulating layer 511 is used as a gate insulating layer. The conductive layer 522a is used as one of a source electrode and a drain electrode. The conductive layer 522b included in the transistor 586 is used as the other of the source and drain.

The conductive layer 522b shared by the transistor 584 and the transistor 585 has a portion used as the other of the source and drain of the transistor 584, and a portion used as the gate of the transistor 585. The insulating layer 517, the insulating layer 512, and the insulating layer 513 are used as gate insulating layers. One of the conductive layer 563a and the conductive layer 563b is used as a source, and the other of the conductive layer 563a and the conductive layer 563b is used as a drain. The conductive layer 523 is used as a gate.

[Structure example 3]

FIG. 21 shows a cross-sectional view of the display portion of the display device 600B.

The display device 600B shown in FIG. 21 includes a transistor 540, a transistor 580, a liquid crystal element 480, a light emitting element 470, an insulating layer 520, a color layer 431, a color layer 434, and the like between a substrate 651 and a substrate 661.

In the liquid crystal element 480, the electrode 611b reflects external light and emits the reflected light toward the substrate 661 side. The light emitting element 470 emits light toward the substrate 661 side.

The substrate 661 is provided with a color layer 431, an insulating layer 421, an electrode 413 used as a common electrode of the liquid crystal element 480, and an alignment film 433b.

The liquid crystal layer 412 is sandwiched between the electrode 611a and the electrode 413 via the alignment film 433a and the alignment film 433b.

The transistor 540 is covered by the insulating layer 512 and the insulating layer 513. The insulating layer 513 and the color layer 434 are bonded to the insulating layer 494 by the adhesive layer 442.

Since the display device 600B has the transistor 540 for driving the liquid crystal element 480 and the transistor 580 for driving the light-emitting element 470 formed on different surfaces, it can be easily formed using a structure and material suitable for driving each display element.

<Example of pixel structure>

Next, specific structural examples of pixels included in the display device will be described with reference to FIGS. 22A to 24B.

FIG. 22A is a block diagram of the display device 601. The display device 601 includes a display unit 662, a circuit GD, and a circuit SD. The display portion 662 includes a plurality of pixel units 690 arranged in a matrix. The display portion 662, the circuit GD, the circuit SD, and the pixel unit 690 respectively correspond to the pixel portion 20, the driving circuit 40, the driving circuit 50, and the pixel unit 21 in FIG. 2.

The display device 601 includes a plurality of wirings GLa, a plurality of wirings GLb, a plurality of wirings ANO, a plurality of wirings CSCOM, a plurality of wirings SLa, and a plurality of wirings SLb. The plurality of wirings GLa, the plurality of wirings GLb, the plurality of wirings ANO, and the plurality of wirings CSCOM are respectively connected to the plurality of pixel cells 690 and the circuit GD arranged in the direction indicated by the arrow R. The plurality of wirings SLa and the plurality of wirings SLb are respectively connected to the plurality of pixel units 690 and the circuit SD arranged in the direction indicated by the arrow C.

The pixel unit 690 includes a reflective liquid crystal element and a light-emitting element.

22B1 to 22B4 show structural examples of the electrode 611 included in the pixel unit 690. The electrode 611 is used as a reflective electrode of the liquid crystal element. An opening 451 is provided in the electrode 611 of FIGS. 22B1 and 22B2.

In Figs. 22B1 and 22B2, the light-emitting element 660 located in the area overlapping the electrode 611 is shown by a broken line. The light emitting element 660 overlaps the opening 451 included in the electrode 611. Thus, the light emitted by the light emitting element 660 is emitted to the display surface side through the opening 451.

In FIG. 22B1, adjacent pixel units 690 in the direction indicated by arrow R are pixels corresponding to different colors. At this time, as shown in FIG. 22B1, it is preferable that the openings 451 in the two pixels adjacent in the direction indicated by the arrow R are arranged at different positions of the electrode 611 so as not to be arranged in one column. As a result, the two light-emitting elements 660 can be separately arranged, so that the phenomenon (also referred to as crosstalk) that the light emitted by the light-emitting element 660 is incident on the color layer included in the adjacent pixel unit 690 can be suppressed. In addition, since two adjacent light-emitting elements 660 can be separately arranged, even if the EL layers of the light-emitting elements 660 are separately manufactured using a shadow mask or the like, a high-resolution display device can be realized.

In FIG. 22B2, adjacent pixel units 690 in the direction indicated by arrow C are pixels corresponding to different colors. The same is true in FIG. 22B2. Preferably, the openings 451 in two pixels adjacent in the direction indicated by the arrow C are provided at different positions of the electrode 611 without being provided in one column.

The smaller the ratio of the total area of the openings 451 to the total area of the non-opening portions is, the brighter the display using the liquid crystal element can be made. In addition, the larger the ratio of the total area of the opening 451 to the total area of the non-opening portion, the brighter the display using the light-emitting element 660 can be made.

The shape of the opening 451 may be, for example, a polygonal shape, a quadrangular shape, an oval shape, a circular shape, a cross shape, or the like. In addition, it may have an elongated strip shape, a slit shape, or a checkered shape. In addition, the opening 451 may be arranged close to adjacent pixels. Preferably, the opening 451 is arranged close to other pixels displaying the same color. As a result, the occurrence of crosstalk can be suppressed.

In addition, as shown in FIGS. 22B3 and 22B4, the light-emitting area of the light-emitting element 660 may also be located in a portion where the electrode 611 is not provided. As a result, the light emitted by the light-emitting element 660 is emitted to the display surface side.

In FIG. 22B3, in the two pixel units 690 adjacent in the direction indicated by the arrow R, the light-emitting elements 660 are not arranged in one column. In FIG. 22B4, in two pixels adjacent in the direction indicated by the arrow R, the light-emitting elements 660 are arranged in a row.

In the structure of FIG. 22B3, the light-emitting elements 660 included in two adjacent pixel units 690 can be arranged separately. Therefore, as described above, crosstalk can be suppressed and high resolution can be achieved. In addition, in the structure of FIG. 22B4, the electrode 611 is not located on the side of the light-emitting element 660 parallel to the arrow C. Therefore, the light emitted by the light-emitting element 660 can be suppressed from being shielded by the electrode 611, and high viewing angle characteristics can be achieved.

As the circuit GD, various sequential circuits such as a shift register can be used. As the circuit GD, a transistor, a capacitor, etc. can be used. The transistor included in the circuit GD can be formed by the same manufacturing process as the transistor included in the pixel unit 690.

The circuit SD is connected to the wiring SLa. As the circuit SD, the drive circuit 50 described in the above embodiment can be used.

For example, the circuit SD can be mounted on a pad electrically connected to the pixel unit 690 by using a COG method, a COF method, or the like. Specifically, an anisotropic conductive film can be used to mount the integrated circuit on the pad.

FIG. 23 is an example of a circuit diagram of the pixel unit 690. FIG. 23 shows two adjacent pixel units 690.

The pixel unit 690 includes a pixel 691a having a switch SW11, a capacitor C11, and a liquid crystal element 640, and a pixel 691b having a switch SW12, a transistor M, a capacitor C12, and a light-emitting element 660. The pixels 691a and 691b correspond to the pixels 31a and 31b in Figs. 1A, 1B, and 2, respectively. In addition, the wiring GLa, the wiring GLb, the wiring ANO, the wiring CSCOM, the wiring SLa, and the wiring SLb are connected to the pixel unit 690. In addition, FIG. 23 shows a wiring VCOM1 connected to the liquid crystal element 640 and a wiring VCOM2 connected to the light emitting element 660.

FIG. 23 shows an example when a transistor is used for the switch SW11 and the switch SW12.

The gate of the switch SW11 is connected to the wiring GLa. One of the source and drain of the switch SW11 is connected to the wiring SLa, and the other is connected to one electrode of the capacitor C11 and one electrode of the liquid crystal element 640. The other electrode of the capacitor C11 is connected to the wiring CSCOM. The other electrode of the liquid crystal element 640 is connected to the wiring VCOM1.

The gate of the switch SW12 is connected to the wiring GLb. One of the source and drain of the switch SW12 is connected to the wiring SLb, and the other is connected to one electrode of the capacitor C12 and the gate of the transistor M. The other electrode of the capacitor C12 is connected to one of the source and drain of the transistor M and the wiring ANO. The other of the source and drain of the transistor M is connected to one electrode of the light-emitting element 660. The other electrode of the light-emitting element 660 is connected to the wiring VCOM2.

FIG. 23 shows an example in which the transistor M includes two gate electrodes connected to each other with a semiconductor sandwiched therebetween. As a result, the amount of current that can flow through the transistor M can be increased.

A predetermined potential can be supplied to the wiring VCOM1 and the wiring CSCOM, respectively.

The wiring VCOM2 and the wiring ANO can be respectively supplied with potentials that generate a potential difference for causing the light-emitting element 660 to emit light.

The pixel unit 690 shown in FIG. 23 can be driven by signals supplied to the wiring GLa and the wiring SLa, and display using the optical modulation of the liquid crystal element 640 when displaying in the reflective mode, for example. In addition, when displaying in the transmissive mode, it is possible to drive by signals supplied to the wiring GLb and the wiring SLb, and to cause the light-emitting element 660 to emit light for display. In addition, when driving in two modes, it is possible to drive using signals supplied to the wiring GLa, the wiring GLb, the wiring SLa, and the wiring SLb, respectively.

The image signal is supplied from the line La shown in FIG. 3 to the wiring SLa, and from the line Lb shown in FIG. 3 to the wiring SLb.

In addition, as the switch SW11 and the switch SW12, it is preferable to use an OS transistor. Therefore, in the pixels 691a and 691b, the image signal can be maintained for an extremely long period of time, and the gray scale displayed in the pixels 691a and 691b can be maintained for a long period of time.

Note that although FIG. 23 shows an example in which one pixel unit 690 includes one liquid crystal element 640 and one light-emitting element 660, it is not limited to this. FIG. 24A shows an example in which one pixel unit 690 includes one liquid crystal element 640 and four light-emitting elements 660 (light-emitting elements 660r, 660g, 660b, and 660w). Unlike FIG. 23, the pixel 691b shown in FIG. 24A can use one pixel to perform full-color display using a light-emitting element.

In FIG. 24A, the wiring GLba, the wiring GLbb, the wiring SLba, and the wiring SLbb are connected to the pixel unit 690.

In the example shown in FIG. 24A, for example, as the four light-emitting elements 660, light-emitting elements each exhibiting red (R), green (G), blue (B), and white (W) can be used. In addition, as the liquid crystal element 640, a reflective liquid crystal element exhibiting white color can be used. As a result, when displaying in the reflective mode, white display with high reflectivity can be performed. In addition, when displaying in transmissive mode, high color rendering can be displayed with low power consumption.

FIG. 24B shows a structural example of the pixel unit 690 corresponding to FIG. 24A. The pixel unit 690 includes a light-emitting element 660w overlapping the opening included in the electrode 611, a light-emitting element 660r, a light-emitting element 660g, and a light-emitting element 660b arranged around the electrode 611. The light-emitting element 660r, the light-emitting element 660g, and the light-emitting element 660b preferably have almost the same light-emitting area.

When the pixel cell is connected to the wiring SLa, the wiring SLba, and the wiring SLbb, the wiring La, the line Lba, and the line Lbb are provided in the drive circuit 50 shown in FIG. 3. In addition, the image signals generated in the line La, the line Lba, and the line Lbb are supplied to the wiring SLa, the wiring SLba, and the wiring SLbb, respectively.

This embodiment mode can be combined with descriptions of other embodiments as appropriate.

Embodiment 4

In this embodiment, a configuration example of a display module using the display device described in the above embodiment will be described.

The display module 1000 shown in FIG. 25 includes a touch panel 1004 connected to the FPC 1003, a display device 1006 connected to the FPC 1005, a frame 1009, a printed circuit board 1010, and a battery 1011 between the upper cover 1001 and the lower cover 1002.

The display device described in the above embodiment can be used as the display device 1006.

The shape or size of the upper cover 1001 and the lower cover 1002 can be appropriately changed according to the size of the touch panel 1004 and the display device 1006.

As the touch panel 1004, a resistive film type touch panel or an electrostatic capacitance type touch panel superimposed on the display device 1006 can be used. In addition, the touch panel 1004 may not be provided and the display device 1006 may have the function of a touch panel.

In addition to the function of protecting the display device 1006, the frame 1009 also has an electromagnetic shielding function for blocking electromagnetic waves generated by the operation of the printed circuit board 1010. In addition, the frame 1009 may also have the function of a heat dissipation plate.

The printed circuit board 1010 includes a power supply circuit and a signal processing circuit for outputting video signals and clock signals. As a power source for supplying electric power to the power supply circuit, either an external commercial power source or a power source of a separately provided battery 1011 may be used. When a commercial power source is used, the battery 1011 can be omitted.

In addition, the display module 1000 can also be provided with components such as a polarizing plate, a phase difference plate, and a plate.

This embodiment mode can be combined with descriptions of other embodiments as appropriate.

Embodiment 5

In this embodiment mode, an example of the structure of an OS transistor that can be used in the above embodiment mode is described.

〈Example of structure of transistor〉

FIG. 26A is a plan view showing an example of the structure of a transistor. FIG. 26B is a cross-sectional view between the line X1-X2 in FIG. 26A, and FIG. 26C is a cross-sectional view between the line Y1-Y2 in FIG. 26A. Here, the direction of the X1-X2 line may be referred to as the channel length direction, and the direction of the Y1-Y2 line may be referred to as the channel width direction. FIG. 26B is a diagram showing a cross-sectional structure in the channel length direction of the transistor, and FIG. 26C is a diagram showing a cross-sectional structure in the channel width direction of the transistor. In order to clearly show the device structure, some components are omitted in FIG. 26A.

A semiconductor device according to an embodiment of the present invention includes insulating layers 812 to 820, metal oxide films 821 to 824, and conductive layers 850 to 853. The transistor 801 is formed on the insulating surface. 26A and 26B show the case where the transistor 801 is formed on the insulating layer 811. The transistor 801 is covered by the insulating layer 818 and the insulating layer 819.

The insulating layer, metal oxide film, conductive layer, etc. constituting the transistor 801 may be a single layer or a stack of multiple films. In the manufacture of these layers, sputtering method, electron beam epitaxy (MBE: Molecular Beam Epitaxy) method, pulsed laser ablation (PLD: Pulsed Laser Deposition) method, CVD method, atomic layer deposition method (ALD method) can be used. Various film forming methods. The CVD method includes a plasma CVD method, a thermal CVD method, an organic metal CVD method, and the like.

The conductive layer 850 includes a region used as a gate electrode of the transistor 801. The conductive layer 851 and the conductive layer 852 include regions used as source electrodes or drain electrodes. The conductive layer 853 includes a region used as a back gate electrode. The insulating layer 817 includes a region used as the gate insulating layer on the side of the gate electrode (front gate electrode), and the insulating layer composed of a stack of the insulating layer 814 to the insulating layer 816 includes one used as the back gate electrode. The area of the gate insulating layer on the side. The insulating layer 818 is used as an interlayer insulating layer. The insulating layer 819 is used as a barrier layer.

The metal oxide films 821 to 824 are collectively referred to as an oxide layer 830. As shown in FIGS. 26B and 26C, the oxide layer 830 includes a region where a metal oxide film 821, a metal oxide film 822, and a metal oxide film 824 are sequentially stacked. In addition, a pair of metal oxide films 823 are located on the conductive layer 851 and the conductive layer 852, respectively. When the transistor 801 is in the on state, the channel formation region of the oxide layer 830 is mainly formed in the metal oxide film 822.

The metal oxide film 824 covers the metal oxide films 821 to 823, the conductive layer 851, and the conductive layer 852. The insulating layer 817 is located between the metal oxide film 823 and the conductive layer 850. Both the conductive layer 851 and the conductive layer 852 include regions overlapping the conductive layer 850 with the metal oxide film 823, the metal oxide film 824, and the insulating layer 817 interposed therebetween.

The conductive layer 851 and the conductive layer 852 are formed by using a hard mask for forming the metal oxide film 821 and the metal oxide film 822. Therefore, the conductive layer 851 and the conductive layer 852 do not include regions in contact with the side surfaces of the metal oxide film 821 and the metal oxide film 822. For example, the metal oxide films 821, 822, the conductive layer 851, and the conductive layer 852 can be formed by the following steps: first, a conductive film is formed on the two stacked metal oxide films; the conductive film is processed into a desired Shape (etching) to form a hard mask; use the hard mask to process the shape of the two metal oxide films to form a stack of the metal oxide film 821 and the metal oxide film 822; then, the hard mask The cover is processed into a desired shape to form the conductive layer 851 and the conductive layer 852.

As the insulating material for the insulating layers 811 to 818, there are the following materials: aluminum nitride, aluminum oxide, aluminum oxynitride, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon oxynitride, silicon oxynitride , Gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, etc. The insulating layers 811 to 818 are composed of a single layer or a stacked layer including these insulating materials. The layers constituting the insulating layers 811 to 818 may include various insulating materials.

In this specification and the like, oxynitride refers to a compound whose oxygen content is greater than that of nitrogen, and nitrogen oxide refers to a compound whose nitrogen content is greater than that of oxygen.

In order to suppress the increase of oxygen defects in the oxide layer 830, the insulating layer 816 to the insulating layer 818 are preferably insulating layers containing oxygen. The insulating layer 816 to the insulating layer 818 are preferably formed using an insulating film that can release oxygen by heating (hereinafter also referred to as an "insulating film containing excessive oxygen"). By supplying oxygen from an insulating film containing excessive oxygen to the oxide layer 830, oxygen defects in the oxide layer 830 can be filled. The reliability and electrical characteristics of the transistor 801 can be improved.

The insulating layer containing excess oxygen is the release of oxygen molecules in the range of the film surface temperature of 100°C or more and 700°C or less or 100°C or more and 500°C or less when using thermal desorption spectroscopy (TDS: Thermal Desorption Spectroscopy) A film with an amount of 1.0×10 ¹⁸ [molecules/cm ^{3] or more.} The released amount of oxygen molecules is preferably 3.0×10 ²⁰ atoms/cm ³ or more.

The insulating film containing excess oxygen can be formed by performing a process of adding oxygen to the insulating film. As the oxygen addition treatment, heating treatment in an oxygen atmosphere, ion implantation method, ion doping method, plasma immersion ion implantation technology, plasma treatment, or the like can be used. As the gas for adding oxygen, oxygen gas such as ¹⁶ O ₂ or ¹⁸ O ₂ , nitrous oxide gas, ozone gas, or the like can be used.

In order to prevent the hydrogen concentration in the oxide layer 830 from increasing, it is preferable to reduce the hydrogen concentration in the insulating layers 812 to 819. In particular, it is preferable to reduce the hydrogen concentration in the insulating layers 813 to 818. Specifically, the hydrogen concentration is 2×10 ²⁰ atoms/cm ³ or less, preferably 5×10 ¹⁹ atoms/cm ³ or less, more preferably 1×10 ¹⁹ atoms/cm ³ or less, and still more preferably 5×10 19 atoms/cm 3 or less. 10 ¹⁸ atoms/cm ³ or less.

The above-mentioned hydrogen concentration is measured by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry).

In the transistor 801, the oxide layer 830 is preferably surrounded by an insulating layer (hereinafter also referred to as a barrier layer) that has barrier properties to oxygen and hydrogen. By adopting this structure, the release of oxygen from the oxide layer 830 can be suppressed, and the intrusion of hydrogen into the oxide layer 830 can be suppressed, so that the reliability and electrical characteristics of the transistor 801 can be improved.

For example, the insulating layer 819 is used as a barrier layer, and at least one of the insulating layers 811, 812, and 814 is used as a barrier layer. The barrier layer can be formed using materials such as aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, silicon nitride, and the like.

Here, a structural example of the insulating layers 811 to 818 is shown. In this example, the insulating layers 811, 812, 815, and 819 are all used as barrier layers. The insulating layers 816 to 818 are oxide layers containing excess oxygen. The insulating layer 811 is a silicon nitride layer, the insulating layer 812 is an aluminum oxide layer, and the insulating layer 813 is a silicon oxynitride layer. The insulating layers 814 to 816 used as the gate insulating layer on the back gate electrode side are a stack of silicon oxide, aluminum oxide, and silicon oxide. The insulating layer 817 used as the gate insulating layer on the front gate side is a silicon oxynitride layer. The insulating layer 818 used as an interlayer insulating layer is a silicon oxide layer. The insulating layer 819 is an aluminum oxide layer.

As the conductive material for the conductive layers 850 to 853, there are metals such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, scandium, or metal nitrides (tantalum nitride, titanium nitride , Molybdenum nitride, tungsten nitride), etc. Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon oxide added can be used. Conductive materials such as indium tin oxide.

An example of the structure of the conductive layers 850 to 853 is shown here. The conductive layer 850 is a single layer of tantalum nitride or tungsten. Alternatively, the conductive layer 850 is a stack of tantalum nitride, tantalum, and tantalum nitride. The conductive layer 851 is a single layer of tantalum nitride or a stacked layer of tantalum nitride and tungsten. The structure of the conductive layer 852 is the same as that of the conductive layer 851. The conductive layer 853a is tantalum nitride, and the conductive layer 853b is tungsten.

In order to reduce the off-state current of the transistor 801, the metal oxide film 822 preferably has a large energy gap, for example. The energy gap of the metal oxide film 822 is 2.5 eV or more and 4.2 eV or less, preferably 2.8 eV or more and 3.8 eV or less, and more preferably 3 eV or more and 3.5 eV or less.

The oxide layer 830 preferably has crystallinity. It is preferable that at least the metal oxide film 822 has crystallinity. By having the above structure, a transistor 801 with excellent reliability and electrical characteristics can be realized.

The oxide that can be used for the metal oxide film 822 is, for example, In-Ga oxide, In-Zn oxide, In-M-Zn oxide (M is Al, Ga, Y, or Sn). The metal oxide film 822 is not limited to an oxide layer containing indium. The metal oxide film 822 can be formed using, for example, Zn-Sn oxide, Ga-Sn oxide, Zn-Mg oxide, or the like. The metal oxide films 821, 823, and 824 can also be formed using the same oxide as the metal oxide film 822. In particular, the metal oxide films 821, 823, and 824 can be formed using Ga oxide, respectively.

When an interface level is formed at the interface between the metal oxide film 822 and the metal oxide film 821, since the channel formation region is also formed in the region near the interface, the threshold voltage of the transistor 801 fluctuates. Therefore, the metal oxide film 821 preferably contains at least one of the metal elements constituting the metal oxide film 822 as a component thereof. Therefore, it is not easy to form an interface energy level at the interface between the metal oxide film 822 and the metal oxide film 821, and the deviation of the electrical characteristics such as the threshold voltage of the transistor 801 can be reduced.

The metal oxide film 824 preferably contains at least one of the metal elements constituting the metal oxide film 822 as a component thereof. As a result, the interface between the metal oxide film 822 and the metal oxide film 824 is not prone to interface scattering, and it is not easy to hinder the transfer of carriers, so the field effect mobility of the transistor 801 can be improved.

Preferably, among the metal oxide films 821 to 824, the metal oxide film 822 has the highest carrier mobility. Thus, a channel can be formed in the metal oxide film 822 away from the insulating layers 816 and 817.

For example, metal oxides containing In such as In-M-Zn oxide can increase the carrier mobility by increasing the In content. In In-M-Zn oxides, the s orbitals of heavy metals mainly promote carrier conduction. By increasing the indium content, the overlap of the s orbitals can be increased. Therefore, oxides with more indium have less mobility than those with indium content. The oxide is high. Therefore, by using an oxide with a large indium content for the metal oxide film, the carrier mobility can be improved.

Therefore, for example, the metal oxide film 822 is formed using In-Ga-Zn oxide, and the metal oxide films 821, 823 are formed using Ga oxide. For example, when the metal oxide films 821 to 823 are formed using In-M-Zn oxide, the In content of the metal oxide film 822 is made higher than that of the metal oxide films 821 and 823. When the In-M-Zn oxide is formed by sputtering, the In content can be changed by changing the atomic ratio of the metal element in the target.

For example, the number of atoms of the metal element of the target used to form the metal oxide film 822 is preferably In:M:Zn=1:1:1, 3:1:2, or 4:2:4.1. For example, the number of atoms of the metal element of the target used to form the metal oxide films 821 and 823 is preferably In:M:Zn=1:3:2 or 1:3:4. The atomic ratio of the In-M-Zn oxide formed using the target material of In:M:Zn=4:2:4.1 is approximately In:M:Zn=4:2:3.

In order to impart stable electrical characteristics to the transistor 801, it is preferable to reduce the impurity concentration in the oxide layer 830. In metal oxides, hydrogen, nitrogen, carbon, silicon, and metal elements other than the main components are all impurities. For example, hydrogen and nitrogen cause the formation of donor energy levels, leading to an increase in carrier density. In addition, silicon and carbon cause the formation of impurity levels in metal oxides. The impurity level becomes a trap, sometimes deteriorating the electrical characteristics of the transistor.

For example, the oxide layer 830 has a region where the ^{silicon concentration is 2×10 18} atoms/cm ³ or less, preferably 2×10 ¹⁷ atoms/cm ^{3 or less.} The carbon concentration in the oxide layer 830 is the same.

The oxide layer 830 has a region where the alkali metal concentration is 1×10 ¹⁸ atoms/cm ³ or less, preferably 2×10 ¹⁶ atoms/cm ^{3 or less.} The alkaline earth metal concentration of the oxide layer 830 is also the same.

The oxide layer 830 has a hydrogen concentration lower than 1×10 ²⁰ atoms/cm ³ , preferably lower than 1×10 ¹⁹ atoms/cm ³ , more preferably lower than 5×10 ¹⁸ atoms/cm ³ , and more preferably The region is less than 1×10 ¹⁸ atoms/cm ^3.

The impurity concentration in the oxide layer 830 is measured by SIMS.

In the case where the metal oxide film 822 has an oxygen defect, a donor level may be formed because hydrogen enters the oxygen defect portion. As a result, it becomes a factor in the reduction of the on-state current of the transistor 801. Note that the oxygen defect is more stable when oxygen enters than when hydrogen enters. Therefore, by reducing oxygen defects in the metal oxide film 822, the on-state current of the transistor 801 can sometimes be increased. Therefore, the method of preventing hydrogen from entering the oxygen defect portion by reducing the hydrogen in the metal oxide film 822 is effective for the on-state current characteristics.

The hydrogen contained in the metal oxide reacts with the oxygen bonded to the metal atom to generate water, and therefore, oxygen vacancies are sometimes formed. When hydrogen enters the oxygen defect, electrons as carriers are sometimes generated. In addition, a part of hydrogen may be bonded to oxygen bonded to a metal atom to generate electrons as carriers. Since the channel formation region is provided in the metal oxide film 822, when the metal oxide film 822 contains hydrogen, the transistor 801 easily has a normally-on characteristic. Therefore, it is preferable to reduce the hydrogen in the metal oxide film 822 as much as possible.

26A to 26C show an example in which the oxide layer 830 has a four-layer structure, but it is not limited to this. For example, the oxide layer 830 may also have a three-layer structure without the metal oxide film 821 or the metal oxide film 823. Alternatively, one or more layers of the same as the metal oxide films 821 to 824 may be provided at any two or more positions of the oxide layer 830, above the oxide layer 830, and below the oxide layer 830. Metal oxide film.

The stacking effect of the metal oxide films 821, 822, and 824 will be described with reference to FIG. 27. FIG. 27 is a schematic diagram of the energy band structure of the channel formation region of the transistor 801.

In FIG. 27, Ec816e, Ec821e, Ec822e, Ec824e, and Ec817e represent the energy at the bottom of the conduction band of the insulating layer 816, the metal oxide film 821, the metal oxide film 822, the metal oxide film 824, and the insulating layer 817, respectively.

Here, the energy difference between the vacuum level and the energy at the bottom of the conduction band (also called "electron affinity") is the energy difference between the vacuum level and the top of the valence band (also called the free potential) minus the energy gap. The value obtained. In addition, the energy gap can be measured with a spectral ellipsometer (UT-300 manufactured by HORIBA JOBIN YVON). In addition, the energy difference between the vacuum level and the top of the valence band can be measured using an Ultraviolet Photoelectron Spectroscopy (UPS: Ultraviolet Photoelectron Spectroscopy) device (VersaProbe manufactured by PHI).

Since the insulating layers 816 and 817 are insulators, Ec816e and Ec817e are closer to the vacuum level (its electron affinity is small) than Ec821e, Ec822e, and Ec824e.

The electron affinity of the metal oxide film 822 is greater than that of the metal oxide films 821 and 824. For example, the electron affinity difference between the metal oxide film 822 and the metal oxide film 821 and the electron affinity difference between the metal oxide film 822 and the metal oxide film 824 are both 0.07 eV or more and 1.3 eV or less. The difference in electron affinity is preferably 0.1 eV or more and 0.7 eV or less, more preferably 0.15 eV or more and 0.4 eV or less. The electron affinity is the energy difference between the vacuum energy level and the bottom of the conduction band.

When a voltage is applied to the gate electrode (conductive layer 850) of the transistor 801, the channel is mainly formed in the metal oxide film 821, the metal oxide film 822, and the metal oxide film 824. The electron affinity metal oxide film 822 in.

Indium gallium oxide has a small electron affinity and high oxygen barrier properties. Therefore, the metal oxide film 824 preferably contains indium gallium oxide. The ratio of gallium atoms [Ga/(In+Ga)] is, for example, 70% or more, preferably 80% or more, and more preferably 90% or more.

There may be a mixed region of the metal oxide film 821 and the metal oxide film 822 between the metal oxide film 821 and the metal oxide film 822. In addition, there may be a mixed region of the metal oxide film 824 and the metal oxide film 822 between the metal oxide film 824 and the metal oxide film 822. The interface state density of the mixed region is low. Therefore, in the band structure of the region where the metal oxide films 821, 822, and 824 are laminated, the energy near each interface continuously changes (also referred to as continuous bonding).

In the oxide layer 830 having the above-mentioned energy band structure, electrons mainly migrate in the metal oxide film 822. Therefore, even if there are energy levels at the interface between the metal oxide film 821 and the insulating layer 812 or between the metal oxide film 824 and the insulating layer 813, these interface energy levels will not easily hinder the electrons in the oxide layer 830. Therefore, the on-state current of the transistor 801 can be increased.

In addition, as shown in FIG. 27, although trap energy due to impurities or defects may be formed near the interface between the metal oxide film 821 and the insulating layer 816 and near the interface between the metal oxide film 824 and the insulating layer 817. The levels are Et826e and Et827e, but due to the presence of the metal oxide films 821 and 824, the metal oxide film 822 can be kept away from the trap levels Et826e and Et827e.

Here, when the energy difference between Ec821e and Ec822e is small, electrons in the metal oxide film 822 may exceed the energy difference and reach the trap level Et826e. When electrons are trapped by the trap level Et826e, a fixed negative charge is generated at the interface of the insulating film, which causes the threshold voltage of the transistor to shift to the positive direction. The same is true when the energy difference between Ec822e and Ec824e is small.

In order to reduce the variation of the threshold voltage of the transistor 801 and improve the electrical characteristics of the transistor 801, the energy difference between Ec821e and Ec822e and the energy difference between Ec824e and Ec822e are preferably 0.1 eV or more, more preferably 0.15 eV or more.

Note that the transistor 801 may also have a structure that does not include a back gate electrode.

<Metal oxide>

Next, the metal oxides that can be used for the above-mentioned OS transistor will be described. Hereinafter, the details of metal oxides and CAC (Cloud-Aligned Composite) will be described in particular.

CAC-OS or CAC-metal oxide has a conductive function in a part of the material, an insulating function in another part of the material, and a semiconductor function as a whole of the material. In addition, when CAC-OS or CAC-metal oxide is used in the channel formation region of the transistor, the function of conductivity is the function of allowing electrons (or holes) used as carriers to flow, and it is insulating. The function is to prevent electrons used as carriers from flowing. By complementing the conductive function and the insulating function, CAC-OS or CAC-metal oxide can have a switching function (on/off function). By separating each function in CAC-OS or CAC-metal oxide, each function can be maximized.

In addition, CAC-OS or CAC-metal oxide includes conductive regions and insulating regions. The conductive region has the above-mentioned conductivity function, and the insulating region has the above-mentioned insulating function. In addition, in the material, the conductive region and the insulating region are sometimes separated at the nanoparticle level. In addition, the conductive region and the insulating region are sometimes unevenly distributed in the material. In addition, the conductive areas are sometimes observed to have blurred edges and connected in a cloud shape.

In CAC-OS or CAC-metal oxide, conductive regions and insulating regions may be dispersed in the material, respectively, and the size thereof is 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less.

In addition, CAC-OS or CAC-metal oxide is composed of components with different energy band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component having a wide gap due to an insulating region and a component having a narrow gap due to a conductive region. In this structure, when the carriers are caused to flow, the carriers mainly flow in a component having a narrow gap. In addition, the component having a narrow gap complements the component having a wide gap, and carriers flow in the component having a wide gap in conjunction with the component having a narrow gap. Therefore, when the above-mentioned CAC-OS or CAC-metal oxide is used in the channel formation region of the transistor, a high current driving force can be obtained in the conduction state of the transistor, that is, a large on-state current and a high field efficiency mobility.

In other words, CAC-OS or CAC-metal oxide can also be referred to as matrix composite or metal matrix composite.

CAC-OS refers to, for example, a structure in which elements contained in a metal oxide are unevenly distributed, and the size of the material containing the unevenly distributed elements is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or Approximate size. Note that in the following, the state in which one or more metal elements are unevenly distributed in the metal oxide and the region containing the metal element is mixed is called mosaic shape or patch shape, and the size of the region is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less or a size similar to it.

The metal oxide preferably contains at least indium. In particular, it is preferable to include indium and zinc. In addition, it can also contain selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten One or more of magnesium and magnesium.

For example, CAC-OS in In-Ga-Zn oxide (in CAC-OS, In-Ga-Zn oxide can be referred to as CAC-IGZO in particular) means that the material is divided into indium oxide (hereinafter referred to as InO _X1 (X1 is a real number greater than 0) or indium zinc oxide (hereinafter referred to as In _X2 Zn _Y2 O _Z2 (X2, Y2 and Z2 are real numbers greater than 0)) and gallium oxide (hereinafter referred to as GaO _X3 (X3 is a real number greater than 0)) or gallium zinc oxide (hereinafter referred to as Ga _X4 Zn _Y4 O _Z4 (X4, Y4, and Z4 are real numbers greater than 0)), etc., are mosaic-like and mosaic-like InO _X1 Or a structure in which In _X2 Zn _Y2 O _{Z2 is} uniformly distributed in the film (hereinafter, also referred to as cloud shape).

In other words, CAC-OS is a composite metal oxide having a structure in which a region mainly composed of _{GaO X3 and a region mainly composed of In X2} Zn _Y2 O _Z2 or InO _{X1 are mixed.} In this specification, for example, when the atomic ratio of In to element M in the first region is greater than the atomic ratio of In to element M in the second region, the In concentration in the first region is higher than that in the second region.

x0

1，m0為任意數)表示的結晶性化合物。 Note that IGZO is a generic term and sometimes refers to compounds containing In, Ga, Zn, and O. As a typical example, InGaO ₃ (ZnO) _m1 (m1 is a natural number) or In( ₁ + _x0 )Ga( _1-x0 )O ₃ (ZnO) _m0 (-1

x0

1, m0 is an arbitrary number) represented by the crystalline compound.

The above-mentioned crystalline compound has a single crystal structure, a polycrystalline structure or a CAAC (c-axis aligned crystal) structure. The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis alignment and are connected in a non-aligned manner on the a-b plane.

On the other hand, CAC-OS is related to the material composition of metal oxides. CAC-OS refers to the following composition: In the material composition containing In, Ga, Zn, and O, some nanoparticle-like regions with Ga as the main component are observed and some nanoparticle-like regions with In as the main component are observed. The particle-like regions are scattered irregularly in a mosaic shape, respectively. Therefore, in CAC-OS, the crystalline structure is a secondary factor.

CAC-OS does not include a laminated structure of two or more films with different compositions. For example, it does not include a two-layer structure composed of a film mainly composed of In and a film mainly composed of Ga.

Note that sometimes a clear boundary between the region _{containing GaO X3} as the main component and the region containing In _X2 Zn _Y2 O _Z2 or InO _{X1 as the main component is not observed.}

CAC-OS contains selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. When one or more types are substituted for gallium, CAC-OS refers to the following composition: a nanoparticle-like region with the element as the main component is observed in one part, and a nanoparticle-like region with In as the main component is observed in a part Scattered irregularly in a mosaic shape.

CAC-OS can be formed by using a sputtering method without intentionally heating the substrate, for example. In the case of forming CAC-OS by a sputtering method, as the deposition gas, one or more selected from an inert gas (typically argon), oxygen gas, and nitrogen gas can be used. In addition, the lower the flow rate ratio of oxygen gas in the total flow rate of the deposition gas during film formation, the better. For example, the flow rate ratio of oxygen gas is set to 0% or more and less than 30%, preferably 0% or more and 10%. %the following.

CAC-OS has the following feature: when the measurement is performed by the θ/2θ scan based on the out-of-plane method, which is one of the X-ray diffraction (XRD: X-ray diffraction) measurement methods, no clear peak is observed. That is, according to X-ray diffraction, it can be seen that there is no alignment in the a-b plane direction and the c-axis direction in the measurement area.

In addition, in the electron diffraction pattern of CAC-OS obtained by irradiating an electron beam with a beam diameter of 1 nm (also called nanobeam), a ring-shaped area with high brightness and a ring-shaped area are observed. Multiple highlights. Therefore, according to the electron diffraction pattern, it can be seen that the crystal structure of CAC-OS has an nc (nano-crystal) structure that is not aligned in the plane direction and the cross-sectional direction.

In addition, for example, in the CAC-OS of In-Ga-Zn oxide, according to the EDX surface analysis image obtained by the energy dispersive X-ray analysis method (EDX: Energy Dispersive X-ray spectroscopy), it can be confirmed that: The region where GaO _X3 is the main component and the region where In _X2 Zn _Y2 O _Z2 or InO _X1 is the main component are unevenly distributed and mixed.

The structure of CAC-OS is different from the IGZO compound in which the metal elements are uniformly distributed, and has different properties from the IGZO compound. In other words, CAC-OS has a structure _{in which a region mainly composed of GaO X3} and the like and a region mainly composed of In _X2 Zn _Y2 O _Z2 or InO _X1 are separated from each other, and the region mainly composed of each element is a mosaic configuration.

Here, _{the conductivity of the region containing In X2} Zn _Y2 O _Z2 or InO _X1 as the main component is higher than that of the region containing GaO _X3 or the like as the main component. In other words, when carriers flow through _{a region whose main component is In X2} Zn _Y2 O _Z2 or InO _X1 , the conductivity of an oxide semiconductor is exhibited. Therefore, when _{a region mainly composed of In X2} Zn _Y2 O _Z2 or InO _X1 is distributed in a cloud shape in an oxide semiconductor, a high field effect mobility (μ) can be achieved.

On the other hand, _{the insulating properties of the region containing GaO X3} or the like as the main component are higher than that of the region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as the main component. In other words, when _{a region mainly composed of GaO X3} or the like is distributed in the oxide semiconductor, leakage current can be suppressed and a good switching operation can be achieved.

Therefore, when CAC-OS is used for semiconductor devices, high on-state current (I _on ) _{can be achieved by the complementary effects of insulation due to GaO X3} etc. and conductivity due to In _X2 Zn _Y2 O _Z2 or InO _X1 And high field effect rate of movement (μ).

In addition, semiconductor elements using CAC-OS have high reliability. Therefore, CAC-OS is applicable to various semiconductor devices.

This embodiment mode can be combined with descriptions of other embodiments as appropriate.

Embodiment 6

In this embodiment, a configuration example of a display system using the drive circuit or display device described in the above embodiment will be described.

FIG. 28 shows an example of the structure of the display system 900. As shown in FIG. The display system 900 includes a display unit 910 and a control unit 920.

The control unit 920 has a function of generating a video signal based on data corresponding to the video displayed on the display unit 910 (hereinafter also referred to as video data). The control unit 920 includes an interface 921, a frame memory 922, a decoder 923, a sensing controller 924, a controller 925, a clock generation circuit 926, an image processing unit 930, a memory device 941, a timing controller 942, and temporary storage 943, drive circuit 950, and touch sensor controller 961.

The display unit 910 has a function of displaying images on the display units 911a and 911b using the image signal input from the control unit 920. In addition, the display unit 910 may also include a touch sensor unit 912 having a function of obtaining information such as presence or absence of a touch, a touch position, and the like. In the case where the display part 910 does not include the touch sensor unit 912, the touch sensor controller 961 may be omitted.

As the display units 911a and 911b, a display unit that uses liquid crystal elements for display, a display unit that uses light-emitting elements for display, or the like can be used. Here, as an example, a structure in which the display unit 910 includes a display unit 911a for displaying using a reflective liquid crystal element and a display unit 911b for displaying using a light-emitting element will be described. The display units 911a and 911b respectively correspond to the unit composed of the pixel group 30a and the driving circuit 40a in FIGS. 1A and 1B, and the unit composed of the pixel group 30b and the driving circuit 40b.

The driving circuit 950 has a function of supplying an image signal to the display unit 910. As the driving circuit 950, the driving circuit 50 in FIGS. 1A and 1B can be used. In this case, the driving circuit 950 has a function of supplying image signals to the display unit 911a and the display unit 911b, respectively.

The host 970 corresponds to a processor or the like having a function of sending video data and the like to the control unit 920. The communication between the control unit 920 and the host 970 is performed through the interface 921. Video data, various control signals, etc. are sent from the host 970 to the control unit 920. In addition, information such as the presence or absence of the touch and the touch position obtained by the touch sensor controller 961 is sent from the control unit 920 to the host 970. Note that the various circuits included in the control unit 920 can be appropriately selected according to the specifications of the host 970 and the display unit 910 and the like.

The frame memory 922 has a function of storing image data input to the control unit 920. When the compressed video data is sent from the host 970 to the control unit 920, the frame memory 922 can store the compressed video data. The decoder 923 is a circuit for expanding the compressed video data. If there is no need to expand the video data, the decoder 923 does not need to perform processing. In addition, the decoder 923 can also be disposed between the frame memory 922 and the interface 921.

The image processing unit 930 has a function of performing various image processing on the image data input from the frame memory 922 or the decoder 923 to generate an image signal. For example, the image processing unit 930 includes a gamma correction circuit 931, a dimming circuit 932, and a color adjustment circuit 933.

In addition, when the drive circuit 950 includes a circuit (current detection circuit) that detects the current flowing through the light-emitting element included in the display unit 911 b, the EL correction circuit 934 may be provided in the image processing unit 930. The EL correction circuit 934 has a function of adjusting the brightness of the light emitting element based on the signal sent from the current detection circuit.

The image signal generated in the image processing unit 930 is output to the driving circuit 950 through the memory device 941. The memory device 941 has a function of temporarily storing image signals. The driving circuit 950 has a function of performing various processing on the video signal input from the memory device 941 and outputting it to the display units 911a and 911b.

The timing controller 942 has a function of generating timing signals used in the driving circuit 950, the touch sensor controller 961, the driving circuit included in the display unit 911, and the like.

The touch sensor controller 961 has a function of controlling the operation of the touch sensor unit 912. The signal including the touch information detected in the touch sensor unit 912 is processed by the touch sensor controller 961 and then sent to the host 970 through the interface 921. The host 970 generates image data reflecting the touch information and sends it to the control unit 920. In addition, the control unit 920 may also have a function of reflecting the touch information in the image data. In addition, the touch sensor controller 961 may also be provided in the touch sensor unit 912.

The clock generation circuit 926 has a function of generating a clock signal used in the control unit 920. The controller 925 has a function of processing various control signals sent from the host 970 through the interface 921 and controlling various circuits in the control unit 920. In addition, the controller 925 has a function of controlling power supply to various circuits in the control unit 920. For example, the controller 925 can temporarily interrupt the power supply to the circuit in the stopped state.

The register 943 has a function of storing data used for the operation of the control unit 920. As the data stored in the register 943, parameters used in the correction processing of the image processing unit 930, parameters used in the waveform generation of various timing signals of the timing controller 942, and the like can be cited. The register 943 can be composed of a scanner chain register including a plurality of registers.

In addition, a sensing controller 924 connected to the light sensor 980 may be provided in the control part 920. The light sensor 980 has a function of detecting external light 981 to generate a detection signal. The sensing controller 924 has a function of generating a control signal based on the detection signal. The control signal generated by the sensing controller 924 is output to the controller 925, for example.

When the display unit 911a and the display unit 911b display the same video, the video processing unit 930 has a function of generating the video signal of the display unit 911a and the video signal of the display unit 911b, respectively. In this case, the reflection intensity of the reflective liquid crystal element included in the display unit 911a and the light-emitting element included in the display unit 911b can be adjusted according to the brightness of the external light 981 measured using the light sensor 980 and the sensing controller 924. light intensity. Here, this adjustment is referred to as dimming or dimming processing. In addition, the circuit that performs this processing is called a dimming circuit.

The image processing unit 930 may also include other processing circuits such as an RGB-RGBW conversion circuit according to the specifications of the display unit 910. The RGB-RGBW conversion circuit refers to a circuit that has the function of converting RGB (red, green, blue) image data into RGBW (red, green, blue, white) image signals. That is, when the display unit 910 includes pixels of 4 colors of RGBW, by using W (white) pixels to display the W (white) component in the image data, power consumption can be reduced. Note that the RGB-RGBW conversion circuit is not limited to this, and for example, an RGB-RGBY (red, green, blue, yellow) conversion circuit or the like may also be used.

By using the drive circuit 50 described in the above-mentioned embodiment as the drive circuit 950, it is possible to reduce the power consumption and the area of the control section 920.

Embodiment 7

In this embodiment, a configuration example of an electronic device in which the display device or the display system described in the above embodiment is installed will be described.

The display device and display system of one embodiment of the present invention can achieve high visibility regardless of the intensity of external light. Therefore, it can be suitably applied to portable electronic devices, wearable electronic devices, e-book readers, and the like. 29A to 29D show examples of electronic devices using the display device of one embodiment of the present invention.

29A and 29B show an example of a portable information terminal 2000. The portable information terminal 2000 includes a housing 2001, a housing 2002, a display section 2003, a display section 2004, a hinge section 2005, and the like.

The housing 2001 and the housing 2002 are connected together by a hinge portion 2005. The portable information terminal 2000 can be converted from the folded state shown in FIG. 29A to the unfolded state of the housing 2001 and the housing 2002 shown in FIG. 29B.

For example, document information can be displayed on the display unit 2003 and the display unit 2004, and can be used as an e-book reader. In addition, still images or moving images may be displayed on the display unit 2003 and the display unit 2004. In addition, the display unit 2003 may include a touch panel.

In this way, the portable information terminal 2000 can be folded when it is carried, so the versatility is superior.

In addition, the housing 2001 and the housing 2002 may also include a power button, an operation button, an external connection port, a speaker, a microphone, and the like.

In addition, the portable information terminal 2000 may also have the function of using the touch sensor provided in the display unit 2003 to recognize text, graphics, and images. In this case, for example, the following learning can be performed: using a finger, a stylus, or the like, write answers to an information terminal displaying a set of questions for learning mathematics, language, etc., and the portable information terminal 2000 determines whether it is right or wrong. In addition, the portable information terminal 2000 may also have a voice interpretation function. In this case, for example, the portable information terminal 2000 can be used to learn foreign languages and the like. The aforementioned portable information terminal is suitable for use in textbooks such as textbooks or notebooks.

In addition, the touch information obtained by the touch sensor provided in the display unit 2003 can be used when the semiconductor device according to an embodiment of the present invention predicts the presence or absence of power supply.

Fig. 29C shows an example of a portable information terminal. The portable information terminal 2010 shown in FIG. 29C includes a housing 2011, a display portion 2012, operation buttons 2013, an external connection port 2014, a speaker 2015, a microphone 2016, a camera 2017, and the like.

In the portable information terminal 2010, a touch sensor is provided in the display portion 2012. Various operations such as making a call or inputting characters can be performed by touching the display section 2012 with a finger or a stylus pen.

In addition, by operating the operation button 2013, it is possible to turn on and off the power, or to switch the type of image displayed on the display section 2012. For example, you can switch the email composing screen to the main menu screen.

In addition, by installing detection devices such as a gyroscope sensor or an acceleration sensor inside the portable information terminal 2010, the orientation (vertical or horizontal) of the portable information terminal 2010 can be determined, and the screen of the display unit 2012 The display direction is automatically switched. In addition, the switching of the screen display can also be performed by touching the display portion 2012, operating the operation buttons 2013, or inputting a voice using the microphone 2016.

The portable information terminal 2010 has, for example, one or more functions selected from among telephones, notebooks, and information reading devices. For example, the portable information terminal 2010 can be used as a smart phone. In addition, the portable information terminal 2010 can execute various applications such as mobile phones, e-mails, article reading and editing, music playback, animation playback, network communications, computer games, and so on.

Fig. 29D shows an example of a camera. The camera 2020 includes a housing 2021, a display portion 2022, an operation button 2023, a shutter button 2024, and the like. In addition, the camera 2020 is equipped with a removable lens 2026.

Here, although the camera 2020 has a structure in which the lens 2026 can be detached from the housing 2021 and exchanged, the lens 2026 and the housing 2021 may be formed as one body.

By pressing the shutter button 2024, the camera 2020 can shoot still images or moving images. In addition, the display unit 2022 may have the function of a touch panel, and the display unit 2022 can be touched to perform imaging.

In addition, the camera 2020 may also include a flash device, a viewfinder, and the like that are additionally installed. In addition, these components may also be assembled in the housing 2021.

As the display unit of the electronic device shown in FIGS. 29A to 29D, the display device described in the above embodiment can be used. In addition, the display system shown in FIG. 28 may be installed in the electronic device shown in FIGS. 29A to 29D. In this case, the display unit 910 shown in FIG. 28 can be used as the display unit of the electronic device. In addition, an integrated circuit used as the control section 920 and a processor used as the host 970 can be installed in the electronic device.

This embodiment mode can be combined with descriptions of other embodiments as appropriate.

10‧‧‧Display device

20‧‧‧Pixel

21‧‧‧Pixel unit

30a‧‧‧Pixel Group

30b‧‧‧Pixel Group

31a‧‧‧pixel

31b‧‧‧pixel

40‧‧‧Drive circuit

50‧‧‧Drive circuit

Claims (6)

A driving circuit includes: a shift register; a decoding circuit; a level shifter circuit; a DA conversion circuit; and an amplifier circuit, wherein the shift register includes a first circuit and a second circuit, and the decoding circuit includes The third circuit and the fourth circuit, the level shifter circuit includes a fifth circuit and a sixth circuit, the DA conversion circuit includes a seventh circuit and an eighth circuit, the amplifying circuit includes a ninth circuit and a tenth circuit, the first The ninth circuit is electrically connected to the first wiring, the tenth circuit is electrically connected to the second wiring, the first circuit, the third circuit, the fifth circuit, the seventh circuit, and the ninth circuit constitute a first line, the The second circuit, the fourth circuit, the sixth circuit, the eighth circuit, and the tenth circuit constitute a second line. The first line has a function of generating a first image signal supplied to the first wiring. The second line has the function of generating a second image signal supplied to the second wiring. During the period when the first image signal is not generated, the power supply to the circuit constituting the first line is stopped, and the second image signal is not generated. During this period, the power supply to the circuit constituting the second line is stopped. According to the first driving circuit of the scope of patent application, the first circuit and the second circuit include flip-flops, the third circuit and the fourth circuit include decoders, and the fifth circuit and the sixth circuit include bits Quasi-transferr, The seventh circuit and the eighth circuit include selection circuits, and the ninth circuit and the tenth circuit include amplifiers. The driving circuit according to item 2 of the scope of patent application, wherein the first circuit and the second circuit include a first switch and a second switch, the first terminal of the first switch is electrically connected to the flip-flop, and the first switch The second terminal of the second switch is electrically connected to the wiring supplied with the power supply potential, the first terminal of the second switch is electrically connected to the input terminal of the flip-flop, and the second terminal of the second switch is electrically connected to the output terminal of the flip-flop Connected, and the second switch has a function of becoming an on state while the first switch is in the off state. The driving circuit according to the first item of the scope of patent application, wherein the DA conversion circuit includes a first electric potential generating circuit and a second electric potential generating circuit, the first electric potential generating circuit has a function of supplying a first reference electric potential to the seventh circuit, the The second potential generation circuit has the function of supplying a second reference potential to the eighth circuit, and stops the supply of the first reference potential during the period when the first image signal is not being generated, and stops during the period when the second image signal is not being generated. The supply of the second reference potential. A display device includes: the driving circuit of the first item of the scope of patent application; and a pixel portion, wherein the pixel portion includes a first pixel and a second pixel, the first pixel includes a reflective liquid crystal element, and the second pixel includes a light emitting And the driving circuit has a function of supplying the first image signal to the first pixel and a function of supplying the second image signal to the second pixel. An electronic device including a display system, the display system including: a control unit including the driving circuit of the first item in the scope of the patent application; A display portion; and a processor, wherein the display portion includes a first display unit, a second display unit, and a touch sensor unit, the first display unit includes a first pixel having a reflective liquid crystal element, and the second display The unit includes a second pixel with a light-emitting element, the processor has a function of sending image data to the control unit, and the control unit has a function of generating the first image signal and the second image signal according to the image data, and The driving circuit supplies the first image signal to the first display unit and supplies the second image signal to the second display unit.

Images