TWI605717B - Display control apparatus and corresponding method - Google Patents

Description

Display control device and corresponding display control method

The present invention relates to the field of display, and in particular to a display control device capable of displaying high-resolution images and a corresponding display control method.

With the rapid development of electronic products, consumers have higher and higher requirements for the resolution of display panels in electronic products, and high-resolution display panels have become the mainstream of display devices. At present, 4K display technology has become the mainstream of display devices. However, in fact, 8K display technology has also been developed and designed.

Among them, the hardware platforms of most current display control devices are based on 4K display technology, that is, the hardware platform of most display control devices can only support 4K (3840*2160) and below resolution images, and cannot Supports 8K (7680*4320) resolution images. That is to say, although a display panel having an 8K resolution has been developed and developed, it has greatly limited the development of the 8K display technology due to limitations of other hardware devices.

Among these constraints, data transmission is a critical limiting factor. In fact, the data processing capability of the current processor is extremely powerful. However, since the data transmission bus can only support the transmission of 4K images at present, it limits the processing and display of 4K images to the maximum supported by the entire hardware platform. This greatly limits the development of 8K display technology.

In view of this, it is necessary to design and develop a new display control device and corresponding image display control method to overcome the above drawbacks.

The technical problem to be solved by the present invention is to provide a display control device and a display control method capable of displaying a high-resolution image using a limited hardware platform.

In order to solve the above technical problem, a technical solution adopted by the present invention is to provide a display control device for controlling a display panel having a first resolution, the display control device being connected to the display panel through a data transmission bus bar, The method includes a processor for controlling reading an image from a memory for storage to a memory, wherein the image has a first resolution, and a signal generating circuit is controlled by the processor to respectively Generating a synchronization signal, a clock signal, and a control timing signal, wherein the clock signal is synchronized with the synchronization signal; and an image processing circuit controlled by the processor to read the image from the memory and read the image The image is cut into a plurality of images having a second resolution; and the plurality of images having the second resolution are sequentially transmitted to the display panel via the data transmission bus according to the clock signal and the synchronization signal to be displayed on the display panel. The image with the first resolution is displayed on the panel, wherein the control timing signal is combined with the plurality of second resolutions The image is transmitted to the display panel for indicating the sequence of the plurality of images having the second resolution; the first resolution is greater than the second resolution, and the second resolution is not greater than the image display control device And the maximum resolution supported by the data transfer bus.

In order to solve the above technical problem, another technical solution adopted by the present invention is: a display control method applied to a display control device for controlling a display panel having a first resolution, the display control device transmitting a bus through a data transmission Connecting to the display panel, comprising: reading an image to a memory, wherein the image has a first resolution; respectively generating a synchronization signal, a clock signal and a control timing signal, wherein the clock signal and Synchronizing the synchronization signal; reading the image from the memory and cutting the read image into a plurality of images having the second resolution; and sequentially transmitting the image according to the clock signal and the synchronization signal via the data transmission bus a plurality of images having a second resolution to the display panel to display the image having the first resolution on the display panel; wherein the control timing signal is transmitted to the plurality of images having the second resolution to The display panel is configured to indicate an order of the plurality of images having the second resolution; the first resolution is large And the second resolution is not greater than a maximum resolution supported by the data transmission bus.

An advantage of the present invention is that the display control device and the display control method of the present invention convert a high-resolution image into a plurality of low-resolution images for data transmission, and then display the data in a different manner from the prior art. In the display panel, it greatly reduces the requirements for the hardware platform, can display high-quality images on the low-profile hardware platform, and the cost is reduced, and greatly expands the application range of the existing hardware platform.

Specific details are set forth in the description which follows to best understand the invention. However, the present invention can be implemented in various other ways than those described herein, and those skilled in the art can make similar promotion without departing from the scope of the present invention. The invention is therefore not limited by the specific embodiments disclosed below.

The present invention provides a new display control device and display control method for the defects mentioned in the background art. The invention will be further described in detail below with reference to the drawings and embodiments.

Please refer to FIG. 1 , which is a schematic diagram of a display control device controlling a display panel according to an embodiment of the invention. As shown in FIG. 1 , the display device 100 of the embodiment of the present invention includes a display control device 110 and a display panel 150 having a first resolution, wherein the display control device 110 and the display panel 150 pass through the data transmission bus bar 130. connection. The display device 100 further includes a memory 170 and a memory 190, and the memory 170 and the memory 190 may be disposed inside or outside the display control device 110. It will be understood by those skilled in the art that the memory 170 and the memory 190 shown in FIG. 1 are disposed outside the display control device 110 for illustrative purposes only and are not to be construed as limiting the scope of the present invention. Specifically, the display control device 110 includes a processor 120, a signal generating circuit 140, and an image processing circuit 160.

The processor 120 is configured to control reading an image from the memory 170 for storage to the memory 190, wherein the image has a first resolution. The signal generating circuit 140 is controlled by the processor 120 to generate a synchronization signal, a clock signal and a control timing signal, wherein the clock signal is synchronized with the synchronization signal. The image processing circuit 160 is controlled by the processor 120 to read the image from the memory 190 and cut the read image into a plurality of images having a second resolution, and according to the clock signal and the The synchronization signal sequentially transmits the plurality of images having the second resolution to the display panel 150 via the data transmission bus to display the image with the first resolution on the display panel 150. The control timing signal is transmitted to the display panel 150 along with the plurality of images having the second resolution for indicating the sequence of the plurality of images having the second resolution.

The first resolution is greater than the second resolution, and the second resolution is not greater than the maximum resolution supported by the data transmission bus 130. In this embodiment, the second resolution is lower than the first resolution by one level, for example, the first resolution is 7680*4320, and the second resolution is 3840*2160, and the display control device 110 and the data transmission bus 130 are The maximum resolution that can be supported is also 3840*2160. That is to say, the image with the first resolution is 8K image, and the image with the second resolution is 4K image, and the display control device 110 and the first data transmission bus 130 can only support the transmission of 4K images.

Therefore, in the present invention, in order to be able to display 8K images on the display panel 150, the display control device 110 cuts the 8K images into a plurality of 4K images (four 4K images), and sequentially transfers the 4K images to the display panel 150. Thus, a corresponding 8K image is displayed on the display panel 150. In the embodiment of the present invention, the image with the first resolution (8K image) may be a static image. Of course, it may also be a dynamic video stream.

In this embodiment, the display control device 110 includes a processor 120, a signal generating circuit 140, and an image processing circuit 160. The processor 120 is connected to the signal generating circuit 140 and the image processing circuit 160, respectively, and controls the signal generating circuit 140 and The image processing circuit 160 performs various operations. In addition, the processor 120 can further connect the memory 170 and the memory 190. The memory 190 can be a DRAM memory, and the memory 170 can be a Flash memory.

Please refer to FIG. 2 , wherein FIG. 2 is a schematic diagram of the display control device cutting the image having the first resolution into a plurality of images having the second resolution according to the embodiment of the present invention. Referring to FIGS. 1 and 2 together, the processor 120 loads and decodes the image 210 (8K image) having the first resolution in the memory 170, and stores the image 210 in the specified address of the memory 190. The image processing circuit 160 reads the image from the memory 190. Specifically, the image processing circuit 160 acquires information such as a memory address, a width, a height, and an image type of the image 210 having the first resolution.

Then, the image processing circuit 160 cuts the image 210 (8K image) having the first resolution into a plurality of images 220 (4K images) having the second resolution according to the information acquired above. In this embodiment, the 8K (7680*4320) image 210 is cut into four 4K (3840*2160) images 220 of the same size, which correspond to the upper left portion, the upper right portion, the lower left portion, and the lower right of the 8K image, respectively. section.

After the cutting is completed, the image processing circuit 160 further calculates the starting address of each image 220 having the second resolution in the memory 1113. In this embodiment, the starting addresses of the four 4K images 220 are respectively For address 0 (addrshift0), address 1 (addrshift1), address 2 (addrshift2), and address 3 (addrshift3), the calculation formulas are:

Addrshift0 = ;

Addrshift1 = ;

Addrshift2 = ;

Addrshif3 = ;

among them, To have an 8K image 210 at the start address of the memory 1113; Is to have a width of 8K image 210; Is the height of the 8K image 210; Depending on the color format of the 8K image 210, for example, when the color format of the 8K image 210 is ARGB4444, then The value is 2; when the color format of the 8K image 210 is ARGB8888, then The value is 4.

Then, the image processing circuit 160 sequentially transmits the cut image 220 having the second resolution to the display panel 150 through the data transmission bus 130.

Please refer to FIG. 3, which is a timing diagram of the display control device according to an embodiment of the present invention. The signal generating circuit 140 further includes a synchronous signal generator, a clock signal generator and a control timing signal generator for respectively generating the synchronous signal, the clock signal and the control timing signal. This clock signal is synchronized with the sync signal. In this embodiment, the clock signal is synchronized with the sync signal, meaning that its rising edge and falling edge are respectively aligned with the rising edge of the pulse of the sync signal. For example, when the synchronization signal is 50 Hz, the clock signal is also 50 Hz, and the rising edge and the falling edge of the clock signal are respectively aligned with the rising edge of the pulse of the synchronous signal. The control timing signal is that the plurality of images having the second resolution are transmitted to the display panel 150. The control timing signal includes a first control signal and a plurality of second control signals in a cycle, the first control signal is opposite to the second control signal, and the first control signal control display panel 150 displays the plurality of second resolutions. The first image in the image 220, and the second control signal control display panel 150 displays a plurality of other images in the image 220 having the second resolution.

In this embodiment, the first control signal is a logic high level "1" and the second control signal is a logic low level "0". Of course, those skilled in the art can understand that the first control signal can also be set to a logic low level "0" and the second control signal can be set to a logic high level "1". In this embodiment, the control timing signal includes a logic high level "1" and three logic low levels in one cycle. "0".

When the control timing signal is logic high level "1", the first 4K image is displayed in the upper left corner of the display panel 120; then, the control signal GPIO is three logic low levels "0", which are respectively in the upper right side thereof. The second 4K image is displayed in the corner, the third 4K image is displayed in the lower left corner, and the fourth 4K image is displayed in the lower right corner.

In other words, the plurality of images having the second resolution are sequentially buffered and stored according to the starting address, and when the plurality of images having the second resolution are stored, the plurality of images having the second resolution are read. And recovering the plurality of images into the original image having the first resolution according to the starting address of each image. For example, after receiving four 4K images in the time corresponding to four sync signals, the four 4K images will be restored to the original 8K images, and the user will see a complete 8K image on the display panel 150.

Specifically, the display panel 150 further includes a timing control circuit, configured to receive the plurality of images having the second resolution, and convert the image into an image according to the image having the first resolution recovered by the control timing signal. Data and drive signals are used to drive control to display a complete 8K image on the display panel 150.

Please refer to FIG. 4, which is a schematic diagram of a timing control circuit 400 according to an embodiment of the present invention. In an embodiment, the timing control circuit 400 includes a processor 401, a buffer 402, and a memory 403. The processor 401 is connected to the buffer 402 and the memory 403, respectively. When the timing control circuit receives the plurality of images having the second resolution, the processor 401 controls the plurality of images with the second resolution to be sequentially buffered to the buffer 402 according to the start address according to the control timing signal, and the four images are stored. When the image has the second resolution, the processor 401 reads the four images with the second resolution, and restores the four images into one image according to the start address of each image, and stores the image in the memory 403. . Calculating the width, height and image format of each image according to the starting address is exactly the opposite of the above cutting method, and will not be described here. It should be noted that those skilled in the art can understand that the buffer 402 and the memory 403 can be disposed in the timing control circuit 400 or can be disposed outside the timing control circuit. FIG. 4 is merely illustrative and cannot be It is considered to limit the scope of protection of the present invention.

Those skilled in the art can understand that the processors 120 and 401 in the present invention can adopt the popular processing devices in the market, and the current mainstream processing devices in the market have extremely powerful data processing. Therefore, the processor 120 has completely Ability to process 8K images. The limitation of the 8K technology is mainly the lack of data transmission capability. That is, in this embodiment, the data transmission capability of the data transmission bus 130 is mainly capable of transmitting 4K images but not 8K images. That is to say, the maximum resolution that the display device 100 can support is mainly determined by the maximum resolution that the data transmission bus 130 can support.

Therefore, although the data transmission capability of the data transmission bus 130 is poor, it can only transmit 4K images. However, the display device 100 of the embodiment of the present invention cuts the 4K images into a plurality of 4K images and sequentially transmits the 4K images. It can still display 8K images on the display panel 150.

Of course, those skilled in the art can understand that the present invention is not limited to dividing 8K images into four 4K images, and can also cut 8K images into 16 2K (1960*1080) images or 64 1K (980). *540) Image, and so on. Alternatively, when the data transmission bus 130 can only support images with a maximum resolution of 1960*1080, when the display device 100 needs to display 4K images, the 4K images can be cut into four 2K images. Alternatively, when the data transmission technology is greatly developed, the data transmission bus can transmit 8K images, and when the display device 100 needs to display 16K images, the 16K images can be cut into 4 8K images correspondingly.

Further, in the above description, the 8K image is cut into four 4K images which are sequentially transmitted in the order of the upper left portion, the upper right portion, the lower left portion, and the lower right portion, and are simultaneously displayed in the upper left area of the display panel 120, Upper right area, lower left area, and lower right area. However, it will be understood by those skilled in the art that they can also be sequentially transmitted and displayed simultaneously in other orders, for example, an upper left portion, a lower left portion, an upper right portion, and a lower right portion, and the like.

In addition, the present invention also provides a display control method for a display control device for controlling a display panel having a first resolution, the display device being connected to the display panel through a data transmission bus. Please refer to FIG. 5, which is a flowchart of a display control method according to an embodiment of the present invention. As shown in FIG. 5, the display control method of the embodiment of the present invention includes:

Step 510: Read an image to a memory, where the image has a first resolution;

Step 520: respectively generate a synchronization signal, a clock signal and a control timing signal, wherein the clock signal is synchronized with the synchronization signal;

Step 530: Read the image from the memory and cut the read image into a plurality of images having the second resolution;

Step 540: sequentially transmit the plurality of images having the second resolution to the display panel via the data transmission bus according to the clock signal and the synchronization signal, to display the image with the first resolution on the display panel;

The control timing signal is transmitted to the display panel along with the plurality of images having the second resolution to indicate the sequence of the plurality of images having the second resolution; wherein the first resolution is greater than the The second resolution is not greater than the maximum resolution supported by the data transmission bus.

Specifically, in the image cutting method in step 530, referring to the embodiment of the cutting method in FIG. 2, the image having the first resolution is stored to a specified address of the memory, and the memory bit of the image having the first resolution is acquired. Information such as address, width, height, and image type, and the image having the first resolution is cut into a plurality of images having the second resolution according to the acquired information. In one embodiment, the 8K (7680*4320) image 210 is cut into four 4K (3840*2160) images 220 of the same size, which correspond to the upper left portion, the upper right portion, the lower left portion, and the lower right of the 8K image, respectively. section. After the cutting is completed, the starting address of each image having the second resolution is further calculated. The second resolution is one level lower than the first resolution, and the image is cut into four images of the second resolution at the start address of the memory:

Addrshift0 = ;

Addrshift1 = ;

Addrshift2 = ;

Addrshif3 = ;

among them, The image having the first resolution is at a start address of the memory; The width of the image having the first resolution; The height of the image having the first resolution; Depending on the color format of the image with the first resolution.

For the timing diagram of each signal in step 520, please refer to FIG. 3, and details are not described herein again. For example, the clock signal is synchronized with the sync signal, and its rising edge and falling edge are respectively aligned with the rising edge of the pulse of the synchronous signal. For example, when the synchronization signal is 50 Hz, the clock signal is also 50 Hz, and the rising edge and the falling edge of the clock signal are respectively aligned with the rising edge of the pulse of the synchronous signal. The control timing signal includes a first control signal and a plurality of second control signals in one cycle, the first control signal is opposite to the second control signal, and the first control signal is controlled to transmit a plurality of images having the second resolution. The first image, and the second control signal controls the transmission of a plurality of other images in the second resolution image.

The plurality of images having the second resolution are sequentially cached according to the start address, and when the plurality of images having the second resolution are stored, the plurality of images having the second resolution are read, and each image is The start address of the image restores the plurality of images to an image. Calculating the width, height and image format of each image according to the starting address is exactly the opposite of the above cutting method, and will not be described here.

In summary, the display device and the image display method of the present invention greatly reduce the image by cutting the high-resolution image into a plurality of low-resolution images for data transmission and then displaying it in the display panel. The requirements for hardware platforms enable high-quality images to be displayed on low-profile hardware platforms, which reduces costs and greatly expands the range of applications for existing hardware platforms. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100‧‧‧ display device
110‧‧‧Display control device
120, 401‧‧‧ processor
130‧‧‧Data transmission bus
140‧‧‧Signal generation circuit
150‧‧‧ display panel
160‧‧‧Image Processing Circuit
170, 190, 403‧‧‧ memory
210‧‧8K image
220‧‧‧4K image
400‧‧‧Sequence Control Circuit
402‧‧‧buffer

FIG. 1 is a schematic diagram of a display control device controlling a display panel according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a display device according to an embodiment of the present invention cutting an image having a first resolution into a plurality of images having a second resolution. Fig. 3 is a timing chart of the display control device according to the embodiment of the present invention. Figure 4 is a schematic diagram of a timing control circuit in accordance with an embodiment of the present invention. FIG. 5 is a flowchart of a display control method according to an embodiment of the present invention.

100‧‧‧ display device

110‧‧‧Display control device

120‧‧‧ processor

130‧‧‧Data transmission bus

140‧‧‧Signal generation circuit

150‧‧‧ display panel

160‧‧‧Image Processing Circuit

170, 190‧‧‧ memory

Claims (17)

A display control device for controlling a display panel having a first resolution, the display control device being connected to the display panel via a data transmission bus, the display control device comprising: a processor for controlling one The first memory reads an image for storage to a second memory, wherein the image has the first resolution; a signal generating circuit is controlled by the processor to generate a synchronization signal, a clock signal, and a control timing signal, wherein the clock signal is synchronized with the synchronization signal; and an image processing circuit controlled by the processor to read the image from the second memory and cut the read image into a plurality An image having a second resolution; and sequentially transmitting the image having the second resolution to the display panel via the data transmission bus according to the clock signal and the synchronization signal to display on the display panel The first resolution image; wherein the control timing signal is transmitted to the display panel together with the images having the second resolution. The order of indicating the images having the second resolution; the first resolution is greater than the second resolution, and the second resolution is not greater than a maximum resolution supported by the data transmission bus. The display control device of claim 1, wherein the image processing circuit reads the image from a specified address of the second memory, and obtains an address of the image in the second memory, Information such as width, height, and image type, and cutting the image having the first resolution into the images having the second resolution according to the acquired information. The display control device of claim 1, wherein the signal generating circuit further comprises: a synchronous signal generator for generating the synchronous signal; and a clock signal generator coupled to the synchronous signal generator, For generating the clock signal; and a control timing signal generator for generating the control timing signal. The display control device of claim 1, wherein the synchronization of the clock signal with the synchronization signal means that a rising edge and a falling edge of the clock signal are respectively aligned with rising edges of the two pulses of the synchronization signal. The display control device according to claim 1, wherein the image processing circuit cuts the image having the first resolution into the images having the second resolution, and calculates that each of the images has the first The image of the second resolution is at a start address of the second memory. The display control device of claim 5, wherein the second resolution is one level lower than the first resolution, and the image processing circuit cuts the image having the first resolution into four The second resolution image. The display control device of claim 6, wherein the four images having the second resolution are respectively in the start address of the second memory: addrshift0 = ; addrshift1 = ; addrshift2 = ; addrshif3 = Where a start address of the second memory in the image having the first resolution; a width of the image having the first resolution; a height of the image having the first resolution; Depending on a color format of the image having the first resolution. The display control device of claim 1, wherein the control timing signal includes a first control signal and a plurality of second control signals in a cycle, the first control signal being opposite to the second control signal, And the first control signal controls the display panel to display the first image of the images having the second resolution, and the second control signal controls the display panel to display the images having the second resolution. Other images. The display control device of claim 1, wherein the image having the first resolution is an 8K image (7680*4320), and the images having the second resolution are 4K images (3840). *2160). A display control method is applied to a display control device for controlling a display panel having a first resolution, the display control device being connected to the display panel through a data transmission bus bar, the display control method comprising: reading one The image is to a memory, wherein the image has the first resolution; respectively generating a synchronization signal, a clock signal and a control timing signal, wherein the clock signal is synchronized with the synchronization signal; reading the image from the memory and Cutting the read image into a plurality of images having a second resolution; and sequentially transmitting the images having the second resolution to the display panel via the data transmission bus according to the clock signal and the synchronization signal And displaying the image having the first resolution on the display panel; wherein the control timing signal is transmitted to the display panel together with the images having the second resolution, to indicate that the a sequence of two resolution images; the first resolution is greater than the second resolution, and the second resolution is no greater than the data Output bus a maximum resolution supported by the. The display control method of claim 10, wherein the step of cutting the read image into the image having the second resolution comprises: acquiring a memory address, a width, and a Information such as height and image type, and the image having the first resolution is cut into the images having the second resolution according to the obtained information. The display control method of claim 10, further comprising: after cutting the read image into the images having the second resolution, calculating each having the second resolution The image of the degree is at a starting address of the memory. The display control method of claim 12, wherein the second resolution is one level lower than the first resolution, and the read image is cut into four of the second resolution Image. The display control method of claim 13, wherein the four images having the second resolution are respectively at the four start addresses of the memory: addrshift0 = ; addrshift1 = ; addrshift2 = ; addrshif3 = Where The image having the first resolution is at a start address of the memory; a width of the image having the first resolution; a height of the image having the first resolution; Depending on a color format of the image having the first resolution. The display control method of claim 10, wherein the synchronization of the clock signal with the synchronization signal means that a rising edge and a falling edge of the clock signal are respectively aligned with rising edges of the two pulses of the synchronization signal; The control timing signal includes a first control signal and a plurality of second control signals in one cycle, the first control signal is opposite to the second control signal, and the first control signal is controlled to transmit the images having the second resolution. The first image is controlled, and the second control signal controls transmission of the other images in the image having the second resolution. The display control method according to claim 10, wherein the image having the first resolution is an 8K image (7680*4320), and the images having the second resolution are 4K images ( 3840*2160). The display control method according to claim 12, wherein the images having the second resolution are sequentially buffered according to a plurality of start addresses, and the images having the second resolution are stored. And reading the images with the second resolution, and restoring the images with the second resolution to the original image having the first resolution according to a starting address of each image.