TWI559382B - Semiconductor device and method of fabricating the same - Google Patents

Description

Semiconductor component and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same.

With the integration of semiconductor elements, in order to achieve high density and high performance, when manufacturing semiconductor elements, it tends to form an upward stacked structure to more effectively utilize the wafer area. Therefore, semiconductor structures having a high aspect ratio are often found in small-sized components. For example, the above semiconductor structure is, for example, a trench including a high aspect ratio.

In general, the fabrication of the above components involves filling the conductor layer with a trench having a high aspect ratio. However, since the gap filling ability of the conductor layer itself is not good, it is easy to form voids which are unevenly dispersed in the trench, which causes the semiconductor element to have an adverse effect on the electrical test. Moreover, the above-mentioned holes may cause unbalanced stress on both sides of the ditch, causing microbending of the semiconductor structure between the trenches, thereby increasing the difficulty of alignment on the subsequent lithography process. Therefore, how to avoid the occurrence of holes in the high aspect ratio trench and prevent the micro-deformation of the semiconductor structure is the subject of current research.

The present invention provides a method of manufacturing a semiconductor device, which can effectively prevent pores that are unevenly dispersed when a conductor material is filled in a trench having a high aspect ratio.

The present invention provides a method of fabricating a semiconductor device, comprising: forming a plurality of fin structures on a substrate and performing at least two cycles to form a first conductor layer. There is a ditch between the fin structures. Each of the above cyclic processes includes a deposition process and an etching process. The deposition process fills the trenches with a first layer of conductive material. The first layer of conductor material covers the top and sidewalls of the fin structure. The etching process removes a portion of the first layer of conductor material. The first thickness of the first conductor layer is adjusted to be smaller than the second thickness of the first conductor layer. The first thickness is a thickness of the first conductor layer located on an upper sidewall of the fin structure, and the second thickness is a thickness of the first conductor layer located on a lower sidewall of the fin structure.

In an embodiment of the invention, after the performing the cyclic process, the method further comprises: filling the trench with a second layer of conductive material.

In an embodiment of the invention, after the cyclic process, the thickness of the first conductor layer decreases from a lower sidewall of the fin structure to an upper sidewall of the fin structure.

In an embodiment of the invention, after the cyclic process, a first angle between a surface of the first conductor layer and a surface of the substrate is smaller than a second between a sidewall of the fin structure and a surface of the substrate Angle.

The present invention provides a semiconductor device comprising: a substrate, a plurality of fin structures, and a first conductor layer. The fin structure is located on the substrate. The first conductor layer covers a sidewall of the fin structure. The first thickness of the first conductor layer is smaller than the second thickness of the first conductor layer. The first thickness is a thickness of the first conductor layer located on an upper sidewall of the fin structure, and the second thickness is a thickness of the first conductor layer located on a lower sidewall of the fin structure.

In an embodiment of the invention, each of the fin structures includes: a strip layer; and a charge storage layer covering the top and sidewalls of the strip layer.

In an embodiment of the invention, each of the fin structures includes: a stacked layer; and a charge storage layer. Each stacked layer includes at least one second conductor layer and at least one dielectric layer that are alternately stacked. A charge storage layer covers the top and sidewalls of the stacked layers.

In an embodiment of the invention, the semiconductor device further includes a second conductor layer covering a surface of the first conductor layer and a top portion of the charge storage layer.

In an embodiment of the invention, the thickness of the first conductor layer is decreased from a lower sidewall of the fin structure to an upper sidewall of the fin structure.

In an embodiment of the invention, a first angle between a surface of the first conductor layer and a surface of the substrate is smaller than a second angle between a sidewall of the fin structure and a surface of the substrate.

The invention further provides a method for fabricating a semiconductor device, comprising: forming a plurality of fin structures on a substrate, wherein the fin structures have a trench therebetween; and filling the conductor layer in the trench, the conductor layer comprising a plurality of conductive material layers And covered a top portion of the fin structure and a sidewall; and adjusting a first thickness of the at least one layer of the conductor material to be less than a second thickness of the conductor material layer, wherein the first thickness is the conductor material located on an upper sidewall of the fin structure The thickness of the layer, the second thickness being the thickness of the conductor material layer located on the lower sidewall of the fin structure.

In an embodiment of the invention, the difference between the first thickness and the second thickness is adjusted to be greater than 1 Å and less than 10 Å.

In an embodiment of the invention, the thickness of the conductor material layer is decreased from a lower sidewall of the fin structure to an upper sidewall of the fin structure.

In an embodiment of the invention, the first angle between the surface of the conductive material layer and the surface of the substrate is smaller than a second angle between the sidewall of the fin structure and the surface of the substrate.

Based on the above, the present invention is characterized in that the first thickness of the first conductive material layer covering the sidewall of the fin structure (the thickness of the first conductive material layer on the upper sidewall of the fin structure) is smaller than the second thickness of the conductive material layer (located The thickness of the first conductive material layer on the lower sidewall of the fin structure can effectively avoid the formation of unevenly dispersed holes when filling the conductor material into the trench of high aspect ratio, thereby improving the electrical performance of the semiconductor device.

The above described features and advantages of the invention will be apparent from the following description.

10‧‧‧Base

12, 12a, 16, 16a‧‧‧ dielectric layer

14, 14a, 32b, 38, 40a‧‧‧ conductor layer

18, 18a‧‧‧Stacking

20, 20a‧‧‧ hard mask layer

22, 22a‧‧‧ charge storage layer

32, 40, 32a‧‧‧ conductor material layer

38a‧‧‧ Strip

50‧‧‧ patterned photoresist layer

100, 200, 300, 400‧‧‧ semiconductor components

101, 201‧‧‧Fin structure

A-A’‧‧‧ line

C‧‧‧ Corner

D1, D2‧‧‧ direction

T‧‧‧ Ditch

T1‧‧‧ thickness

T2‧‧‧ thickness

Θ1‧‧‧ angle

Θ2‧‧‧ angle

Θ3‧‧‧ angle

FIG. 1A is a top view of a semiconductor device in accordance with an embodiment of the invention.

Fig. 1B is a schematic cross-sectional view of the semiconductor device taken along line A-A' of Fig. 1A.

2 is a cross-sectional view of a semiconductor device in accordance with another embodiment of the present invention.

3A-3F are schematic cross-sectional views showing a method of fabricating a semiconductor device in accordance with an embodiment of the invention.

4A-4B are schematic cross-sectional views showing a method of fabricating a semiconductor device in accordance with another embodiment of the present invention.

FIG. 1A is a top view of a semiconductor device in accordance with an embodiment of the invention. Fig. 1B is a schematic cross-sectional view of the semiconductor device taken along line A-A' of Fig. 1A.

1A and 1B, the semiconductor device 100 includes a substrate 10, a patterned dielectric layer 12a, a plurality of fin structures 101, a plurality of conductor layers 32b, and a plurality of conductor layers 40a. Substrate 10 can comprise a semiconductor material, an insulator material, a conductor material, or any combination of the foregoing. The material of the substrate 10 is, for example, selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. A material composed of at least one of the materials or any physical structure suitable for use in the process of the present invention. The substrate 10 includes a single layer structure or a multilayer structure. In addition, a silicon on insulator (SOI) substrate can also be used. The substrate 10 is, for example, tantalum or niobium.

The patterned dielectric layer 12a is located on the substrate 10. The dielectric layer 12a includes an oxide, a nitride, an oxynitride or a low dielectric constant material having a dielectric constant of less than 4. In an embodiment, the dielectric layer 12a is, for example, a bottom oxide layer (BOX). The thickness of the dielectric layer 12a is, for example, between 3,000 Å and 4,000 Å.

A plurality of fin structures 101 are located on the dielectric layer 12a. Each fin structure 101 extends along a first direction D1. There is a trench T between two adjacent fin structures 101. The trench T can be a trench of any length, width, shape. The trench T can be a wide trench or a narrow trench. In one embodiment, the width of the trench T is, for example, between 200 Å and 300 Å; and the depth is, for example, between 5,000 Å and 6,000 Å. In other words, the trench T has a large aspect ratio. In an embodiment, the aspect ratio of the trench T is, for example, between 16 and 30. The cross section of the trench T may be any shape, for example, a V-shape, a U-shape, a diamond shape, or a combination thereof, but the invention is not limited thereto.

Each of the fin structures 101 includes, for example, a stacked layer 18a and a charge storage layer 22a. Each stacked layer 18a includes at least one conductor layer 14a and at least one dielectric layer 16a that are alternately stacked. In one embodiment, the conductor layer 14a is located on the dielectric layer 12a, and the dielectric layer 16a is located on the conductor layer 14a, but the invention is not limited thereto. In another embodiment, the dielectric layer 16a may also be on the dielectric layer 12a. The conductor layer 14a and the dielectric layer 16a are alternately stacked above the substrate 10 to form a stacked layer 18a. In terms of geometry, the angle θ2 between the sidewall of each fin structure 101 and the surface of the substrate 10 is, for example, greater than 85.0 degrees and less than 89.9 degrees. On the other hand, the corner portion C of each of the stacked layers 18a may have a curvature. The dielectric layer 16a may be the same as or different from the material of the dielectric layer 12a. The material of the dielectric layer 16a may include an oxide, a nitride, an oxynitride or a low dielectric constant material having a dielectric constant of less than 4. The thickness of the dielectric layer 16a is, for example, between 300 Å and 500 Å. The material of the conductor layer 14a includes an undoped semiconductor or a doped semiconductor such as polysilicon or doped polysilicon. The thickness of the conductor layer 14a is, for example, between 200 Å and 300 Å. In an embodiment, the conductor layer 14a is, for example, a bit line or a word line as the semiconductor element 100. Further, in this embodiment, the fin structure 101 has, for example, a charge storage layer 22a on the stacked layer 18a composed of a polysilicon layer and an oxide layer which alternate with each other.

1A and 1B, each of the fin structures 101 may optionally further include a hard mask layer 20a. The hard mask layer 20a is, for example, located at the uppermost layer of the fin structure 101, but the invention is not limited thereto. The hard mask layer 20a may be a single layer or a plurality of layers. The material of the hard mask layer 20a is, for example, tantalum oxide, tantalum nitride or other material having a high Young's modulus. The thickness of the hard mask layer 20a is, for example, between 4,000 Å and 5,000 Å.

The charge storage layer 22a covers the sidewall of the stacked layer 18a, the sidewall of the hard mask layer 20a, and the top of the hard mask layer 20a. The material of the charge storage layer 22a includes an oxide, a nitride, or a combination thereof. Specifically, the material of the charge storage layer 22a includes tantalum nitride, tantalum oxide, or a combination thereof. The charge storage layer 22a may be a single layer or a plurality of layers. In an embodiment, the charge storage layer 22a is, for example, a single layer of ruthenium oxide layer. In another embodiment, the charge storage layer 22a is, for example, a composite layer composed of an oxide layer/nitride layer/Oxide (ONO). The thickness of the charge storage layer 22a is, for example, between 200 Å and 300 Å.

The conductor layer 32b is located on the charge storage layer 22a in the trench T and covers a portion of the sidewall of the charge storage layer 22a. In other words, the conductor layer 32b covers the sidewall of each fin structure 101. The conductor layer 32b may be a single layer or a plurality of layers. It is to be noted that the first thickness t1 of the conductor layer 32b is smaller than the second thickness t2 of the conductor layer 32b. The first thickness t1 refers to the thickness of the conductor layer 32b located at the upper sidewall of the fin structure 101, and the second thickness t2 refers to the thickness of the conductor layer 32b located at the lower sidewall of the fin structure 101. Further, when the conductor layer 32b has a multilayer structure, the first thickness t1 and the second thickness t2 refer to the sum of the thicknesses of the multilayer conductor layers. That is, as long as at least one layer of the conductor layer has a thickness distribution in which the thickness of the conductor layer located on the upper side wall of the fin structure 101 is smaller than the thickness of the conductor layer located on the lower side wall of the fin structure 101. In an embodiment, each of the conductor layers has the above thickness distribution. In an embodiment, the thickness of the conductor layer 32b is diminished from the lower sidewall of each fin structure 101 to the upper sidewall of each fin structure 101. In an embodiment, the difference between the first thickness t1 and the second thickness t2 is greater than 1 Å and less than 10 Å, but the invention is not limited thereto. In another embodiment, the angle θ1 between the surface of the conductor layer 32b and the surface of the substrate 10 is smaller than the angle θ2 between the sidewall of each fin structure 101 and the surface of the substrate 10. Each conductor layer 32b extends along a second direction D2. The second direction D2 is different from the first direction D1. The second direction D2 is, for example, orthogonal to the first direction D1. Each conductor layer 32b is located in the trench T and covers a portion of the sidewall of the fin structure 101. The material of the conductor layer 32b is, for example, polycrystalline germanium, doped polycrystalline germanium, metallic material or a combination thereof. The doped polysilicon is, for example, an N+ doped polysilicon or a P+ doped polysilicon. The thickness of the conductor layer 32b is, for example, between 10 Å and 50 Å.

The conductor layer 40a is located on the charge storage layer 22a of the fin structure 101 and extends into the trench T to be electrically connected to the conductor layer 32b. The material of the conductor layer 40a is, for example, polycrystalline germanium, doped polycrystalline germanium, metallic material or a combination thereof. The conductor layer 40a extends along the second direction D2. The doped polysilicon is, for example, an N+ doped polysilicon or a P+ doped polysilicon. The thickness of the conductor layer 40a is, for example, between 1000 Å and 1400 Å.

The conductor layer 40a and the conductor layer 32b are, for example, a word line or a bit line which are collectively used as the semiconductor element 100. It is to be noted that when the conductor layer 40a and the conductor layer 32b are, for example, word lines as the semiconductor element 100, the conductor layer 14a located in the fin structure 101 is used as a bit line. Similarly, when the conductor layer 40a and the conductor layer 32b are, for example, bit lines of the semiconductor element 100, the conductor layer 14a located in the fin structure 101 is used as a word line.

Although the case where the fin structure 101 is constituted by the stacked layer 18a and the charge storage layer 22a is exemplified in the above embodiment, the semiconductor element of the present invention is not limited thereto, and another embodiment will be listed below to explain this point. In addition, the description of the flow and the components similar to the above embodiment will be omitted in the following description.

2 is a cross-sectional view of a semiconductor device in accordance with another embodiment of the present invention.

Please refer to FIG. 1A, FIG. 1B and FIG. 2 simultaneously, which is different from the above embodiment. The semiconductor device 200 of another embodiment of the present invention is similar to the above-described semiconductor device 100, but each of the fin structures 201 includes a strip layer 38a and a charge storage layer 22a. The strip layer 38a does not include the dielectric layer 16a described above, but is composed of a conductor material. The layer of conductor material is, for example, polycrystalline germanium, doped polycrystalline germanium, metallic materials or a combination thereof. The doped polysilicon is, for example, an N+ doped polysilicon or a P+ doped polysilicon. The charge storage layer 22a covers the top and side walls of the strip layer 38a.

Hereinafter, a method of manufacturing a semiconductor device of the present invention will be described.

3A-3F are schematic cross-sectional views showing a method of fabricating a semiconductor device in accordance with an embodiment of the invention.

Referring to Figure 3A, a substrate 10 is provided. The material of the substrate 10 is as described above and will not be described herein. Next, a dielectric layer 12 is formed on the substrate 10. The material and thickness of the dielectric layer 12 are as described above for the portion of the dielectric layer 12a. The method of forming the dielectric layer 12 is, for example, a thermal oxidation method or a chemical vapor deposition method.

Then, a plurality of stacked layers 18 are formed on the dielectric layer 12. Specifically, the step of forming the stacked layer 18 is, for example, forming the electrically stacked conductor layer 14 and the dielectric layer 16. The method of forming each of the stacked layers 18 includes forming the conductive layer 14 on the dielectric layer 12 and forming the dielectric layer 16 on the conductive layer 14, but the invention is not limited thereto. In another embodiment, a method of forming stacked layers 18 includes sequentially forming a plurality of conductor layers 14 and a plurality of dielectric layers 16 on dielectric layer 12. The material and thickness of the conductor layer 14 are as described above for the portion of the conductor layer 14a. The method of forming the conductor layer 14 includes a chemical vapor deposition method. The material and thickness of the dielectric layer 16 are as described above for the portion of the dielectric layer 16a. The method of forming the dielectric layer 16 is, for example, thermal oxidation or chemistry. Vapor deposition method.

Thereafter, a hard mask layer 20 is formed on the uppermost stacked layer 18. The material and thickness of the hard mask layer 20 are as described above in the section of the hard mask layer 20a. The method of forming the hard mask layer 20 includes chemical vapor deposition or organometallic chemical vapor deposition (MOCVD). Next, a patterned photoresist layer 50 is formed on the hard mask layer 20.

Referring to FIG. 3A and FIG. 3B simultaneously, the patterned photoresist layer 50 is used as a mask and etched to form a plurality of stacked layers 18a on the substrate 10, and a plurality of trenches T are formed between the stacked layers 18a. The method of etching the semiconductor device 200 includes etching the hard mask layer 20 with the patterned photoresist layer 50 as a mask to transfer the pattern of the patterned photoresist layer 50 to the hard mask layer 20. The etching method includes an anisotropic etching such as a dry etching method. The dry etching method may be sputtering etching, reactive ion etching, or the like. Next, the patterned photoresist layer 50 is removed. Then, the plurality of dielectric layers 16, the plurality of conductor layers 14, and the dielectric layer 12 are etched with the patterned hard mask layer 20a as a mask to form a plurality of stacked layers 18a on the substrate 10. Further, the angle θ3 between the side wall of each stacked layer 18a and the surface of the substrate 10 is, for example, greater than 85.0 degrees and less than 89.9 degrees. On the other hand, the corner portion C of each of the stacked layers 18a may have a curvature.

Then, referring to FIG. 3C, a charge storage layer 22 is formed on the substrate 10. To form the fin structure 101. The charge storage layer 22 is conformally formed along the top surface and sidewalls of the stacked layer 18a. In other words, the charge storage layer 22 covers the top and sidewalls of the stacked layer 18a. The material and thickness of the charge storage layer 22 are as described above. Charge storage layer 22 The formation method is, for example, a chemical vapor deposition method or a thermal oxidation method.

Referring to FIGS. 3C to 3E, at least two cycles of the process, for example, two to ten times, are performed to form a single or multiple conductor layer 32a in the trench T. In the present specification, the so-called one-time cycle process refers to performing one deposition process and one etching process. More specifically, referring to FIG. 3C, the deposition process refers to filling the trench T with a layer of conductive material 32 (as shown in FIG. 3D) that is conformally formed on the charge storage layer 22. In an embodiment, the material of the conductive material layer 32 is, for example, polycrystalline germanium, doped polycrystalline germanium, metallic material, or a combination thereof. The deposition process can be an atomic layer deposition process or a chemical vapor deposition process.

Referring to FIGS. 3D and 3E, the etching process refers to removing a portion of the conductor material layer 32 to unevenly reduce the thickness of the conductor material layer 32. After at least 2 cycles of the cycle, the first thickness t1 of the formed conductor layer 32a is less than the second thickness t2 of the conductor layer 32a. The first thickness t1 refers to the thickness of the conductor layer 32a located at the upper sidewall of the fin structure 101, and the second thickness t2 refers to the thickness of the conductor layer 32a located at the lower sidewall of the fin structure 101. The etching process can include an isotropic etching process or an anisotropic etching process. Further, when the conductor layer 32a has a multilayer structure, the first thickness t1 and the second thickness t2 refer to the sum of thicknesses of the plurality of layers of the conductor material at different positions. That is, as long as at least one layer of the conductor material in the conductor layer 32a has a thickness distribution in which the thickness of the conductor material layer located on the upper sidewall of the fin structure 101 is smaller than the conductor material layer located on the lower sidewall of the fin structure 101. thickness of. In one embodiment, each of the layers of conductor material in conductor layer 32a has the thickness profile described above. In an embodiment, located in charge storage The layer of conductor material 32 on top of layer 22 and a portion of charge storage layer 22 are also removed. In an embodiment, the top of the charge storage layer 22 is rounded in the etching process. Therefore, after the etching process is performed, the top of the charge storage layer 22a has an arc shape, which is favorable for the conductor material in the subsequent process. The layers are filled in the trenches to avoid the formation of unevenly dispersed holes.

In an exemplary embodiment, the thickness of the conductor layer 32a is diminished from the lower sidewall of the fin structure 101 to the upper sidewall of the fin structure 101. In another exemplary embodiment, the cyclic process is repeated such that there is a difference between the first thickness t1 and the second thickness t2, the difference being greater than 1 Å and less than 10 Å, but the invention is not limited thereto. In another embodiment, the angle θ1 between the surface of the conductor layer 32a and the surface of the substrate 10 is smaller than the angle θ2 between the sidewall of each fin structure 101 and the surface of the substrate 10.

Next, referring to FIG. 3F, a conductor material layer 40 is formed on the top of the charge storage layer 22a of the fin structure 101 and the surface of the conductor layer 32a. The conductor material layer 40 fills the trench T and is electrically connected to the conductor layer 32a. The material of the conductor material layer 40 is, for example, polycrystalline germanium, doped polycrystalline germanium, metallic material or a combination thereof. The doped polysilicon is, for example, an N+ doped polysilicon or a P+ doped polysilicon. A method of forming the conductor material layer 40 includes a chemical vapor deposition method. In an embodiment, the formed conductor layer 32a and the conductor material layer 40 may also be heat treated to diffuse the holes in the conductor layer 32a and the conductor material layer 40 to the outside or to gather on top of the trench T. The method of performing the above heat treatment is, for example, rapidly heating the formed conductor layer 32a and the conductor material layer 40 to 800 ° C to 1100 ° C and immediately cooling to 25 ° C to 100 ° C, or heating to 600 ° C to 1000 ° C and holding the temperature 1 Hours ~ 24 hours. The rate of temperature rise is, for example, 300 ° C / Hours ~ 500 ° C / hour. The heat treatment environment is, for example, under a hydrogen atmosphere. The method of raising the temperature is, for example, heating using a laser pulse.

Next, referring to FIG. 1A, FIG. 1B, and FIG. 3F, the conductor layer 32a and the conductor material layer 40 are patterned to form a plurality of conductor layers 32b and a plurality of conductor layers 40a on the substrate 10. Each of the conductor layers 32b extends in a direction different from the direction in which the fin structures 101 extend, for example, perpendicular to each other. Each conductor layer 32b is located in the trench T and covers a portion of the sidewall of the fin structure 101. Each of the conductor layers 40a is located on the charge storage layer 22a of the fin structure 101 and extends into the trench T while also covering the surface of the conductor layer 32b. Each of the conductor layers 40a also covers the charge storage layer 22a on the top surface of the fin structure 101.

It is to be noted that since the present invention utilizes a cyclic process to form a thin and thick conductor layer 32a on the sidewall of the fin structure to reduce the aspect ratio of the trench, the subsequent formation of the conductor material layer 40 is easier to fill. In the trench, the semiconductor device 300 of the present invention is less likely to create voids in the trench T than the conventional components that directly fill the conductor material layer in the trench.

Although the case where the fin structure 101 is constituted by the stacked layer 18a and the charge storage layer 22a is exemplified in the above embodiment, the method of manufacturing the semiconductor device of the present invention is not limited thereto, and another embodiment will be listed below to explain this. a little. In addition, the description of the flow and the components similar to the above embodiment will be omitted in the following description.

4A-4B are schematic cross-sectional views of a semiconductor device in accordance with another embodiment of the present invention.

Referring to FIG. 4A, unlike the above embodiment, the method of fabricating the semiconductor device 400 of another embodiment of the present invention is similar to the method for fabricating the semiconductor device 300 described above, but after the dielectric layer 12 is formed on the substrate 10, A conductor layer 38 is formed on the dielectric layer 12 without forming the dielectric layer 16 described above. The material of the conductor layer 38 is as described above in the section of the strip layer 38a, and thus will not be described again. The method of forming the conductor layer 38 includes a chemical vapor deposition method. Thereafter, a hard mask layer 20 is formed on the conductor layer 38, and a patterned photoresist layer 50 is formed on the hard mask layer 20.

Referring to FIG. 4B, the patterned photoresist layer 50 is used as a mask and etched to form a plurality of strip layers 38a on the substrate 10, and a plurality of trenches T are formed between the strip layers 38a. The method of etching the semiconductor device 400 has been described in detail in the above embodiments, and thus will not be described again.

Referring to FIG. 2 and FIG. 4B simultaneously, the subsequent steps of forming the charge storage layer 22a to form the plurality of fin structures 201, the steps of forming the conductive material layers 32, 40, and the steps of reducing the thickness of the conductive material layer 32 are as follows. It has been described in detail in the description of the above embodiments, and thus will not be described again.

In summary, the present invention forms a thin and thick first conductor material layer on the sidewall of the fin structure, so that the subsequently formed second conductor material layer has better trench filling property, and therefore, the conductor can be effectively avoided. When the material is filled into a trench having a high aspect ratio, a hole that is unevenly dispersed is formed, thereby improving the electrical performance of the semiconductor device.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of protection of the present invention It is subject to the definition of the scope of the patent application attached.

10‧‧‧Base

12a, 16a‧‧‧ dielectric layer

14a, 32b, 40a‧‧‧ conductor layer

18a‧‧‧Stacking

20a‧‧‧hard mask layer

22a‧‧‧Charge storage layer

100‧‧‧Semiconductor components

101‧‧‧Fin structure

C‧‧‧ Corner

T‧‧‧ Ditch

T1‧‧‧ thickness

T2‧‧‧ thickness

Θ1‧‧‧ angle

Θ2‧‧‧ angle

Claims (14)

A method of fabricating a semiconductor device, comprising: forming a plurality of fin structures on a substrate, wherein the fin structures have a trench therebetween; and performing at least two cycles to form a first conductor layer, wherein each A recycling process includes: a deposition process in which a first layer of conductor material is filled, the first layer of conductor material covering the top and sidewalls of the fin structures; and an etching process to remove portions of the first a layer of conductive material, wherein a first thickness of the first conductor layer is adjusted to be smaller than a second thickness of the first conductor layer, wherein the first thickness is the first conductor layer located on an upper sidewall of the fin structures The thickness of the second conductor is the thickness of the first conductor layer on the lower sidewall of the fin structures. The method of fabricating a semiconductor device according to claim 1, wherein after the performing the cyclic processes, the method further comprises: filling a trench with a second layer of conductive material. The method of fabricating a semiconductor device according to claim 1, wherein the cyclic process is performed such that a thickness of the first conductor layer is from a lower sidewall of the fin structure to an upper sidewall of the fin structure Decrement. The method of manufacturing a semiconductor device according to claim 1, wherein the cyclic processes are performed such that a first angle between a surface of the first conductor layer and a surface of the substrate is smaller than the fin structures Side wall and surface of the substrate A second angle between the two. A semiconductor device comprising: a substrate; a plurality of fin structures on the substrate; and a first conductor layer covering the sidewalls of the fin structures, wherein a first thickness of the first conductor layer is less than the first a second thickness of a conductor layer, the first thickness being a thickness of the first conductor layer on an upper sidewall of the fin structures, the second thickness being the first portion located on a lower sidewall of the fin structures The thickness of the conductor layer. The semiconductor device of claim 5, wherein each fin structure comprises: a strip layer; and a charge storage layer covering a top portion and a sidewall of the strip layer. The semiconductor device of claim 5, wherein each of the fin structures comprises: a stacked layer, each stacked layer comprising at least one second conductive layer and at least one dielectric layer alternately stacked; and a charge storage A layer covering the top and side walls of the stacked layer. The semiconductor device of claim 5, further comprising: a second conductor layer covering a surface of the first conductor layer and a top portion of the charge storage layer. The semiconductor device according to claim 5, wherein the first The thickness of the conductor layer is diminished from the lower sidewall of each fin structure to the upper sidewall of each fin structure. The semiconductor device of claim 5, wherein a first angle between a surface of the first conductor layer and a surface of the substrate is less than a gap between a sidewall of each fin structure and a surface of the substrate The second angle. A method of fabricating a semiconductor device, comprising: forming a plurality of fin structures on a substrate, wherein the fin structures have a trench therebetween; and filling a trench in the trench, the conductor layer includes a plurality of conductive material layers And covering the top and sidewalls of the fin structures; and adjusting a first thickness of the at least one layer of conductive material to be less than a second thickness of the layer of conductive material, wherein the first thickness is located in the fin structures The thickness of the layer of conductor material of the upper sidewall is the thickness of the layer of conductor material at the lower sidewall of the fin structures. The method of manufacturing a semiconductor device according to claim 11, wherein the difference between the first thickness and the second thickness is adjusted to be greater than 1 Å and less than 10 Å. The method of fabricating a semiconductor device according to claim 11, wherein the thickness of the conductor material layer is decreased from a lower sidewall of the fin structure to an upper sidewall of the fin structures. The method of manufacturing a semiconductor device according to claim 11, wherein a first angle between a surface of the conductor material layer and a surface of the substrate is small. a second angle between the sidewall of the fin structure and the surface of the substrate.