TWI524439B - Semiconductor device and method of forming vertical interconnect structure using stud bumps - Google Patents

Description

Semiconductor component and method of forming vertical interconnect structure using bumps

The present invention relates generally to semiconductor devices, and more particularly to the use of stud bumps and integrated passive components for a fan-out wafer level chip scale package (FO-WLCSP). Integrated passive device; IPD) A semiconductor component and method for forming a vertical interconnect structure.

Semiconductor components are commonly found in modern electronics. The number and density of electrical components contained in different semiconductor components vary. A single-piece semiconductor component typically includes an electrical component such as a light emitting diode (LED), a small signal transistor, a resistor, a capacitor, an inductor, and a power metal oxide semiconductor field effect transistor (metal) Oxide semiconductor field effect transistor; MOSFET). Integrated semiconductor components typically contain hundreds to millions of electrical components. Examples of integrated semiconductor components include a microcontroller, a microprocessor, a charged-coupled device (CCD), a solar cell, and a digital micro-mirror device. ;DMD).

Semiconductor components perform a wide variety of functions, such as high speed computing, transmitting and receiving electromagnetic signals, controlling electronics, converting sunlight into electricity, and producing visual projections of television displays. Semiconductor components are used in entertainment, communications, power conversion, networking, computers, and consumer products. Semiconductor components are also found in military applications, aerospace, automotive, industrial controllers, and office equipment.

Semiconductor components utilize the electrical properties of semiconductor materials. The atomic structure of the semiconductor material allows its conductivity to be controlled using an electric field or via a doping procedure. The doping incorporates impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor components.

Semiconductor components include active and passive electrical structures. The active structure consists of a bi-carrier and a field-effect transistor that controls the flow of current. The current flow in the transistor is boosted or suppressed by varying the degree of doping and applying an electric or base current. Passive structures, including resistors, capacitors, and inductors, establish a specific relationship between voltage and current to achieve various electrical functions. The passive and active structures are electrically connected to each other to form a circuit that enables the semiconductor component to perform high speed calculations as well as other useful functions.

The production of semiconductor components generally utilizes two complex processes, namely, front-end fabrication and back-end fabrication, each of which may contain hundreds of steps. The front end fabrication includes forming a plurality of grains on a surface of a semiconductor wafer. Each of the dies is substantially identical to each other and includes circuitry formed by electrically connecting the active and passive components. The back end manufacturing includes self-finishing wafer singulation of individual dies and encapsulating the dies to provide structural support and environmental isolation.

One of the goals of semiconductor manufacturing is to produce smaller semiconductor components. Smaller components typically consume less power, are more efficient, and can be produced more efficiently. In addition, smaller semiconductor components have a smaller footprint and are necessary for small products. Smaller grain sizes can be achieved by improving the front end process, which produces grains with smaller and higher density active and passive components. The back-end process can result in a semiconductor component package with a smaller footprint by improvements in electrical interconnects and packaging materials.

Another goal of semiconductor manufacturing is to produce higher performance semiconductor components. Improvements in component performance can be achieved by forming active components that can operate at higher speeds. In high frequency applications, such as radio frequency (RF) wireless communications, IPDs are often included within semiconductor components. Examples of IPDs include resistors, capacitors, and inductors. A typical RF system requires multiple IPDs in one or more semiconductor packages to perform the required electrical functions.

Electrical interconnections between semiconductor packages can be achieved via conductive through silicon vias (TSVs) or through hole vias (THVs). To form a TSV or THV, the semiconductor die is singulated from the wafer and placed over a temporary carrier. When the die is fixed to the carrier, it cuts through a perforation in the semiconductor material or in a peripheral region surrounding each of the semiconductor grains. The perforations are then filled with an electrically conductive substance, for example, by a copper deposition process.

Due to the relatively small area, the formation of TSV and THV requires considerable time on the filling of the perforations. A fully filled TSV can create high stresses between the perforations, resulting in cracks and lower reliability. Equipment required for electroplating, such as electroplating baths, and passivation of sidewalls, both increase manufacturing costs. In addition, voids may form inside the perforations which cause defects and reduce the reliability of the components. For manufacturing vertical electrical leads in semiconductor packages, TSV and THV can be slow and costly. These interconnection mechanisms also have problems in production yield, large package size, and process cost management.

It is desirable to provide a vertical interconnect structure for stacked semiconductor components. In view of this, in one embodiment, the present invention is a method of fabricating a semiconductor device, the steps of which include providing a temporary carrier and forming a conductive layer over the temporary carrier. The conductive layer comprises a wettable pad. The method further includes forming a stud bump on the wettable pad, fixing a semiconductor die or component to the temporary carrier, depositing an encapsulant on the semiconductor die or component, and the bump A pillar structure is formed around the pillar bump and a first interconnect structure is formed on the first surface of the encapsulant. The first interconnect structure includes a first IPD and is electrically connected to the stud bump. The method further includes removing the temporary carrier and forming a second interconnect structure on a second surface of one of the encapsulants on the opposite side of the first interconnect structure.

In another embodiment, the invention is a method of fabricating a semiconductor device, the method comprising the steps of: providing a carrier, forming a stud bump on the carrier, securing a semiconductor die or component to the carrier, depositing a package And surrounding the stud bump and forming a first interconnect structure on a first surface of the encapsulant. The first interconnect structure is electrically connected to the stud bump.

In another embodiment, the present invention is a method of fabricating a semiconductor device, the method comprising the steps of forming a first interconnect structure having a first IPD, forming a stud bump over the first interconnect structure, Fixing a semiconductor die or component to the first interconnect structure, depositing an encapsulant on the semiconductor die or component, and surrounding the stud bump and forming a second interconnect structure on the first interconnect structure pair On the side of the encapsulant.

In another embodiment, the invention is a semiconductor component comprising a first interconnect structure having a first IPD. A stud bump is formed over the first interconnect structure. A semiconductor die or component is secured to the first interconnect structure. An encapsulant is deposited over the semiconductor die or component and around the stud bumps. A second interconnect structure is formed on the encapsulant on the opposite side of the first interconnect structure.

The details of the present invention are described in the following with reference to the embodiments of the drawings, wherein the same reference numerals represent the same or similar components. Although the description of the present invention is the best mode of achieving the objectives of the present invention, it is understood by those skilled in the art that it encompasses alternatives, modifications, and the like included in the spirit and scope of the invention as defined by the appended claims. An effective structure or method, and equivalent structures or methods supported by the following disclosure and drawings.

The production of semiconductor components generally utilizes two complex processes: front-end manufacturing and back-end manufacturing. The front end fabrication includes forming a plurality of grains on a surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to each other to form a functional circuit. Active electrical components such as transistors and diodes have the ability to control the flow of current. Passive electrical components such as capacitors, inductors, resistors, and transformers establish the relationship between the particular voltage and current required to achieve various circuit functions.

Passive and active components are formed on the surface of a semiconductor wafer by a series of process steps including doping, deposition, photolithography, etching, and planarization. The doping process incorporates impurities into the semiconductor material by techniques such as ion implantation or thermal diffusion. The doping process modifies the conductivity of the semiconductor material in the active device, converts the semiconductor material into an insulator, a conductor, or dynamically changes the conductivity of the semiconductor material in response to an electric field or a base current. The transistor contains regions of different types and doping levels depending on the desired configuration, enabling the transistor to boost or suppress the flow of current depending on the applied electric field or base current.

Active and passive components are formed by a stack of materials having different electrical characteristics. The formation of such laminates can be accomplished by a variety of deposition techniques that are somewhat dependent on the type of material being deposited. For example, thin film deposition may include chemical vapor deposition (CVD), physical vapor deposition (PVD), electrolytic plating, and electroless plating. Each stack is typically patterned to form an active component, a passive component, or an electrical connection between components.

The laminate can be patterned using optical lithography, which involves depositing a photosensitive material such as a photoresist onto the laminate to be patterned. The pattern utilizes light to be transferred from a photomask to a photoresist. It removes the light-resistant photoresist pattern portion using a solvent to expose the underlying portion to be patterned. After the remaining photoresist is removed, a patterned laminate remains. Alternatively, the patterning of certain materials is by depositing the material directly into areas or spaces formed by a prior deposition/etch process using techniques such as electroless and electrolytic plating.

Depositing a thin film material onto an existing pattern can enlarge the underlying pattern and create a non-uniform flat surface. It requires a uniform flat surface to produce smaller and structurally dense active and passive components. It can use a planarization process to remove material from the wafer surface and create a uniform flat surface. Planarization involves smoothing the surface of the wafer with a polishing pad. Abrasive materials and corrosive chemicals are added to the surface of the wafer during smoothing. The mechanical action of the abrasive material, combined with the corrosive action of the chemical, removes any irregular surface relief resulting in a uniform flat surface.

Backend fabrication involves cutting or singulating the finished wafer into individual dies, and then packaging the dies to provide structural support and environmental isolation. In the case of a singulated die, the wafer is scored and cut along a non-functional area on the wafer called a saw or saw wire. Wafer singulation utilizes a laser cutting tool or saw blade. After singulation, individual dies are secured to a package substrate that includes pins or contact pads for interconnecting with other system components. The pads formed on the semiconductor die are then connected to the pads inside the package. This electrical connection can be achieved by solder bumps, stud bumps, conductive paste or wirebond. An encapsulant or other molding material is deposited on the package to provide physical support and electrical insulation. The completed package is inserted into the electrical system such that the functionality of the semiconductor component can be used by other system components.

1 illustrates an electronic device 50 having a wafer carrier substrate or PCB 52 with a plurality of semiconductor packages mounted thereon. The electronic device 50 can have a semiconductor package, or a plurality of types of semiconductor packages, depending on its application. For purposes of illustration, Figure 1 shows different types of semiconductor packages.

The electronic device 50 can be a stand-alone system that performs one or more electrical functions using the semiconductor packages. Alternatively, electronic device 50 can be a secondary component in a larger system. For example, the electronic device 50 can be a graphics card, a network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include a microprocessor, a memory, an application specific integrated circuit (ASIC), a logic circuit, an analog circuit, an RF circuit, a separate component, or other semiconductor die or electrical component.

In FIG. 1, PCB 52 provides a common substrate for structural support and electrical interconnection to a semiconductor package mounted on the PCB. The conductive signal traces 54 are formed on one surface or laminate of the PCB 52 by evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process. Signal traces 54 provide electrical communication between the semiconductor package, the fixed components, and other external system components. Trace 54 also provides power and ground connections to each semiconductor package.

In some embodiments, a semiconductor component has two package levels. The first level of packaging is a technique for mechanically and electrically assembling semiconductor dies to an intermediate carrier. The second level package includes mechanically and electrically assembling the intermediate carrier to the PCB. In other embodiments, a semiconductor component may have only a first level package in which the die is directly fixed to the PCB in a mechanical and electrical manner.

For purposes of illustration, a number of first level package types, including wire bond packages 56 and flip chips 58, are shown on top of PCB 52. In addition, a plurality of types of second level packages, including a ball grid array (BGA) 60, a bump chip carrier (BCC) 62, and a dual in-line package (DIP) 64, land grid array (LGA) 66, multi-chip module (MCM) 68, quad flat non-leaded package (QFN) 70 and four flat A quad flat package 72 is shown mounted on the PCB 52. Any combination of semiconductor packages, configured in any combination of first and second level package formats, as well as other electronic components, can be coupled to PCB 52, depending on system requirements. In some embodiments, electronic device 50 includes a single assembled semiconductor package, while other embodiments may require multiple interconnected packages. By incorporating one or more semiconductor packages onto a single substrate, the manufacturer can add the finished component to the electronic device and system. Because semiconductor packages contain complex functions, electronic devices can be produced using less expensive components and a production line flow process. The resulting device is less prone to failure and less expensive to produce, resulting in lower cost to the consumer.

2a-2c show an exemplary semiconductor package. Figure 2a illustrates further details of the DIP 64 affixed to the PCB 52. The semiconductor die 74 includes an active region including an analog or digital circuit implemented as an active component, a passive component, a conductive layer, and a dielectric layer, and is electrically formed in the die according to the electrical design of the die. even. For example, the circuit can include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit components formed within the active region of the semiconductor die 74. The pad 76 is one or more layers of conductive materials, such as aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au) or silver (Ag), which are electrically connected to the semiconductor crystal. Circuit components within the pellets 74. During assembly of the DIP 64, the semiconductor die 74 is secured to an intermediate carrier 78 using a gold-silicon eutectic layer or an adhesive material such as a thermal epoxy. The package body comprises an insulating encapsulating material such as a polymer or a ceramic. Conductor lead 80 and wire bond 82 provide an electrical interconnection between semiconductor die 74 and PCB 52. The encapsulant 84 is deposited on the package for environmental protection by preventing moisture and particulates from entering the package contamination grain 74 or wire bond 82.

FIG. 2b illustrates further details of the BCC 62 secured to the PCB 52. The semiconductor die 88 is secured to the carrier 90 by an underfill or epoxy synthetic resin bonding material 92. Wire bonding 94 provides a first level package interconnect between pads 96 and 98. A molding material or encapsulant 100 is deposited over the semiconductor die 88 and the wire bond 94 to provide support and electrical isolation of the component body. The pads 102 are formed on one surface of the PCB 52 by a suitable metal deposition such as electrolytic plating or electroless plating to prevent oxidation. The pad 102 is electrically connected to one or more conductive signal traces 54 in the PCB 52. Bumps 104 are formed between pads 98 of BCC 62 and pads 102 of PCB 52.

In FIG. 2c, the semiconductor die 58 is fixed to the interposer carrier 106 in a flip chip form with the first level package facing down. The active region 108 of the semiconductor die 58 includes analog or digital circuitry implemented as active, passive, conductive, and dielectric layers in accordance with the electrical design of the die. For example, the circuit can include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit components within the active region 108. Semiconductor die 58 is electrically and mechanically coupled to carrier 106 via bumps 110.

The BGA 60 utilizes bumps 112 to electrically and mechanically connect to the PCB 52 in a second level package in the form of a BGA. The semiconductor die 58 is electrically connected to the conductive signal traces 54 in the PCB 52 through the bumps 110, the signal lines 114, and the bumps 112. A molding material or encapsulant 116 is deposited over the semiconductor die 58 and the carrier 106 to provide support and electrical isolation of the component body. The flip-chip semiconductor component provides a very short electrical conduction path from the active component on the semiconductor die 58 to the conductive traces on the PCB 52 to reduce signal propagation distance, reduce capacitance, and improve overall circuit performance. In another embodiment, the semiconductor die 58 may be electrically and mechanically directly connected to the PCB 52 using a flip-chip first level package without via the interposer carrier 106.

Figures 3a-3h illustrate a process for forming a vertical interconnect structure with stud bumps and IPDs for FO-WLCSP. In FIG. 3a, a temporary substrate or carrier 120 comprises a susceptor material such as germanium, polymer, polymeric composition, metal, ceramic, glass, glass epoxy, beryllium oxide or other A suitable low-cost, sturdy material for structural support. A selective interface layer 121 can be formed over the carrier 120 as an etch stop layer. An electrically conductive layer 122 is formed over the interface layer 121 and the carrier 120 by patterning, PVD, CVD, sputtering, electrolytic plating, electroless plating, or other suitable metal deposition process. Conductive layer 122 can be one or more layers of aluminum, copper, tin, nickel, gold, silver, tungsten, poly-silicon, or other suitable electrically conductive material. The conductive layer 122 includes a wettable pad to facilitate the formation of subsequent stud bumps. In one embodiment, the wettable pads of the conductive layer 122 are pre-plated over the interface layer 121.

A plurality of semiconductor dies or components 124 are secured to the interface layer 121 in a flip chip configuration with the pads 126 facing downwardly over the carrier 120. Each of the semiconductor dies 124 includes an active surface 128 including an analog or digital circuit implemented as an active device, a passive device, a conductive layer, and a dielectric layer, and is formed within the die, and is electrically designed according to the die And the functions are electrically interconnected to each other. For example, the circuit can include one or more transistors, diodes, and other circuit components formed in the active surface 128 to implement a base frequency analog circuit or a digital circuit, such as a digital signal processor (DSP). , ASIC, memory or other signal processing circuit. Semiconductor die 124 may also include an IPD, such as an inductor, capacitor, and resistor for RF signal processing. In another embodiment, a separate semiconductor component can be secured to the interface layer 121.

In FIG. 3b, a plurality of stud bumps or rod structures 130 are formed on the wettable pads of the conductive layer 122. In an embodiment, a wire bonding machine can form stud bumps 130. The stud bumps 130 have a height ranging from 2 to 120 micrometers (μm).

FIG. 3b shows that the stud bump 130 is implemented as a bump having a convex post shape, including the bump portion 132 and the stud portion 134. In another embodiment, the stud bumps 130 can be formed as stacked bumps 136, as shown in Figure 3c. The stud bumps 130 can also be formed without the conductive layer 122, as shown in Figure 3d. In any event, the formation of the stud bumps 130 is a simple, low cost process.

Figure 3e shows an encapsulant or molding material 138 using paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination ( A vacuum lamination or other suitable coating mechanism is deposited over the semiconductor die 124 and the stud bumps 130. The encapsulant 138 may be a polymer synthetic material such as an epoxy resin having a filler, an epoxy acrylate having a filler, or a polymer having a suitable filler. The encapsulant 138 is non-conductive and environmentally protects the semiconductor component from external components and contamination. Encapsulant 138 is subjected to grinding or plasma etching to planarize its surface and expose stud bumps 130. Alternatively, the height of the stud bumps 130 may be less than the thickness of the semiconductor die 124 (the die faces face down). After the package is performed, both the encapsulant and the back side of the semiconductor die 124 are ground or planarized until the stud bumps 130 are exposed. By doing so, the stud bumps 130 have a higher degree of reliability against the flow of the encapsulant, the material cost of the stud bumps is reduced, and the total package height can be reduced.

In FIG. 3f, a top side accretion interconnect structure 140 is formed on one of the first surfaces of encapsulant 138. The hyperplastic interconnect structure 140 includes an insulating or passivation layer 142 formed by PVD, CVD, printing, spin coating, spray coating, sintering, or thermal oxidation. The passivation layer 142 may be one or more layers of hafnium oxide (SiO ₂ ), hafnium nitride (Si ₃ N ₄ ), hafnium oxynitride (SiON), tantalum pentoxide (Ta ₂ O ₅ ), aluminum oxide (Al ₂ O). ₃ ) or other laminates of materials having similar insulating and structural properties. A portion of passivation layer 142 is removed by an etch process to expose stud bumps 130.

An electrically conductive layer 144 is formed over the insulating layer 142 and the stud bumps 130 by patterning, PVD, CVD, sputtering, electrolytic plating, electroless plating, or other suitable metal deposition process. Conductive layer 144 can be one or more layers of aluminum, copper, tin, nickel, gold, silver, or other suitable electrically conductive material. A portion of the conductive layer 144 is electrically connected to the stud bumps 130. Other portions of conductive layer 144 may be electrically or electrically insulated from each other depending on the design and function of the semiconductor components.

An insulating or passivation layer 146 is formed over passivation layer 142 and conductive layer 144 by PVD, CVD, printing, spin coating, spray coating, sintering, or thermal oxidation. Passivation layer 146 can be one or more layers of SiO ₂ , Si ₃ N ₄ , SiON, Ta ₂ O ₅ , Al ₂ O ₃ , or other materials having similar insulating and structural properties. A portion of passivation layer 146 is removed by an etch process to expose conductive layer 144.

In Figure 3g, it is by chemical etching, mechanical peel-off, CMP, mechanical grinding, thermal bake, laser scanning or wet stripping (wet) Stripping) to remove the carrier 120 and the interface layer 121. After the carrier 120 and the interface layer 121 are removed, the conductive layer 122 and the pads 126 of the semiconductor die 124 are exposed.

In FIG. 3h, a bottom side growth interconnect structure 150 is formed on a second surface of the encapsulant 138, on the opposite side of the top side growth interconnect structure 140, and on a front side surface of the semiconductor die 124. The hyperplastic interconnect structure 150 includes an electrically conductive layer 152 formed by patterning, PVD, CVD, sputtering, electrolytic plating, electroless plating, or other suitable metal deposition process. Conductive layer 152 can be one or more layers of aluminum, copper, tin, nickel, gold, silver, or other suitable electrically conductive material. A portion of the conductive layer 152 is electrically connected to the stud bumps 130 and the pads 126 of the semiconductor die 124. Other portions of conductive layer 152 may be electrically or electrically insulated from each other depending on the design and function of the semiconductor components.

An insulating or passivation layer 154 is formed on conductive surface 152 and active surface 128 of semiconductor die 124 by PVD, CVD, printing, spin coating, spray coating, sintering, or thermal oxidation. The passivation layer 154 may be one or more layers of SiO ₂ , Si ₃ N ₄ , SiON, Ta ₂ O ₅ , Al ₂ O ₃ , or other materials having similar insulating and structural properties. A portion of passivation layer 154 is removed by an etch process to expose conductive layer 152.

An electrically conductive bump material is deposited over the conductive layer 152 by an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be aluminum, tin, nickel, gold, silver, palladium (Pb), bismuth (Bi), copper, solder, and combinations of the foregoing, plus a selective flux. For example, the bump material can be eutectic tin/palladium, high lead solder, or lead free solder. The bump material is bonded to the conductive layer 152 using a suitable adhesion or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form spherical solder balls or bumps 156. In some applications, bumps 156 are reflowed a second time to promote electrical contact with conductive layer 152. The bumps can also be bonded to the conductive layer 152. Bumps 156 represent an interconnect structure type that can be formed on conductive layer 152. The interconnect structure can also use wiring, conductive paste, stud bumps, micro bumps, or other electrical connections.

The semiconductor die 124 is singulated into individual semiconductor components 160 by a saw blade or laser cutting tool 158, as shown in FIG. After singulation, individual semiconductor components 160 can be stacked as shown in FIG. The stud bumps 130 provide vertical z-direction interconnections between the top side accretion interconnect layer 140 and the bottom side accretion interconnect layer 150. The conductive layer 144 is electrically connected to the conductive layer 152 of each of the semiconductor elements 160 and the pads 126 via the stud bumps 130 .

Figure 6 illustrates an embodiment of a vertical interconnect structure in which the semiconductor die has an active surface that faces upward. Similar to the process illustrated in Figures 3a-3h, the semiconductor device 170 uses a temporary substrate or carrier having a selective interface layer that acts as an etch stop layer. An electrically conductive layer 172 is formed over the carrier by patterning, PVD, CVD, sputtering, electrolytic plating, electroless plating, or other suitable metal deposition process. Conductive layer 172 can be one or more layers of aluminum, copper, tin, nickel, gold, silver, tungsten, polysilicon or other suitable electrically conductive material. The conductive layer 172 includes a wettable pad to facilitate the formation of subsequent stud bumps.

A plurality of semiconductor dies or components 174 are affixed to the carrier in a flip chip configuration with pads 176 facing up. The semiconductor die 174 includes an active surface 178 including analog or digital circuits implemented as active components, passive components, conductive layers, and dielectric layers formed within the die, and electrically coupled to each other depending on the electrical design and function of the die Sexual interconnection. For example, the circuit can include one or more transistors, diodes, and other circuit components formed in the active surface 178 to implement a base frequency analog circuit or digital circuit, such as a DSP, ASIC, memory, or other signal processing circuit. . Semiconductor die 174 may also include an IPD, such as inductors, capacitors, and resistors for RF signal processing. In another embodiment, a separate semiconductor component can be secured to the carrier or interface layer.

A plurality of stud bumps 180 are formed on the wettable pads of the conductive layer 172. In addition, a plurality of stud bumps 182 are formed on pads 176 of semiconductor die 174. It uses a one-wire bonding machine to form stud bumps 180-182 by a stud bump process. The stud bumps 180-182 can be copper, aluminum, tungsten, gold, solder, or other suitable electrically conductive material. In one embodiment, the stud bumps 180-182 are implemented as bumps having a convex cylindrical shape. Alternatively, stud bumps 180-182 may be formed as stacked bumps, similar to that shown in Figure 3c. The wiring 186 is electrically connected between the pad 176 and the conductive layer 172.

An encapsulant or molding material 188 is deposited on the semiconductor die 174 and stud bumps 180-182 using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, or other suitable coating mechanism. Above. The encapsulant 188 may be a polymer synthetic material such as an epoxy synthetic resin having a filler, an epoxy acrylate having a filler, or a polymer having a suitable filler. The encapsulant 188 is non-conductive and environmentally protects the semiconductor component from external components and contamination. Encapsulant 188 is subjected to grinding or plasma etching to planarize its surface and expose stud bumps 180-182.

A top side accretion interconnect structure 190 is formed on one of the first surfaces of the encapsulant 188. The hyperplastic interconnect structure 190 includes an insulating or passivation layer 192 formed by PVD, CVD, printing, spin coating, spray coating, sintering, or thermal oxidation. A portion of the passivation layer 192 is removed by an etch process to expose the stud bumps 180-182. An electrically conductive layer 194 is formed over the passivation layer 192 and the stud bumps 180-182. A portion of the conductive layer 194 is electrically connected to the stud bumps 180-182, respectively. Other portions of conductive layer 194 may be electrically or electrically insulated from one another depending on the design and function of the semiconductor components. An insulating or passivation layer 196 is formed over the passivation layer 192 and the conductive layer 194. A portion of passivation layer 196 is removed by an etch process to expose conductive layer 194.

The carrier and interface layer are removed by chemical etching, mechanical stripping, CMP, mechanical milling, thermal baking, laser scanning or wet stripping. A bottom side growth interconnect structure 200 is formed on one of the second surfaces of the encapsulant 188, on the opposite side of the top side growth interconnect structure 190, and on one of the back side surfaces of the semiconductor die 174. An electrically conductive layer 202 is formed on the back side surfaces of the conductive layer 172 and the semiconductor die 174. A portion of the conductive layer 202 is electrically connected to the stud bumps 180. Other portions of conductive layer 202 may be electrically or electrically insulated from one another depending on the design and function of the semiconductor components. An insulating or passivation layer 204 is formed over the back side surfaces of the conductive layer 202 and the semiconductor die 174. A portion of the insulating layer 204 is removed by an etching process to expose the conductive layer 202.

An electrically conductive bump material is deposited on the conductive layer 202 by an evaporation, electrolytic plating, electroless plating, solder ball implantation or screen printing process. The bump material can be aluminum, tin, nickel, gold, silver, palladium, rhodium, copper, solder, and combinations of the foregoing, plus a selective fluxing solvent. For example, the bump material can be eutectic tin/palladium, high lead solder, or lead free solder. The bump material is bonded to the conductive layer 202 using a suitable adhesion or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form spherical solder balls or bumps 206. In some applications, bumps 206 are reflowed a second time to enhance electrical contact with conductive layer 202. The bumps can also be crimped to the conductive layer 202. Bumps 206 represent an interconnect structure type that can be formed on conductive layer 202. The interconnect structure can also use wiring, conductive paste, stud bumps, microbumps, or other electrical connections.

The semiconductor components 170 are stackable. The stud bumps 180-182 provide a vertical z-direction interconnect between the top side accumulating interconnect layer 190 and the bottom side accelerating interconnect layer 200. The conductive layer 194 is electrically connected to the conductive layer 202 of the semiconductor device 170, the pad 176, and the wiring 186 via the stud bumps 180-182.

Figure 7 illustrates an embodiment of a vertical interconnect structure having one or more IPDs formed in a bottom side interconnect structure prior to packaging. In this example, a bottom side growth interconnect structure 240 is formed over the carrier. An electrically conductive layer 242 is patterned and deposited to form individual portions or sections 242a-242h using PVD, CVD, sputtering, electrolytic plating, electroless plating processes, or other suitable metal deposition processes. The individual portions of the conductive layer 242 may be electrically or electrically insulated from each other depending on the connectivity of the individual semiconductor dies. Conductive layer 242 can be one or more layers of aluminum, copper, tin, nickel, gold, silver, or other suitable electrically conductive material.

A resistive layer 244 is patterned and deposited on conductive layer 242b and between conductive layers 242e and 242f using PVD or CVD. The resistive layer 244 is a tantalum crucible (Ta _x Si _y ) or other metal telluride, tantalum nitride (TaN), nickel chromium (NiCr), titanium nitride (TiN) or polycrystalline germanium doped with impurities, which has a resistivity ( Resistivity) is between 5 and 100 ohm/sq. An insulating layer 246 is formed over the resistive layer 244 by PVD, CVD, printing, sintering, or thermal oxidation. The insulating layer 246 may be one or more layers of Si ₃ N ₄ , SiO ₂ , SiON, Ta ₂ O ₅ , ZnO, ZrO ₂ , Al ₂ O ₃ , polyimide, benzocyclobutene (BCB). A laminate of polybenzoxazoles (PBO) or other suitable dielectric material. The resistive layer 244 and the insulating layer 246 may be formed in the same mask and etched simultaneously. Alternatively, the resistive layer 244 and the insulating layer 246 can be patterned and etched with different masks.

An insulating or passivation layer 248 is formed over the resistive layer 244, the insulating layer 246, and the conductive layer 242 by spin coating, PVD, CVD, printing, sintering, or thermal oxidation. Passivation layer 248 can be one or more layers of SiO ₂ , Si ₃ N ₄ , SiON, Ta ₂ O ₅ , Al ₂ O ₃ , or other materials having suitable insulating properties. A portion of the passivation layer 248 is removed to expose the conductive layer 242, the resistive layer 244, and the insulating layer 246.

An electrically conductive layer 252 is patterned and deposited over conductive layer 242, resistive layer 244, insulating layer 246, and passivation layer 248 using PVD, CVD, sputtering, electrolytic plating, electroless plating processes, or other suitable metal deposition processes. To form individual portions or segments, and depending on the connectivity of the individual semiconductor dies, the portions or blocks may be electrically or electrically insulated from each other. Conductive layer 252 can be one or more layers of aluminum, copper, tin, nickel, gold, silver, or other suitable electrically conductive material.

An insulating or passivation layer 254 is formed over conductive layer 252 and insulating layer 248 by spin coating, PVD, CVD, printing, sintering, or thermal oxidation. Passivation layer 254 can be one or more layers of SiO ₂ , Si ₃ N ₄ , SiON, Ta ₂ O ₅ , Al ₂ O ₃ , or other materials having suitable insulating properties. A portion of the passivation layer 254 is removed to expose the conductive layer 252.

The structures described in the proliferation interconnect structure 240 constitute one or more passive circuit components or IPDs. In one embodiment, the conductive layer 242b, the resistive layer 244, the insulating layer 246, and the conductive layer 252 are metal-insulator-metal (MIM) capacitors. The resistive layer 244 interposed between the conductive layers 242e-242f is one of the resistive members in the passive circuit. Individual sections of conductive layer 252 can be wound or wound into a coil on a plane to create or exhibit the properties of an inductor. The above IPD structure provides such as a resonator, a high-pass filter, a low-pass filter, a band-pass filter, a symmetric Hi-Q resonant transformer. Electrical characteristics required for high frequency applications such as (symmetric Hi-Q resonant transformer), matching network, and tuning capacitor. These IPDs can act as front-end wireless RF components that can be placed between an antenna and a transceiver. The inductor can be a hi-Q shell (balun), a transformer, or a coil operating at up to 100 GHz (Gigahertz; billion Hz). In some applications, multiple shellfish are formed on the same substrate to enable multi-band operation. For example, two or more bellows are used in a mobile phone or other global system for mobile (GSM) communication to be responsible for four bands, each dedicated to the operation of one of the four band devices. A typical RF system requires multiple IPDs and other high frequency circuitry in one or more semiconductor packages to perform the required electrical functions.

A plurality of semiconductor dies or components 214 are affixed to the proliferative interconnect structure 240 in a flip chip configuration with the pads 216 facing downwardly over the carrier. The semiconductor die 214 includes an active surface 218 including analog or digital circuits implemented as active components, passive components, conductive layers, and dielectric layers formed within the die, and in accordance with the electrical design and function of the die Electrical interconnection. For example, the circuit can include one or more transistors, diodes, and other circuit components formed in the active surface 218 to implement a base frequency analog circuit or digital circuit, such as a DSP, ASIC, memory, or other signal processing circuit. . Semiconductor die 214 may also include an IPD, such as inductors, capacitors, and resistors for RF signal processing. In another embodiment, a separate semiconductor component is secured to the proliferation interconnect structure 240.

A plurality of stud bumps 220 are formed over the conductive layer 252. The stud bumps 220 are electrically connected to the conductive layer 252 and the pads 216 of the semiconductor die 214.

An encapsulant or molding material 228 is deposited over the semiconductor die 214 and the stud bumps 220 using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, or other suitable coating mechanism. . The encapsulant 228 may be a polymer synthetic material such as an epoxy synthetic resin having a filler, an epoxy acrylate having a filler, or a polymer having a suitable filler. The encapsulant 228 is non-conductive and environmentally protects the semiconductor component from external components and contamination. Encapsulant 228 is subjected to grinding or plasma etching to planarize its surface and expose stud bumps 220.

A top side accretion interconnect structure 230 is formed over encapsulant 228. The hyperplastic interconnect structure 230 includes an insulating or passivation layer 232 formed by PVD, CVD, printing, spin coating, spray coating, sintering, or thermal oxidation. A portion of passivation layer 232 is removed by an etch process to expose stud bumps 220. An electrically conductive layer 234 is formed over the passivation layer 232 and the stud bumps 220. A portion of the conductive layer 234 is electrically connected to the stud bump 220. Other portions of conductive layer 234 may be electrically or electrically insulated from one another depending on the design and function of the semiconductor components. An insulating or passivation layer 236 is formed over the passivation layer 232 and the conductive layer 234. A portion of passivation layer 236 is removed by an etch process to expose conductive layer 234.

The carrier is removed by chemical etching, mechanical stripping, CMP, mechanical milling, thermal baking, laser scanning or wet stripping.

An insulating or passivation layer 258 is formed over conductive layer 242 and insulating layer 248 by spin coating, PVD, CVD, printing, sintering, or thermal oxidation.

Passivation layer 258 can be one or more layers of SiO ₂ , Si ₃ N ₄ , SiON, Ta ₂ O ₅ , Al ₂ O ₃ or other materials having suitable insulating properties. A portion of the passivation layer 258 is removed to expose the conductive layer 242.

An electrically conductive layer 260 is formed over conductive layer 242 by patterning, PVD, CVD, sputtering, electrolytic plating, electroless plating, or other suitable metal deposition process. Conductive layer 260 can be one or more layers of aluminum, copper, tin, nickel, gold, silver, or other suitable electrically conductive material.

An electrically conductive bump material is deposited on the conductive layer 260 by an evaporation, electrolytic plating, electroless plating, solder ball implantation or screen printing process. The bump material can be aluminum, tin, nickel, gold, silver, palladium, rhodium, copper, solder, and combinations of the foregoing, plus a selective flux. For example, the bump material can be eutectic tin/palladium, high lead solder, or lead free solder. The bump material is bonded to the conductive layer 260 using a suitable adhesion or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form spherical solder balls or bumps 262. In some applications, bumps 262 are reflowed a second time to enhance electrical contact with conductive layer 260. The bumps can also be crimped to the conductive layer 260. Bumps 262 represent an interconnect structure type that can be formed on conductive layer 260. The interconnect structure can also use wiring, conductive paste, stud bumps, microbumps, or other electrical connections.

The semiconductor component 210 is stackable. The stud bump 220 provides a vertical z-direction interconnect between the top side accretion interconnect layer 230 and the bottom side accretion interconnect layer 240. The conductive layer 234 is electrically connected to the conductive layer 252 and the pads 216 of the semiconductor die 214 via the stud bumps 220 .

Figure 8 illustrates an embodiment of a vertical interconnect structure having one or more IPDs formed in a topside interconnect structure. Similar to the process illustrated in Figures 3a-3h, the semiconductor component 270 uses a temporary substrate or carrier having a selective interfacial layer that acts as an etch stop layer. An electrically conductive layer 272 is formed over the carrier by patterning, PVD, CVD, sputtering, electrolytic plating, electroless plating, or other suitable metal deposition process. Conductive layer 272 can be a laminate of one or more layers of aluminum, copper, tin, nickel, gold, silver, tungsten, polysilicon or other suitable electrically conductive material. The conductive layer 272 includes a wettable pad to facilitate the formation of subsequent stud bumps.

A plurality of semiconductor dies or components 274 are affixed to the carrier in a flip chip configuration with pads 276 facing downward. The semiconductor die 274 includes an active surface 278 including analog or digital circuits implemented as active components, passive components, conductive layers, and dielectric layers formed within the die, and in accordance with the electrical design and function of the die Electrical interconnection. For example, the circuit can include one or more transistors, diodes, and other circuit components formed in the active surface 278 to implement a base frequency analog circuit or digital circuit, such as a DSP, ASIC, memory, or other signal processing circuit. . Semiconductor die 274 may also include an IPD, such as inductors, capacitors, and resistors for RF signal processing. In another embodiment, a separate semiconductor component is secured to the carrier or interface layer.

A plurality of stud bumps 280 are formed on the wettable pads of the conductive layer 272. An encapsulant or molding material 288 is deposited over the semiconductor die 274 and stud bumps 280 using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, or other suitable coating mechanism. . The encapsulant 288 may be a polymer synthetic material such as an epoxy synthetic resin having a filler, an epoxy acrylate having a filler, or a polymer having a suitable filler. The encapsulant 288 is non-conductive and environmentally protects the semiconductor component from external components and contamination. Encapsulant 288 is subjected to grinding or plasma etching to planarize its surface and expose stud bumps 280.

A top side accretion interconnect structure 290 is formed on one of the first surfaces of encapsulant 288. An insulating or passivation layer 292 is formed over encapsulant 288 and stud bumps 280 by spin coating, PVD, CVD, printing, sintering, or thermal oxidation. The passivation layer 292 may be one or more layers of SiO ₂ , Si ₃ N ₄ , SiON, Ta ₂ O ₅ , Al ₂ O ₃ or other materials having suitable insulating properties. A portion of the passivation layer 292 is removed to expose the stud bumps 280.

An electrically conductive layer 294 is formed over the insulating layer 292 by patterning in conjunction with PVD, CVD, sputtering, electrolytic plating, electroless plating, or other suitable metal deposition process to form individual portions or sections. Individual portions of conductive layer 294 may be electrically or electrically insulated from one another depending on the connectivity of the individual semiconductor dies. Conductive layer 294 can be one or more layers of aluminum, copper, tin, nickel, gold, silver, or other suitable electrically conductive material. A portion of the conductive layer 294 is electrically connected to the stud bump 280. Other portions of conductive layer 294 may be electrically or electrically insulated from each other depending on the design and function of the semiconductor components.

A resistive layer 296 is patterned and deposited over conductive layer 294 and insulating layer 292 using PVD or CVD. The resistive layer 296 is Ta _x Si _y or other metal telluride, tantalum nitride (TaN), nickel chromium (NiCr), titanium nitride (TiN) or polysilicon doped with impurities, and has a resistivity of 5 and 100. Between ohm/sq. An insulating layer 298 is formed over the resistive layer 296 by PVD, CVD, printing, sintering, or thermal oxidation. The insulating layer 298 may be one or more layers of Si ₃ N ₄ , SiO ₂ , SiON, Ta ₂ O ₅ , ZnO, ZrO ₂ , Al ₂ O ₃ , polyimine, BCB, PBO or other suitable dielectric materials. A laminate of the components.

An insulating or passivation layer 300 is formed over the passivation layer 292, the conductive layer 294, the resistive layer 296, and the insulating layer 298 by spin coating, PVD, CVD, printing, sintering, or thermal oxidation. The passivation layer 300 may be one or more layers of SiO ₂ , Si ₃ N ₄ , SiON, Ta ₂ O ₅ , Al ₂ O ₃ or other materials having suitable insulating properties. A portion of the passivation layer 300 is removed to expose the conductive layer 294, the resistive layer 296, and the insulating layer 298.

An electrically conductive layer 302 is patterned and deposited over the passivation layer 300, the conductive layer 294, and the resistive layer 296 by PVD, CVD, sputtering, electrolytic plating, electroless plating, or other suitable metal deposition process to form Individual parts or sections are used for further interconnection. Individual portions of conductive layer 302 may be electrically or electrically insulated from one another depending on the connectivity of the individual semiconductor dies. Conductive layer 302 can be one or more layers of aluminum, copper, tin, nickel, gold, silver, or other suitable electrically conductive material.

An insulating or passivation layer 304 is formed over conductive layer 302 and passivation layer 300 by spin coating, PVD, CVD, printing, sintering, or thermal oxidation. The passivation layer 304 may be one or more layers of SiO ₂ , Si ₃ N ₄ , SiON, Ta ₂ O ₅ , Al ₂ O ₃ or other materials having suitable insulating properties. A portion of the passivation layer 304 is removed to expose the conductive layer 302.

The structures described in the proliferative interconnect structure 290 form one or more passive circuit components or IPDs. In one embodiment, the conductive layer 294, the resistive layer 296, the insulating layer 298, and the conductive layer 302 are a MIM type capacitor. The resistive layer 296 is also a resistive member in a passive circuit. Other individual blocks of conductive layer 302 may be wound or rolled into a coil on a plane to create or exhibit the properties of an inductor.

The carrier and interface layer are removed by chemical etching, mechanical stripping, CMP, mechanical milling, thermal baking, laser scanning or wet stripping. A bottom side growth interconnect structure 310 is formed on a second surface of the encapsulant 288, on the opposite side of the top side growth interconnect structure 290, and on a front side surface of the semiconductor die 274. An electrically conductive layer 312 is formed on the conductive layer 272 and the front side surface of the semiconductor die 274. A portion of the conductive layer 312 is electrically connected to the stud bump 280. Other portions of conductive layer 312 may be electrically or electrically insulated from each other depending on the design and function of the semiconductor components. An insulating or passivation layer 314 is formed on the conductive layer 312 and the front side surface of the semiconductor die 274. A portion of the insulating layer 314 is removed by an etching process to expose the conductive layer 312.

An electrically conductive bump material is deposited over the conductive layer 312 by an evaporation, electrolytic plating, electroless plating, solder ball implantation or screen printing process. The bump material can be aluminum, tin, nickel, gold, silver, palladium, rhodium, copper, solder, and combinations of the foregoing, plus a selective fluxing solvent. For example, the bump material can be eutectic tin/palladium, high lead solder, or lead free solder. The bump material is bonded to the conductive layer 312 using a suitable adhesion or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a spherical tin ball or bump 316. In some applications, bumps 316 are reflowed a second time to enhance electrical contact with conductive layer 312. The bumps can also be crimped to the conductive layer 312. Bump 316 represents an interconnect structure type that can be formed on conductive layer 312. The interconnect structure can also use wiring, conductive paste, stud bumps, microbumps, or other electrical connections.

Semiconductor component 270 is stackable. The stud bump 280 provides a vertical z-direction interconnect between the top side accretion interconnect layer 290 and the bottom side accretion interconnect layer 310. The conductive layers 294 and 302 are electrically connected to the conductive layer 312 and the pads 276 of the semiconductor die 274 via the stud bumps 302.

Figure 9 illustrates an alternate embodiment of a vertical interconnect structure having one or more IPDs formed in the bottom side interconnect structure after packaging. Similar to the process illustrated in Figures 3a-3h, the semiconductor component 320 uses a temporary substrate or carrier having a selective interface layer that acts as an etch stop layer. An electrically conductive layer 322 is formed over the carrier by patterning, PVD, CVD, sputtering, electrolytic plating, electroless plating, or other suitable metal deposition process. Conductive layer 322 can be one or more layers of aluminum, copper, tin, nickel, gold, silver, tungsten, polysilicon or other suitable electrically conductive material. The conductive layer 322 includes a wettable pad to facilitate the formation of subsequent stud bumps.

A plurality of semiconductor dies or components 324 are secured to the carrier in a flip chip configuration with pads 326 facing downward. The semiconductor die 324 includes an active surface 328 including analog or digital circuits implemented as active components, passive components, conductive layers, and dielectric layers formed within the die, and in accordance with the electrical design and function of the die Electrical interconnection. For example, the circuit can include one or more transistors, diodes, and other circuit components formed in the active surface 328 to implement a base frequency analog circuit or digital circuit, such as a DSP, ASIC, memory, or other signal processing circuit. . Semiconductor die 324 may also include an IPD, such as inductors, capacitors, and resistors for RF signal processing. In another embodiment, a separate semiconductor component is secured to the carrier or interface layer.

A plurality of stud bumps 330 are formed on the wettable pads of the conductive layer 322. An encapsulant or molding material 338 is deposited over the semiconductor die 324 and the stud bumps 330 using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, or other suitable coating mechanism. . The encapsulant 338 may be a polymer synthetic material such as an epoxy synthetic resin having a filler, an epoxy acrylate having a filler, or a polymer having a suitable filler. The encapsulant 338 is non-conductive and environmentally protects the semiconductor component from external components and contamination. Encapsulant 338 is subjected to grinding or plasma etching to planarize its surface and expose stud bumps 330.

A top side accretion interconnect structure 340 is formed on one of the first surfaces of the encapsulant 338. The hyperplastic interconnect structure 340 includes an insulating or passivation layer 342 formed by PVD, CVD, printing, spin coating, spray coating, sintering, or thermal oxidation. A portion of passivation layer 342 is removed by an etch process to expose stud bumps 330. An electrically conductive layer 344 is formed over the passivation layer 342 and the stud bumps 330. A portion of the conductive layer 344 is electrically connected to the stud bumps 330. Other portions of conductive layer 344 may be electrically or electrically insulated from each other depending on the design and function of the semiconductor components. An insulating or passivation layer 346 is formed over the passivation layer 342 and the conductive layer 344. A portion of the insulating layer 346 is removed by an etching process to expose the conductive layer 344.

The carrier and interface layer are removed by chemical etching, mechanical stripping, CMP, mechanical milling, thermal baking, laser scanning or wet stripping. A bottom side growth interconnect structure 350 is formed on a second surface of the encapsulant 338, on the opposite side of the top side growth interconnect structure 340, and on a front side surface of the semiconductor die 324. An electrically conductive layer 352 is patterned and deposited using PVD, CVD, sputtering, electrolytic plating, electroless plating processes, or other suitable metal deposition processes. Individual portions of conductive layer 352 may be electrically or electrically insulated from each other depending on the connectivity of the individual semiconductor dies. Conductive layer 352 can be one or more layers of aluminum, copper, tin, nickel, gold, silver, or other suitable electrically conductive material. The conductive layer 352 is electrically connected to the stud bumps 330 and the pads 326 of the semiconductor die 324.

An insulating layer 354 is formed over the conductive layer 352 by PVD, CVD, printing, sintering, or thermal oxidation. The insulating layer 354 may be one or more layers of Si ₃ N ₄ , SiO ₂ , SiON, Ta ₂ O ₅ , ZnO, ZrO ₂ , Al ₂ O ₃ , polyimine, BCB, PBO or other suitable dielectric materials. A laminate of the components.

A resistive layer 356 is patterned and deposited using PVD or CVD. The resistive layer 356 is Ta _x Si _y or other metal telluride, tantalum nitride (TaN), nickel chromium (NiCr), titanium nitride (TiN) or polysilicon doped with impurities, and has a resistivity of 5 and 100. Between ohm/sq.

An insulating or passivation layer 358 is formed over the insulating layer 354, the resistive layer 356, and the conductive layer 352 by spin coating, PVD, CVD, printing, sintering, or thermal oxidation. The passivation layer 358 can be one or more layers of SiO ₂ , Si ₃ N ₄ , SiON, Ta ₂ O ₅ , Al ₂ O ₃ or other materials having suitable insulating properties. A portion of the passivation layer 358 is removed to expose the conductive layer 352, the insulating layer 354, and the resistive layer 356.

An electrically conductive layer 360 is patterned and deposited over conductive layer 352, insulating layer 354, resistive layer 356, and passivation layer 358 using PVD, CVD, sputtering, electrolytic plating, electroless plating processes, or other suitable metal deposition processes. To form individual portions or segments, and depending on the connectivity of the individual semiconductor dies, the portions or segments may be electrically or electrically insulated from each other. Conductive layer 360 can be one or more layers of aluminum, copper, tin, nickel, gold, silver, or other suitable electrically conductive material.

An insulating or passivation layer 362 is formed over conductive layer 360 and insulating layer 358 by spin coating, PVD, CVD, printing, sintering, or thermal oxidation. Passivation layer 362 can be one or more layers of SiO ₂ , Si ₃ N ₄ , SiON, Ta ₂ O ₅ , Al ₂ O ₃ , or other materials having suitable insulating properties. A portion of the passivation layer 362 is removed to expose the conductive layer 360.

The structures described in the proliferation interconnect structure 330 constitute one or more passive circuit components or IPDs. In an embodiment, the conductive layer 352, the insulating layer 354, and the conductive layer 360 are a MIM type capacitor. The resistive layer 356 is a resistive member in a passive circuit. Individual sections of conductive layer 360 may be wound or rolled into a coil on a plane to create or exhibit the properties of an inductor.

An electrically conductive bump material is deposited on the conductive layer 360 by an evaporation, electrolytic plating, electroless plating, solder ball implantation or screen printing process. The bump material can be aluminum, tin, nickel, gold, silver, palladium, rhodium, copper, solder, and combinations of the foregoing, plus a selective flux. For example, the bump material can be eutectic tin/palladium, high lead solder, or lead free solder. The bump material is bonded to the conductive layer 360 using a suitable adhesion or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form spherical solder balls or bumps 364. In some applications, bumps 139 are reflowed a second time to enhance electrical contact with conductive layer 360. The bumps can also be crimped to the conductive layer 360. Bumps 364 represent an interconnect structure type that can be formed on conductive layer 360. The interconnect structure can also use wiring, conductive paste, stud bumps, microbumps, or other electrical connections.

Semiconductor component 320 is stackable. The stud bumps 330 provide a vertical z-direction interconnect between the top side accretion interconnect layer 340 and the bottom side accretion interconnect layer 350. The conductive layer 344 is electrically connected to the conductive layers 352 and 360 and the pads 326 of the semiconductor die 324 via the stud bumps 330.

As shown in Figures 7-9, the IPDs can be formed in one or both of the top side proliferative interconnect structure and the bottom side proliferative interconnect structure.

Although one or more embodiments of the invention are described in detail above, it is to be understood by those skilled in the art that the invention may be modified and modified without departing from the scope of the invention as defined by the appended claims.

50. . . Electronic device

52. . . PCB

54. . . Traces

56. . . Wire bonding package

58. . . Flip chip

60. . . Ball grid array

62. . . Bump wafer carrier

64. . . Double row package

66. . . Substrate grid array

68. . . Multi-chip module

70. . . Four-sided leadless flat package

72. . . Four-sided flat package

74. . . Semiconductor grain

76. . . Pad

78. . . Mediation carrier

80. . . Conductor lead

82. . . Wire bonding

84. . . Encapsulant

88. . . Semiconductor grain

90. . . Carrier

92. . . Underfill or epoxy synthetic resin adhesive material

94. . . Wire bonding

96. . . Pad

98. . . Pad

100. . . Molding material or encapsulant

102. . . Pad

104. . . Bump

106. . . Carrier

108. . . Action area

110. . . Solder bump or solder ball

112. . . Solder bump or solder ball

114. . . Signal line

116. . . Molding material or encapsulant

120. . . Carrier

121. . . Interface layer

122. . . Conductive layer

124. . . Semiconductor die or component

126. . . Pad

128. . . Surface

130. . . Stud bump

132. . . Bump portion

134. . . Bump portion

136. . . Stacked bump

138. . . Encapsulant or molding material

139. . . Bump

140. . . Top side hyperplastic interconnect structure

142. . . Passivation layer

144. . . Conductive layer

146. . . Insulating or passivation layer

150. . . Bottom side hyperplastic interconnect structure

152. . . Conductive layer

154. . . Insulating or passivation layer

156. . . Tin ball or bump

158. . . Saw blade or laser cutting tool

160. . . Semiconductor component

170. . . Semiconductor component

172. . . Conductive layer

174. . . Semiconductor die or component

176. . . Pad

178. . . Surface

180. . . Stud bump

182. . . Stud bump

186. . . wiring

188. . . Encapsulant or molding material

190. . . Top side hyperplastic interconnect structure

192. . . Insulating or passivation layer

194. . . Conductive layer

196. . . Insulating or passivation layer

200. . . Bottom side hyperplastic interconnect structure

202. . . Conductive layer

204. . . Insulating or passivation layer

206. . . Tin ball or bump

210. . . Semiconductor component

214. . . Semiconductor die or component

216. . . Pad

218. . . Surface

220. . . Stud bump

230. . . Top side hyperplastic interconnect structure

232. . . Insulating or passivation layer

234. . . Conductive layer

236. . . Insulating or passivation layer

240. . . Bottom side hyperplastic interconnect structure

242. . . Conductive layer

244. . . Resistance layer

246. . . Insulation

248. . . Insulating or passivation layer

252. . . Conductive layer

254. . . Insulating or passivation layer

258. . . Insulating or passivation layer

260. . . Conductive layer

262. . . Tin ball or bump

270. . . Semiconductor component

272. . . Conductive layer

274. . . Semiconductor die or component

276. . . Pad

278. . . Surface

280. . . Stud bump

288. . . Encapsulant or molding material

290. . . Top side hyperplastic interconnect structure

292. . . Insulating or passivation layer

294. . . Conductive layer

296. . . Resistance layer

298. . . Insulation

300. . . Insulating or passivation layer

302. . . Conductive layer

304. . . Insulating or passivation layer

310. . . Bottom side hyperplastic interconnect structure

312. . . Conductive layer

314. . . Insulating or passivation layer

316. . . Tin ball or bump

320. . . Semiconductor component

322. . . Conductive layer

324. . . Semiconductor die or component

326. . . Pad

328. . . Surface

330. . . Stud bump

338. . . Encapsulant or molding material

340. . . Top side hyperplastic interconnect structure

342. . . Passivation layer

344. . . Conductive layer

346. . . Insulating or passivation layer

350. . . Bottom side hyperplastic interconnect structure

352. . . Conductive layer

354. . . Insulation

356. . . Resistance layer

358. . . Passivation layer

360. . . Conductive layer

362. . . Insulating or passivation layer

364. . . Tin ball or bump

Figure 1 illustrates a PCB having a different type of package secured to its surface;

Figures 2a-2c illustrate further details of a representative semiconductor package affixed to the PCB;

3a-3h illustrate a process for forming a vertical interconnect structure using stud bumps;

4 illustrates a semiconductor component including a vertical interconnect structure having stud bumps;

Figure 5 illustrates a stacked semiconductor device electrically interconnected with stud bumps;

6 illustrates a semiconductor element having a stud bump and a die having an active surface facing upward;

Figure 7 illustrates a semiconductor component having an IPD formed in a bottom side interconnect structure;

Figure 8 illustrates a semiconductor component having an IPD formed in a top side interconnect structure;

Figure 9 illustrates another embodiment of a semiconductor component having an IPD formed in a bottom side interconnect structure.

122. . . Conductive layer

124. . . Semiconductor die or component

126. . . Pad

128. . . Surface

130. . . Stud bump

138. . . Encapsulant or molding material

140. . . Top side hyperplastic interconnect structure

142. . . Passivation layer

144. . . Conductive layer

146. . . Insulating or passivation layer

150. . . Bottom side hyperplastic interconnect structure

152. . . Conductive layer

154. . . Insulating or passivation layer

156. . . Tin ball or bump

160. . . Semiconductor component

Claims (15)

A method of fabricating a semiconductor device, comprising: providing a semiconductor die or component; providing a conductive layer comprising a wettable pad; forming a stud bump on the wettable pad; depositing a package And on the semiconductor die or assembly and around the stud bump; forming a first interconnect structure on a first surface of the encapsulant, the first interconnect structure comprising a first integrated passive component ( And being electrically connected to the stud bump; and forming a second interconnect structure on a second surface of one of the encapsulants on the opposite side of the first interconnect structure. The method of claim 1, wherein the stud bump comprises a plurality of stacked bumps. The method of claim 1, wherein the height of one of the stud bumps is less than a thickness of the semiconductor die or component. The method of claim 1, further comprising: stacking the plurality of semiconductor components; and electrically connecting the plurality of semiconductor components via the stud bumps. The method of claim 1, wherein the semiconductor die or component comprises a flip-chip semiconductor die having an active surface facing the second interconnect structure. A method of fabricating a semiconductor device, comprising: providing a semiconductor die or component; Providing a vertical interconnect structure; depositing an encapsulant on the semiconductor die or component and the vertical interconnect structure; forming a first interconnect structure on a first surface of the encapsulant; and forming a second The interconnect structure is on a second surface of one of the encapsulants on the opposite side of the first interconnect structure. The method of claim 6, wherein the first interconnect structure comprises an integrated passive component. The method of claim 6, wherein the second interconnect structure comprises an integrated passive component. The method of claim 6, wherein the vertical interconnect structure comprises a bump portion and a stud portion. The method of claim 6, further comprising: stacking a plurality of semiconductor elements; and electrically electrically stacking the stacked semiconductor elements via the first interconnect structure, the second interconnect structure, and the vertical interconnect structure Sexual connection. A semiconductor component comprising: a semiconductor die or component; a conductive layer comprising a wettable pad; a vertical interconnect structure formed over the wettable pad; an encapsulant deposited on Forming on the semiconductor die or component and the vertical interconnect structure; and a first interconnect structure on a first surface of the encapsulant, The first interconnect structure includes a first integrated passive component (IPD). The semiconductor device of claim 11, further comprising a second interconnect structure formed on a second surface of the encapsulant on the opposite side of the first interconnect structure. The semiconductor component of claim 12, wherein the second interconnect structure comprises a second IPD. The semiconductor device of claim 11, wherein the vertical interconnect structure comprises a bump portion and a pillar portion or a plurality of stacked bumps. The semiconductor component of claim 11, further comprising a plurality of stacked semiconductor components electrically connected to each other through the vertical interconnect structure.