TWI506737B - A manufacturing method of an electronic device package, an electronic device package, and an oscillator - Google Patents
A manufacturing method of an electronic device package, an electronic device package, and an oscillator Download PDFInfo
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- TWI506737B TWI506737B TW100109555A TW100109555A TWI506737B TW I506737 B TWI506737 B TW I506737B TW 100109555 A TW100109555 A TW 100109555A TW 100109555 A TW100109555 A TW 100109555A TW I506737 B TWI506737 B TW I506737B
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- electronic device
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- base substrate
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- device package
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- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 239000000758 substrate Substances 0.000 claims description 185
- 229910052751 metal Inorganic materials 0.000 claims description 60
- 239000002184 metal Substances 0.000 claims description 60
- 238000000034 method Methods 0.000 claims description 22
- 239000000463 material Substances 0.000 claims description 16
- 239000012212 insulator Substances 0.000 claims description 6
- 229910052804 chromium Inorganic materials 0.000 claims description 5
- 239000011651 chromium Substances 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical group [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 229910052707 ruthenium Inorganic materials 0.000 claims description 2
- 229910052718 tin Inorganic materials 0.000 claims description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 1
- 239000011521 glass Substances 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 239000011135 tin Substances 0.000 claims 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims 1
- 239000010937 tungsten Substances 0.000 claims 1
- 229910052799 carbon Inorganic materials 0.000 description 8
- 239000005361 soda-lime glass Substances 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000005496 eutectics Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910015363 Au—Sn Inorganic materials 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
- H03H9/05—Holders; Supports
- H03H9/10—Mounting in enclosures
- H03H9/1007—Mounting in enclosures for bulk acoustic wave [BAW] devices
- H03H9/1014—Mounting in enclosures for bulk acoustic wave [BAW] devices the enclosure being defined by a frame built on a substrate and a cap, the frame having no mechanical contact with the BAW device
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
- H03H9/05—Holders; Supports
- H03H9/10—Mounting in enclosures
- H03H9/1064—Mounting in enclosures for surface acoustic wave [SAW] devices
- H03H9/1071—Mounting in enclosures for surface acoustic wave [SAW] devices the enclosure being defined by a frame built on a substrate and a cap, the frame having no mechanical contact with the SAW device
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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- Engineering & Computer Science (AREA)
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- General Physics & Mathematics (AREA)
- Acoustics & Sound (AREA)
- Manufacturing & Machinery (AREA)
- Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
- Oscillators With Electromechanical Resonators (AREA)
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Description
本發明係關於電子裝置被密封於形成在接合的兩片基板之間之空腔內的表面安裝型(SMD)之封裝體。尤其針對用以陽極接合兩片基板之構造予以提案。
近年來,行動電話或攜帶資訊終端機器以使用利用表面安裝型之小型封裝體之電子裝置為多。其中,大多以振動子或MEMS、陀螺儀感應器、加速度感應器等,中空之空腔構造之封裝體為必要零件。中空空腔構造之封裝體所知的有經金屬膜接合基座基板和蓋基板的構造。再者,接合方法所知的也有共晶接合、縫接合、陽極接合(參照日本專利文獻1)
在此,針對以往經金屬膜使基座基板和蓋基板陽極接合之封裝體之製造方法予以說明。尤其,針對多數之封裝體要素陣列狀地形成於一片薄板狀之基座基板上,且於將蓋基板接合於基座基板之後分割成一個一個封裝體之製造方法予以說明。
如第7圖所示般,以往之電子裝置封裝體係由電子裝置47、形成平板狀之基座基板41、形成凹部之蓋基板42,和用以接合基座基板41和蓋基板42之接合膜的金屬膜49所構成。藉由在蓋基板42形成凹部,並以蓋基板42密封基座基板41而構成空腔46。電子裝置47係被收納在空腔46內。
基座基板41係由絕緣物、半導體或是金屬所構成,形成平板狀。因應安裝之電子裝置47之數量在基座基板41之表面形成用以安裝電子裝置47之配線43,在基座基板41之對應的背面,形成外部電極45。為了連接基座基板41之表面之配線43和背面之外部電極45,在封裝體之任意部位形成貫通孔及掩埋此之貫通電極44,經貫通電極44連接配線43和外部電極45。
蓋基板42係由絕緣物、半導體或是金屬所構成,形成具有凹部。於基座基板41和蓋基板42被接合而形成空腔46之時,在基座基板41和蓋基板42相接之部分形成有當作接合膜之金屬膜49。原本若僅在基座基板41和蓋基板42相接之部分形成金屬膜49亦可,但是於考慮工程之簡化之時,則如第7圖(B)所示般,在蓋基板42之單面全面形成金屬膜49。
針對製造方法予以說明。以可以在晶圓狀之蓋基板42安裝多數電子裝置47之方式,形成多數凹型之空腔46(第7圖(A)),之後在蓋基板42之單面上形成當作接合膜之金屬膜49(第7圖(B))。適合作為該金屬膜49的有鋁、鉻、矽、銅等。在晶圓狀之基座基板41形成用以安裝多數電子裝置47之配線43和外部電極45和貫通電極44(第7圖(C))。接著在基座基板41上安裝電子裝置47,並以藉由打線接合之接線48連接電子裝置47和配線43(第7圖(D))。
然後,對準基座基板41和蓋基板42而予以重疊,進行接合。在接合中,如第7圖(E)所示般,以兼加熱器電極之基板50、51夾著被對準之基座基板41和蓋基板42。然後,以接觸於金屬膜49之方式設置正極探針52,並使兼加熱器電極之基板50、51之溫度上升,而對正極探針52和兼加熱器電極之基板50之間施加電壓,依此經金屬膜49而接合基座基板41和蓋基板42。之後以切割裝置等將封裝體要素切斷成各個,完成各個電子裝置封裝體。
[專利文獻1]日本特開平09-002845號公報
但是,在以往之電子裝置封裝體之製造方法殘留有以下課題。首先,在蓋基板42之一方之面上形成多數成為空腔46之凹部,於薄化蓋基板42之時,因蓋基板42之一方之面和另一方之面的形狀有差異,故有蓋基板42變形較大之課題。因此,採用增厚形成在蓋基板42中形成有凹部之面上的金屬膜49之厚度,來抑制變形之對策。但是,當增加金屬膜49之膜厚時,則有金屬膜49和基座基板41之接合強度下降之課題。
本發明係鑒於如此之情形而研究出,其目的在於提供即使薄化在基板之一方之面和另一方之面薄化表面形狀不同之基板之時,亦可以將基板之變形抑制成最小,經金屬膜安定性接合基座基板和蓋基板之電子裝置封裝體。
與本發明有關之電子裝置封裝體之製造方法,該電子裝置封裝體具備:基座基板;蓋基板,其係在與上述基座基板對向之狀態下被接合於該基座基板;和電子裝置,其係被收納於多數形成在上述基座基板和上述蓋基板之間的空腔內之各個,並且被安裝在上述基座基板上,該電子裝置封裝體之製造方法具備:在上述蓋基板之一方之面上形成成為空腔之凹部的工程;在上述蓋基板之另一方之面上形成第一金屬膜之工程;在上述蓋基板之一方之面上形成第二金屬膜之工程;和經上述第二金屬膜接合上述基座基板和上述蓋基板之工程。
若藉由與本發明有關之電子裝置封裝體之製造方法時,即使在與蓋基板中形成有凹部之面相反之面上也形成金屬膜。因此,即使蓋基板成為非常薄,該金屬膜亦發揮防止蓋基板之變形之功效,有於接合基座基板和蓋基板之時,可以將蓋基板之變形抑制成非常小之效果。並且,因在與該蓋基板中接合於基座基板之面相反之面上形成金屬膜,故有可以在該金屬膜刻印產品之辨識號碼之效果。至今,蓋基板為絕緣物之時,要在與蓋基板中接合於基座基板之面相反之面上刻印產品之辨識號碼相當得困難。
以下,參照第1圖至第5圖說明與本發明有關之實施型態。本實施型態之電子裝置封裝體1係如第1圖及第2圖所示般,基座基板2和蓋基板3被形成疊層兩層之箱狀,為在內部之空腔5內收納電子裝置4之表面安裝型封裝體。電子裝置4為LSI或MEMS、感測器、壓電振動子或是其複合體。
基座基板2及蓋基板3皆由絕緣物、半導體、金屬或其複合材料所構成,在本實施型態中為由例如鈉鈣玻璃所構成之絕緣物。在第1圖及第2圖所示之例中,在蓋基板3中接合基座基板2之接合面側,形成有成為收納電子裝置4之空腔5的矩形狀之凹部,基座基板2形成平板狀。凹部5係於重疊兩基板2、3之時,成為收納電子裝置4之空腔5的凹部。然後,蓋基板3係在使該凹部5對向於基座基板2側之狀態下,經為接合膜之金屬膜7而對該基座基板2接合。
如第2圖所示般,為了電性連接電子裝置4和外部電極11,貫通電極10被形成基座基板2。用以使貫通電極10貫通之貫通孔,係被形成在空腔5內開口。在第2圖中,雖然貫通孔係以一面維持大略一定之直徑,一面筆直貫通基座基板2之貫穿孔為例而予以說明,但是並不限定於此情形,即使形成例如朝向基座基板2之下面而逐漸縮徑之錐形狀亦可。無論哪一種,若貫通基座基板2即可。
然後,在貫通孔以掩埋該貫通孔之方式形成貫通電極10。該貫通電極10係完全堵塞貫通孔而維持空腔5內之氣密,並且擔任電性導通外部電極11和電子裝置4之任務。貫通孔和貫通電極10之間隙使用無機材料或有機材料等使基座基板2配合熱膨脹係數之材料而被完全堵塞。
接著,針對與本發明有關之一實施型態之電子裝置封裝體之製造方法,參照第3圖之流程工程圖、第4及第5圖而予以說明。
首先,針對基座基板2,研磨蝕刻晶圓狀之絕緣基板使成為目的之厚度,進行洗淨(S10)。接著,在基座基板2形成貫通孔(S11)。針對貫通孔之形成方法,則不論藉由光微影之蝕刻的形成或藉由壓製加工的形成等之方法。然後,形成用以在基座基板2上安裝電子裝置4之配線9(S12)。接著,在被形成在基座基板2之貫通孔形成貫通電極10(S13)。並且,在與基座基板2上之配線9之面相反之面上形成外部電極11(S14)。被形成至外部電極11之基座基板2則被表示於第4圖(E)。
另外,針對蓋基板3,如第4圖(A)所示般,研磨蝕刻晶圓狀之絕緣基板使成為目的之厚度,進行洗淨(S20)。接著,如第4圖(B)所示般,在平板狀之蓋基板3形成成為空腔5之凹部(S21)。針對凹部之形成方法,則不論藉由光微影之蝕刻的形成或藉由壓製加工的形成等之方法。接著,如第4圖(C)所示般,在與蓋基板3中形成有凹部之面相反之面全面上形成有用以防止晶圓變形之第一金屬膜6(S22)。就以第一金屬膜6之形成方法而言,使用蒸鍍法或濺鍍法、CVD法等。第一金屬膜6使用線膨脹係數小於蓋基板3所使用之材料的材料。例如,於蓋基板3使用鈉鈣玻璃之時,第一金屬膜6使用Si、Cr、W或該些之組合等,其厚度被設定在200~2000之範圍。鈉鈣玻璃之線膨脹係數為9~10×10-6
/℃,對此Si為2.8~7.3×10-6
/℃,Cr為6.2×10-6
/℃,W為4.3×10-6
/℃
接著,如第4圖(D)所示般,在蓋基板3中形成有凹部之面全面上形成當作接合膜之第二金屬膜7(S23)。就以形成之方法而言,同樣使用蒸鍍法或濺鍍法、CVD法等而形成。第二金屬膜7盡可能使用線膨脹係數大於蓋基板3所使用之材料的材料。例如,於蓋基板3使用鈉鈣玻璃之時,第二金屬膜7使用Al、Ni、Au-Sn、Cu等,其厚度被設定在200~2000之範圍。但是,第二金屬膜7不一定要局限於線膨脹係數大於蓋基板3所使用之材料的材料,即使對鈉鈣玻璃之蓋基板3使用Si、Cr、W亦可。Al之線膨脹係數為23.9×10-6
/℃、Ni為13×10-6
/℃、Au為14.2×10-6
/℃、Sn為23×10-6
/℃、Cu為13×10-6
/℃。在此,形成在蓋基板3中形成有凹部之面上的第二金屬膜7之材料,以藉由蓋基板3和基座基板2之接合方法而選擇為優先。假設,第二金屬膜7之線膨脹係數小於蓋基板3所使用之材料小時,當增加形成在與蓋基板3中形成有凹部之面相反之面上的第一金屬膜6之厚度時,則減少當作晶圓之蓋基板3之變形。
然後,如第4圖(F)所示般,將電子裝置4安裝在基座基板2上(S30)。在第4圖中,雖然以使用接線8之打線接合連接配線9和電子裝置4,但是不一定要限定於該工法,若為覆晶接合或焊接等,確保電導通之連接工法即可。
將金屬膜6、7之膜厚設為200~2000之範圍係取決於膜形成之安定性及接合強度之關係。膜厚低於200,因蓋基板3之材料和金屬膜6、7之密接強度弱,故為了確保接合強度,必須為200以上之膜厚。另外,設為2000以上之膜厚時,由於基座基板2和蓋基板3之接合強度藉由膜之分子間結合力被左右,故接合強度下降。
接著,在經第二金屬膜7之狀態下接合安裝有電子裝置4之狀態的基座基板2和形成有第一金屬膜6之蓋基板3(S31)。在此,在第4圖及第5圖所示之例中,基座基板2係被形成可對蓋基板3重疊之大小。
基座基板2和蓋基板3之接合方法係藉由基座基板2及蓋基板3之各個之構成材料和第二金屬膜7之種類而被選擇。例如,基座基板2及蓋基板3皆以鈉鈣玻璃構成之時,合適之接合方法可舉出陽極接合。第5圖(A)係表示以陽極接合接合基座基板2和蓋基板3之情形。在陽極接合中,首先對準蓋基板3和基座基板2而予以重疊。接著,使以碳等所形成之負電極板21接觸於與基座基板2中與蓋基板3接合之面相反之面全面上,使以碳等所形成之正電極板22接觸於與蓋基板3中與基座基板2接合之面相反之面全面上。並且,在正電極板22和負電極板21之間施加一定之荷重。在該狀態下,以加熱器等將正電極板22、負電極板21、基座基板2及蓋基板3加熱至200~300℃,對正電極板22和負電極板21之間施加500~1000V之電壓而陽極接合基座基板2和蓋基板3。
在第5圖(A)之狀態下,在接合晶圓狀之基座基板2和晶圓狀之蓋基板3而所構成之一片晶圓內存在多數電子裝置封裝體要素。在此,如第5圖(B)所示般,使用鑽石輪劃片機或線鋸,將電子裝置封裝體1切斷成個別(S32)。第2圖表示將電子裝置封裝體1切斷成個別之狀態的剖面圖。之後,藉由進行內部之電特性檢查,製造電子裝置封裝體1(S33)。
在此,針對陽極接合基座基板2和蓋基板3之效果予以說明。至此使用陶瓷基板之基座基板中,必須對一個一個電子裝置接合蓋。因此,於基座基板和蓋接合時,在基座基板承受大的壓力,當接合面之寬度小時,則無法承受壓力,有產生破裂或缺陷之課題。本實施型態之電子裝置封裝體1因基座基板2和蓋基板3之接合使用陽極接合,故可以同時安裝多數電子裝置4。因此,接合時被施加於一個一個基座基板之壓力變小,即使接合面變小也不會產生破裂或缺陷。因此,對於製作小型化之封裝體非常有效。
並且,本發明之技術範圍並不限定於上述實施形態,只要在不脫離本發明之主旨的範圍,亦可以作各種變更。在上述例中,雖然說明基座基板2及蓋基板3皆由鈉鈣玻璃所構成,以陽極接合接合基座基板2和蓋基板3之例,但是並不限定於此,例如即使為藉由熔接經金屬膜7接合基座基板2和蓋基板3之情形或共晶接合亦可。
接著,針對本發明所涉及之振盪器之一實施型態,一面參照第6圖一面予以說明。本實施形態之振盪器100係如第6圖所示般,將使用當作電子裝置4之例如由水晶所構成之壓電振動片的電子裝置封裝體1(壓電振動子),構成當作被電性連接於積體電路101之振盪子。該振盪器100具備有安裝電容器等之電子零件102之基板103。在基板103安裝有振盪器用之上述積體電路101,在該積體電路101之附近,安裝有電子裝置封裝體1(壓電振動子)。該些電子零件102、積體電路101及電子裝置封裝體1(壓電振動子)係藉由無圖示之配線圖案分別被電性連接。並且,各構成零件係藉由無圖示之樹脂而模製。
在如此構成之振動器100中,當對壓電振動子施加電壓時,該壓電振動子內之壓電振動片則振動。該振動係藉由壓電振動片具有之壓電特性變換成電訊號,當作電訊號被輸入至積體電路101。被輸入之電訊號藉由積體電路101被施予各種處理,當作頻率訊號被輸出。依此,壓電振動子當作振盪子而發揮功能。再者,可以將積體電路101之構成,藉由因應要求選擇性設定例如RTC(即時鐘)模組等,附加除控制時鐘用單功能振盪器等之外,亦可以控制該機器或外部機器之動作日或時刻,或提供時刻或日曆等之功能。
1...電子裝置封裝體
2...基座基板
3...頂蓋基板
4...電子裝置
5...空腔
6...第一金屬膜(防止變形)
7...第二金屬膜(接合膜)
8...接線
9...配線
10...貫通電極
11...外部電極
21...負電極板
22...正電極板
第1圖為表示與本發明有關之電子裝置封裝體之一實施型態的斜視圖。
第2圖為表示與本發明有關之電子裝置封裝體之一實施型態的剖面圖。
第3圖為表示與本發明有關之電子裝置封裝體之製造方法之一實施型態的流程圖。
第4圖為表示與本發明有關之電子裝置封裝體之製造方法之一實施型態的剖面工程圖。
第5圖為表示與本發明有關之電子裝置封裝體之製造方法之一實施型態的剖面工程圖。
第6圖為表示與本發明有關之振盪器之一實施型態的圖示。
第7圖為以往之電子裝置封裝體之剖面圖工程圖。
1...電子裝置封裝體
2...基座基板
3...頂蓋基板
6...第一金屬膜(防止變形)
7...第二金屬膜(接合膜)
21...負電極板
22...正電極板
Claims (10)
- 一種電子裝置封裝體之製造方法,該電子裝置封裝體具備:基座基板;蓋基板,其係在與上述基座基板對向之狀態下被接合於該基座基板;和電子裝置,其係被收納於多數形成在上述基座基板和上述蓋基板之間的空腔內之各個,並且被安裝在上述基座基板上,該電子裝置封裝體之製造方法具備:在上述蓋基板之一方之面上形成成為上述空腔之凹部的工程;在上述蓋基板之另一方之面上形成由線膨脹係數較上述蓋基板小之材料所構成的第一金屬膜之工程;在上述蓋基板之一方之面上形成第二金屬膜之工程;和經上述第二金屬膜接合上述基座基板和上述蓋基板之工程。
- 如申請專利範圍第1項所記載之電子裝置封裝體之製造方法,其中較上述第二金屬膜之前形成上述第一金屬膜。
- 如申請專利範圍第1或2項所記載之電子裝置封裝體之製造方法,其中上述第一金屬膜和上述第二金屬膜由互相不同之材料所構成。
- 如申請專利範圍第1項所記載之電子裝置封裝體之製造方法,其中 上述第一金屬膜為矽、鉻、鎢或該些組合。
- 如申請專利範圍第1或2項所記載之電子裝置封裝體之製造方法,其中上述第二金屬膜係由線膨脹係數較上述蓋基板大之材料所構成。
- 如申請專利範圍第5項所記載之電子裝置封裝體之製造方法,其中上述第二金屬膜為鋁、銅、金、鎳、錫或該些組合。
- 如申請專利範圍第1或2項所記載之電子裝置封裝體之製造方法,其中上述第一及第二金屬膜之膜厚被設定成200Å~2000Å之範圍。
- 如申請專利範圍第1或2項所記載之電子裝置封裝體之製造方法,其中上述蓋基板為由玻璃材料所構成之絕緣物。
- 一種電子裝置封裝體,具備:基座基板;蓋基板,其係在一方之面上形成凹部,並且形成第二金屬膜,在另一方之面上形成第一金屬膜,藉由在使上述凹部與上述基座基板對向之狀態下經上述第二金屬膜而接合於上述基座基板,而在與上述基座基板之間形成空腔;和電子裝置,其係被收納於上述空腔內並且被安裝在上述基座基板上, 上述第一金屬膜係使用線膨脹係數較上述蓋基板小之材料而形成。
- 一種振盪器,具備:如申請專利範圍第9項所記載之電子裝置封裝體,上述電子裝置為壓電振動片;和上述電子裝置封裝體作為振盪子而被電性連接的積體電路。
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JPWO2012017888A1 (ja) * | 2010-08-04 | 2013-10-03 | 株式会社村田製作所 | 電子部品の製造方法および電子部品 |
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JP5538974B2 (ja) | 2014-07-02 |
US20110233694A1 (en) | 2011-09-29 |
KR20110108290A (ko) | 2011-10-05 |
KR101872518B1 (ko) | 2018-06-28 |
EP2390908A3 (en) | 2014-01-01 |
CN102254836A (zh) | 2011-11-23 |
US8530986B2 (en) | 2013-09-10 |
CN102254836B (zh) | 2015-08-05 |
EP2390908A2 (en) | 2011-11-30 |
JP2011205033A (ja) | 2011-10-13 |
TW201203471A (en) | 2012-01-16 |
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