1355723 九、發明說明： " 【發明所屬之技術領域】 本發明係關於一種晶片尺寸級封裝體，特別是關於一 種散熱增益型晶片尺寸級封裝體（heat spreader chip scale package )° • 【先前技術】 •晶片封裝技術在半導體製程中扮演著一個重要的角 色。由於晶片在運作時，電流通過具有電阻等的元件會產 生大量的熱’於是晶片的散熱便成為一個重要的課題。隨 著半導體元件中積體電路元件的堆積密度（packing density)上升，晶片在運作時所產生的熱能也越來越大。 籲 在現行的晶片封裝技術中，通常會在已封裝完成的晶 片上增加散熱裝置，以增進晶片的散熱效率並確保晶片的 正常運作。然而這種外加散熱裝置的模式，在晶片速度不 斷快速提昇的趨勢下，已越來越難以應付晶片在運作時所 : 產生的熱能’而且在每一個已完成封裝的晶片上裝設一個 • 散熱裝置’其程序也相當地複雜非常耗費成本。展望下一 個世代的晶片，這種外加散熱裝置的模式將無法滿足未來 晶片的散熱需求。 6 1355723 【發明内容】 本發明於是提出—種散熱增益型W尺寸級封裝體。 • j晶片封裝時’即—併將散熱元件内建在晶片封裝體中。 &種解决方式不但簡化了原本封裝晶片與裝置散熱元件分 進行的製程，更具有前瞻性解決未來晶片散熱問題的優 點。 鲁 本發明的散熱増益型晶片尺寸級封裝體’包含具有主 動表面與背面之晶粒、包圍背面並暴露出主動表面之散熱 片以及覆蓋背面與散熱片並暴露出主動表面之封膠體。 本發明又揭示一種形成散熱增益型晶片尺寸級封裝體 的方法。首先，複數個晶粒獨立黏於具有選擇黏性的載體 上，並使得各晶粒之主動表面與載體相接觸。其次，將散 熱裝置覆蓋但不接觸複數個晶粒，散熱裝置包含對應複數 Φ 個晶粒之複數個散熱件（heat spreader )。然後，使用封膠 體以壓模（molding)的方式密封晶粒之背面以及散熱件。接 著，切割散熱件以成為複數個單位封裝體，各單位封裝體 . 均包含一晶粒與一散熱片（heat sink )。以及，去除各單位 4 封裝體之載體部分，以形成所欲之散熱增益型晶片尺寸級 封裝體。 ' 【實施方式】 7 1355723 本發明散熱增益型晶片尺寸級封裝體的好處在於，在 晶片封裝時，即一併將散熱元件内建在晶片封裝體中。這 種解決方式不但簡化了原本封裝晶片與裝置散熱元件分開 進行的製程，更具有前瞻性解決未來晶片散熱問題與生產 快、時間短的優點。 第1圖例示本發明散熱增益型晶片尺寸級封裝體一較 佳實施例。散熱增益型晶片尺寸級封裝體100包含至少一 晶粒110、一散熱片120與一封膠體130。晶粒110具有一 主動表面111與一背面112，背面112被散熱片120所包 圍，但是主動表面111則暴露在散熱片120之外。晶粒110 可以是任何經過適當切割後的半導體晶片。一般說來，散 熱片120可包含高導熱的材料，以增進散熱效率，例如銅、 在呂等金屬或非金屬材料。 覆蓋住晶粒Π0背面112與散熱片120的封膠體130 暴露出晶粒110的主動表面，以方便日後電連接使用。雖 然裸晶的散熱效果良好，但容易受到環境的影響與破壞， 因此本發明係使用封膠體130來保護晶粒110，並藉以黏 著固定晶粒110與散熱片120。封膠體130通常是一種導 熱性良好的模封材料，例如環氧樹脂模封材料（epoxy molding compound，EMC)等0 1355723 為了方便日後的使用，主動表面111較佳可以包含至 少一焊塾(pads)、凸塊(bumps)等各式輸出入(I/O)端點（圖 未示），作為電連接之用。或是為了切割方便，主動表面 111可以視情況需要先用一具有黏性的載體140封起來，俟 切割完成後再予移除。 散熱片120的形狀可以呈梯形或帽形，使得背面112 被散熱片120所包圍。視情況需要，封膠體130不一定要 將散熱片120完全覆蓋。例如，當散熱片120具有頂部121 與延伸部122時，封膠體130可以只覆蓋延伸部122 ’而不 覆蓋頂部121之上表面。此外，散熱片120的表面亦可以設 置有複數個凹槽、突起、刻痕、粗糙面、開孔等之散熱圖 案來增加散熱片120的散熱面積，並提高封膠體130對於 散熱片120的黏附效果。 第2-6圖例示本發明形成散熱增益型晶片尺寸級封裝 體方法的一較佳實施例。本發明形成散熱增益型晶片尺寸 級封裝體方法，首先將複數個晶粒210獨立黏於具有選擇 黏性的載體240上。其中，這些經過切割的晶粒210均具 有一主動表面211與一背面212，而且在將晶粒210黏於 載體240上時，係使得各晶粒210之主動表面211接觸載 體 240 〇 9 1355723 為了方便日後的使用，主動表面211可以包含至少一 焊墊、凸塊等各式輸出入(I/O)端點（圖未示），作為電連接 之用。載體240可以包含複合層結構，例如黏膠與剛性基 材或黏膝與捲帶（tape)。黏膠可以具有選擇的點性，並在·一 適當條件下失去黏性，例如使用曝光或加熱等方式。一般 而言，剛性基材可以是玻璃、矽、金屬等等材料。 其次，如第3圖所示，將散熱裝置220覆蓋但不接觸 複數個晶粒210。散熱裝置220係包含對應複數個晶粒210 之複數個散熱件（heat spreader) 226。一般說來，散熱裝 置220可包含高導熱的材料，以增進散熱效率，例如銅、 鋁等金屬或非金屬材料。此外，每一個散熱件226的表面 皆可以設置有複數個凹槽、突起、刻痕、粗糙面、開孔等 之散熱圖案來增加散熱面積並提高黏著面積。 之後，如第4圖所示，將封膠體230以壓模（molding) 方式填充於散熱件2 2 6與晶粒210間的空隙中與散熱件2 2 6 的四周，以密封晶粒210之背面212並將散熱件226與晶 粒210固定在一起。雖然裸晶的散熱效果良好，但容易受 到環境的影響與破壞，因此使用封膠體230來保護晶粒 210。封膠體230通常是一種導熱性良好的模封材料，例如 環氣樹脂模封材料（epoxy molding compound，EMC)等。 1355723 .接著，如第5圖所示，切 位封裝體，其巾各單位料體咖件2=成|為各別單 210與一散熱片22〇,散熱片220的形狀可以呈;晶教 形。此時，散熱片220會具有 罘形或帽 使得背面212被散熱片220戶斤包圍。視情況需要^ 23〇不一定要將散熱片22〇完 是隋况而要，封膠體 -Τ 復盖。例如，封膠體 可以只覆蓋延伸部222,而不覆蓋頂部221之上^ 切割後，如第6圖所示，即可去除單位封裳 Γ體部分，而絲以動表面川㈣成賴增益^ 曰曰片尺寸級封裝體201。如前所述，_可以具有選擇的 黏性，因此可以適當騎使_失去純，方 除單位封裝體200之載體部分24〇。 由於本發明散熱增益型晶片尺寸級封裝體在晶片封裝 時，即—併將散熱元件内建在晶片封裝體中，這種解決方' 式不但簡化了原本封裝晶片與裝置散熱元件分開進行的製 私，更具有前瞻性解決未來晶片散熱問題與生產快、時間 短的優點。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 1355723 【圖式簡單說明】 第1圖例示本發明散熱增益型晶片尺寸級封裝體一較 佳實施例。 第2-6圖例不本發明形成散熱增益型晶片尺寸級封裝 體方法的一較佳實施例。 【主要元件符號說明】 100散熱增益型晶片尺寸級封裝體 110晶粒 112背面 130.封膠體 200單位封裝體 211主動表面 220散熱片 222延伸部 230封膠體 111主動表面 120散熱片 140載體 210晶粒 212背面 221頂部 226散熱件 240載體 121355723 IX. DESCRIPTION OF THE INVENTION: 1. TECHNICAL FIELD The present invention relates to a wafer size package, and more particularly to a heat spreader chip scale package. 】 • Wafer packaging technology plays an important role in semiconductor manufacturing. Since the current is passed through an element having a resistance or the like during the operation of the wafer, a large amount of heat is generated, and heat dissipation of the wafer becomes an important issue. As the packing density of the integrated circuit components in the semiconductor device rises, the heat generated by the wafer during operation is also increased. In the current chip packaging technology, heat sinks are usually added to the packaged wafer to improve the heat dissipation efficiency of the wafer and ensure the normal operation of the wafer. However, this mode of external heat sink, in the trend of increasing wafer speed, has become more and more difficult to cope with the heat generated during the operation of the wafer' and to install one on each wafer that has been packaged. The device 'its program is also quite complex and very costly. Looking ahead to the next generation of chips, this mode of external heat sinks will not meet the cooling needs of future chips. 6 1355723 SUMMARY OF THE INVENTION The present invention thus proposes a heat dissipation gain type W size package. • When the j chip is packaged, ie, the heat dissipating component is built into the chip package. The & solution not only simplifies the process of packaging the wafer and the device's heat dissipating components, but also promising the advantages of future chip thermal issues. The heat-dissipating wafer size package of the present invention comprises a die having a main surface and a back surface, a heat sink surrounding the back surface and exposing the active surface, and a seal covering the back surface and the heat sink and exposing the active surface. The present invention further discloses a method of forming a heat dissipation gain type wafer size package. First, a plurality of grains are independently adhered to a carrier having a selective viscosity, and the active surfaces of the respective grains are brought into contact with the carrier. Secondly, the heat sink is covered but does not contact a plurality of crystal grains, and the heat sink includes a plurality of heat spreaders corresponding to a plurality of Φ grains. Then, the back surface of the die and the heat sink are sealed in a molding manner using a sealant. Then, the heat sink is cut to form a plurality of unit packages, and each unit package includes a die and a heat sink. And, the carrier portion of each unit 4 package is removed to form a desired heat sink type wafer size package. [Embodiment] 7 1355723 The heat dissipation gain type wafer size package of the present invention has the advantage that, at the time of wafer packaging, a heat dissipating component is built in the chip package. This solution not only simplifies the process of separating the original packaged wafer from the device's heat dissipating component, but also promising to solve the problem of future chip heat dissipation and fast production and short time. Fig. 1 illustrates a preferred embodiment of the heat dissipation gain type wafer size package of the present invention. The heat dissipation gain type wafer size package 100 includes at least one die 110, a heat sink 120 and a gel 130. The die 110 has an active surface 111 and a back surface 112, and the back surface 112 is surrounded by the heat sink 120, but the active surface 111 is exposed outside the heat sink 120. The die 110 can be any suitably diced semiconductor wafer. In general, the heat sink 120 may comprise a highly thermally conductive material to enhance heat dissipation efficiency, such as copper, metal or non-metallic materials such as lyon. The encapsulant 130 covering the back surface 112 of the die Π0 and the heat sink 120 exposes the active surface of the die 110 to facilitate future electrical connection. Although the heat dissipation effect of the bare crystal is good, it is susceptible to environmental influence and damage. Therefore, in the present invention, the sealing body 130 is used to protect the die 110, and the die 110 and the heat sink 120 are adhered and fixed. The encapsulant 130 is generally a good thermal conductivity molding material, such as epoxy molding compound (EMC), etc. 0 1355723 For the convenience of future use, the active surface 111 preferably may comprise at least one pad (pads) ), bumps and other types of input and output (I / O) endpoints (not shown), for electrical connection. Or for the convenience of cutting, the active surface 111 may be sealed with a viscous carrier 140 as needed, and then removed after the cutting is completed. The shape of the heat sink 120 may be trapezoidal or hat-shaped such that the back surface 112 is surrounded by the heat sink 120. The encapsulant 130 does not have to completely cover the heat sink 120 as needed. For example, when the heat sink 120 has a top portion 121 and an extension portion 122, the sealant 130 may cover only the extension portion 122' without covering the upper surface of the top portion 121. In addition, the surface of the heat sink 120 may also be provided with heat dissipation patterns of a plurality of grooves, protrusions, nicks, rough surfaces, openings, etc. to increase the heat dissipation area of the heat sink 120 and improve the adhesion of the sealing body 130 to the heat sink 120. effect. 2-6 illustrate a preferred embodiment of the method of forming a heat dissipation gain type wafer size package of the present invention. The method for forming a heat dissipation gain type wafer size package of the present invention firstly adheres a plurality of crystal grains 210 independently to a carrier 240 having a selective viscosity. Each of the cut dies 210 has an active surface 211 and a back surface 212, and when the die 210 is adhered to the carrier 240, the active surface 211 of each die 210 contacts the carrier 240 〇9 1355723 For future use, the active surface 211 may include at least one type of input/output (I/O) terminal (not shown) such as pads and bumps for electrical connection. The carrier 240 can comprise a composite layer structure such as a glue and a rigid substrate or a sticky knee and a tape. The adhesive can have a selected point of view and lose its viscosity under appropriate conditions, such as by exposure or heating. In general, the rigid substrate can be a glass, tantalum, metal, or the like. Next, as shown in Fig. 3, the heat sink 220 is covered but does not contact the plurality of crystal grains 210. The heat sink 220 includes a plurality of heat spreaders 226 corresponding to the plurality of dies 210. In general, the heat sink 220 can comprise a highly thermally conductive material to enhance heat dissipation efficiency, such as metallic or non-metallic materials such as copper and aluminum. In addition, the surface of each of the heat dissipating members 226 may be provided with heat dissipation patterns of a plurality of grooves, protrusions, nicks, rough surfaces, openings, etc. to increase the heat dissipation area and increase the adhesion area. Then, as shown in FIG. 4, the encapsulant 230 is filled in the gap between the heat sink 2 26 and the die 210 and the periphery of the heat sink 2 26 in a molding manner to seal the die 210. The back side 212 secures the heat sink 226 to the die 210. Although the heat dissipation effect of the bare crystal is good, it is easily affected and destroyed by the environment, so the sealant 230 is used to protect the crystal grains 210. The encapsulant 230 is usually a mold material having good thermal conductivity, such as an epoxy molding compound (EMC) or the like. 1355723. Next, as shown in FIG. 5, the tangential package body has a unit body material 2=成|for each single sheet 210 and one heat sink 22 〇, the shape of the heat sink 220 can be; shape. At this time, the fins 220 may have a dome shape or a cap such that the back surface 212 is surrounded by the fins 220. Depending on the situation, ^ 23 〇 does not have to be finished with the heat sink 22 is the case, the sealant - Τ cover. For example, the encapsulant may cover only the extension portion 222 without covering the top portion 221. After cutting, as shown in Fig. 6, the unit portion of the body part can be removed, and the wire is moved to the surface (4). The chip size package 201. As previously mentioned, _ can have a selected viscosity, so that it can be properly ridden to lose the purity, except for the carrier portion 24 of the unit package 200. Since the heat dissipation gain type wafer size package of the present invention is packaged in a wafer, that is, and the heat dissipation element is built in the chip package, the solution not only simplifies the separation of the original package wafer from the device heat dissipation element. Private, more forward-looking solution to the future heat dissipation problems of the chip and the advantages of fast production and short time. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should fall within the scope of the present invention. 1355723 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 illustrates a preferred embodiment of the heat dissipation gain type wafer size package of the present invention. 2-6 illustrate a preferred embodiment of the method of forming a heat sinking gain wafer size package of the present invention. [Main component symbol description] 100 heat dissipation type wafer size class package 110 die 112 back surface 130. Sealant body 200 package body 211 active surface 220 heat sink 222 extension portion 230 sealant 111 active surface 120 heat sink 140 carrier 210 crystal Grain 212 back 221 top 226 heat sink 240 carrier 12