J342598 九、發明說明: 【發明所屬之技術領域】 本發明是有關於一種高效能之積體電路的製作,且特別 是有關於一種形成比如是電感元件之高效能的電子元件於晶 ? 片之表面上的方法’可以降低因為晶片所導致的電磁損耗。 【先前技術】 半導體技術持續所追求的目標係能夠在具競爭性的價格 _ 下製造出向效能的半導體元件。隨著半導體製程及材料的研 發,再配合新型且精緻的元件設計,如此半導體元件的尺寸 ' 可以大幅縮小。大部分的半導體元件係用來處理數位資料, 然而也有部分之半導體元件整合有類比的功能,如此半導體 兀件便可明時處理紐資料及類比資料,或者半導體元件 亦可以僅具有類比的功能。製造類比電路的主要困難點之一 疋在於許多用於類比電路的電子元件甚大,難以與次微米極 φ 級的電子元件整合’尤其是針對電容元件及電感元件而言, 此乃因為電容元件及電感元件的尺寸過於龐大。 般而η電感元件係應用在移動通訊的領域中,比如 疋應帛在配置有射頻放大iiW amplifier)之半導體元件 上’而射頻放大器主要包括有調整電路(t_dcircuit),其 ’ 中罐電路具有電感元件及電容元件。雛電路之電感元件 * ㈣紐、電容元叙餘值及鮮騎料_整電路所 產生的阻抗,針對某一頻率的訊號,調整電路可以是具有高 5 阻抗的或是低阻抗的。調整電路可以阻隔或導通訊號之傳 導’並且依照元件的頻率,調整電路還可以放大類比訊號。 如此’調整電路可以作域波器之用,藉以渡掉某一頻率之 訊號或者是去掉由處理類比訊號之電路所產生的雜訊。利用 LC共振的原理,調整電路亦可以產生高的電子阻抗,藉以抵 消在部分線财之寄生電容效應。#電感元件形成於半導體 基底之-表面上時,會產生下述的問題,就是在螺旋狀之電 感元件與位在下面之基底之間所產生的寄生電容會有自我共 振的效應’因此會關#在設計高頻電路時,域元件的使 用。另外,藉由電感元件的設計,可以減少電感元件與位在 下面之基底之間的電容耦合。 在高頻電路中,由電感元件所產生的電磁場會使得石夕基 底内產生渦電流(eddy current)的現象。由於石夕基底係為一 種電阻型導體,因此渦電流會損耗電磁能量,產生嚴重的能 量損耗’而形成-低品質參數之電感元件,使得l/vz?之共振 頻率限制了頻率的上限。另外,由電感元件所產生的渴電流 會干擾靠近賴元件之電路效能。由於金射赚的原因, 用來形成概元叙細金麟路亦料耗能量,如此亦會形 成一低品質參數之電感元件。 在製作高頻類比半導體元件時,必須要提供一關鍵的元 件,就是電献件,藉·成LC舰電路。在現今半導體業 界’均朝向高元件紐_勢發展,耻基絲賴使用率 會大幅增加,即使如此,電感元件還是形成在極小化之基底 表面上’並且電感元件還要維持在高品質參數的情況下。一 般而言,形成在基底表面上的電感元件係在一平面上呈現螺 旋狀的樣式,此平面係平行於基紅表面。傳_造電感元 件於基底之表面上的方法有如下所述之限制。大部分高品質 係數的電感元件係配置在混合元件結構(hybrid devi ce confi即ration)中、單晶微波積體電路(M〇n〇HthicJ342598 IX. Description of the Invention: [Technical Field] The present invention relates to the fabrication of a high-performance integrated circuit, and more particularly to a high-performance electronic component such as an inductor component. The method on the surface can reduce the electromagnetic losses caused by the wafer. [Prior Art] The goal pursued by semiconductor technology is to be able to manufacture semiconductor components with performance at competitive prices. With the development of semiconductor processes and materials, coupled with new and sophisticated component designs, the size of such semiconductor components can be significantly reduced. Most of the semiconductor components are used to process digital data. However, some semiconductor components are integrated with analog functions, so that semiconductor components can process new data and analog data in a timely manner, or semiconductor components can have only analog functions. One of the main difficulties in manufacturing analog circuits is that many of the electronic components used in analog circuits are very large and difficult to integrate with sub-micron φ-class electronic components, especially for capacitive and inductive components, because of capacitive components and inductors. The size of the component is too large. Generally, the η-inductive component is used in the field of mobile communication, such as 疋 帛 半导体 on a semiconductor component equipped with an RF amplification iiW amplifier. The RF amplifier mainly includes an adjustment circuit (t_dcircuit), which has an inductance in the tank circuit. Components and capacitor components. Inductive components of the young circuit * (4) New Zealand, capacitor element residual value and fresh riding material _ the impedance generated by the whole circuit, for the signal of a certain frequency, the adjustment circuit can have high impedance or low impedance. The adjustment circuit can block or direct the communication of the communication number and the adjustment circuit can amplify the analog signal according to the frequency of the component. Thus, the adjustment circuit can be used as a domain waver to remove a signal of a certain frequency or to remove noise generated by a circuit that processes analog signals. Using the principle of LC resonance, the adjustment circuit can also generate high electronic impedance, thereby offsetting the parasitic capacitance effect in some of the lines. When the inductor element is formed on the surface of the semiconductor substrate, the problem arises that the parasitic capacitance generated between the spiral inductor element and the underlying substrate has a self-resonant effect. #Use of domain components when designing high frequency circuits. In addition, the capacitive coupling between the inductive component and the underlying substrate can be reduced by the design of the inductive component. In high-frequency circuits, the electromagnetic field generated by the inductive component causes an eddy current to occur in the bottom of the base. Since the Shixia base system is a resistive conductor, the eddy current will lose electromagnetic energy and cause severe energy loss' to form an inductive component with low quality parameters, so that the resonant frequency of l/vz? limits the upper limit of the frequency. In addition, the thirsty current generated by the inductive component can interfere with the circuit performance of the component. Due to the reasons for the gold shot, the energy used to form the summary of the Jinlin Road is also expected to consume energy, which will also form a low-quality parameter inductive component. When making high-frequency analog semiconductor components, it is necessary to provide a key component, that is, an electrical component, which is borrowed into a LC ship circuit. In today's semiconductor industry, both are moving toward high-component components, and the use of shame-based filaments will increase dramatically. Even so, inductive components are formed on the surface of the minimized substrate and the inductive components are maintained at high quality parameters. In case. In general, the inductive elements formed on the surface of the substrate exhibit a spiral pattern on a plane that is parallel to the base red surface. The method of transmitting the inductor element to the surface of the substrate has the following limitations. Most of the high-quality inductance components are arranged in a hybrid component structure (hybrid devi ce confi or ration), single crystal microwave integrated circuit (M〇n〇Hthic
Microwave Integrated Circuits,MMICas)中或者是由分開 配置之元件所,然社述電子元件之製造係料與積體 電路製造之基本製程整合。若是將作為類比資料控制及類比 資料貯存之電路與作為數位資料控制及數位資料貯存之電路 整合並製造在半導體大型基底上,則會達到許多顯著的優 點’而整合的優點包括降低製造成本及降低能量消耗。形成 在半導體基底表面上之螺旋狀的電感元件由於受到實際尺寸 的限制,會導致電感元件之線路與下面基底之間產生寄生電 容’並且受到位在下面之電阻性矽基底的影響,電感元件會 導致電磁能量損耗的發生。當調整電路之共振頻率突然下降 時’寄生電容會對LC電路產生嚴重的負面緣果。 值得注意的是,由電感元件所產生的電磁場會使得電阻 性之碎基底内產生渴..電流的現.象而產生嚴韋;的能.章損耗, 如此會形成一低品質參數之電感元件, 另外,可以藉由品質參數(Q)來代表電感之效能。品質參 數係定義為Q = Es/El,其中Es係代表貯存在元件之反應部 分的能量,而E1係代表在元件之反應部分所失去的能量。當 元件的品質愈高時,元件之電阻值會愈趨近於零,此時元件 之品質參數係趨近於無限大。就形成在矽基底上之電感元件 而言,由於受到位在下面之電阻性之矽基底所影響及受到形 成電感元件之金屬線路所影響,使得電磁能量會顯著地下 降。就元件而言,品質參數係用來量測元件之反應純度 (purity)或敏感性(susceptance) ’然而電阻性之石夕基底電 阻性之金屬線路及介電耗損均會降低品質參數。在實際上, 電路總是配置有部分會浪費能量之電阻元件,如此會減少能 夠被補償(recovered)之能量。品質參數係為無單位的,就裝 配在印刷電路板(PCB)上之分開g己置的電感元件而言,當品質 參數大於1GG時’係認定為具有甚高的品f參數;然:而就形 成在積體電路中之電感元件而言,品f參數敍約介於3到 10之間。 電感元件可以利用傳統的半導體製程形成在具有半導體 兀件之大型基底上’此時由電感元件所產生之寄生電容會限 纖止頻率的上限,_這姐_在許多制錢不能被接 受的,因此必須設計具有較高品質參數之電感元件,比如是 50或更局’其巾品f參數會受齡c電路之共軸率所影響。 ^知技射’必輕配置彼此分_元件才缺供較H 品質參數,吨些分開的元件要與厢元㈣舰整合。但 是當要將電感元件及這些周_元#配置於料體基底上而 ,形成大魏路結構時,便無法達絲品質參數_的。若 是採用非大型的電路結構,必須要配置額外的線路藉以連接 裝置之附屬元件,而此類似網路形式之用來連接的線路亦會 產生額外的寄生電容及電阻損耗。在RF放大器之許多應用 上’比如是可攜式電池充電的用品,此時電力的消耗是二項 重要的考量點’並且是要愈低愈好。藉由提高電力的消耗, 係可以部分地徽寄生電容效獻電阻能量損耗,但是這個 方法還是有-些限制。而上述的這_題均發生在市場快速 擴張的無線通_品上,比如是行動電話,其中RF積體電路 之整合係為最重要的挑戰之一。另外,藉由顯著地增加操作 頻率,比如是增加到l〇GHz到100GHz之間,可以部分解決上 述問題,然而在如此高的操作頻率之下,受到石夕基底的影響, 電感兀件的品質參數會顯著地下降。為了要使產品能夠在此 頻率下運作’研發^{大型電感元件,其斜㈣除了碎以外的 材質作為製作f感元件之基底,而這種大型電感元件比如可 以利用藍寶石(sapphire)或是石申化鎵(GaA_為基底。相較 ;夕基底’ ι^_些形成在非石夕材質之基底上的電感元件具有較 低的基底損耗,此乃因為不會形成渦電流(eddy , 因此便不會有電磁能I的損耗’如此可以製作出且有古。所 參數之電感元件。並且,彻上述方式所形成之電感元件: 產生較少的寄生電谷,因此可以允許在較高的頻率下操作。 然而,若是需要更複雜的應用,還是必須要利用矽作為基底 來形成電感元件,此乃因為若是要利用除了矽以外的材質 比如是砷化鎵,作為基底係為甚為麻煩的,並且在形成半導 體元件時,會遇到需多技術上的挑戰。由於砷化鎵在高頻下 係為半絕緣的材質,因此可以減少因為砷化鎵基底所導致的 電磁損耗,如此可以增加形成在砷化鎵基底上之電感元件的 品質參數。然而砷化鎵之RF晶片係為非常昂貴妁,若是能夠 避免使用砷化鎵之KF晶片,則在製程上具有較佳的成本優 勢。 在不犧牲元件效能的情況下(比如是因為基底損耗而犧 牲元件效能),有許多方法可以將電感元件與半導體環境整 合。其中一種方法便是利用姓刻或是微機械加工的方式將位 在電感元件底部之夕基底選擇性地去除,因此可以減少基底 之電阻此I耗損及寄生效應。另外一種方法便是利用多層金 屬層連線’其材質比如是鋁,或是利用陰刻法(damascene) 所形成之銅金屬層連線。 而另外一種方法’便是利用高電阻性之矽基底,如此可 ' 阻耗損。而由基底所產生的電阻 損耗會顯著地影響崎作為材f之電感鱗的品質參數。另 外,偏壓井(biased weli)可以配置在職狀之電感元件下, 因此可喊少基底内之電感鋪。而另外—種複雜的方法是 形成主動性之電感元件,其可_社動電路模擬電感元件 之電子特性。然而模賴電感元件會導致高功率的消耗並且 «有雜訊的產生’故此方法*能應帛在低功率及高頻率的產 叩上。所有的方法均有制的目的,就是要提高電感元件之 品質參數及降低賊元件在製造上的表_,而最重要的考 量點就是齡電磁能量祕的部分,此乃因為電磁能量會使 石夕基底產生渦電流。 當積體電路之體積縮小之際,每片晶片之成本會降低, 並且會增進晶>1某方面之效能。絲連接晶片與其他線路或 系統之錢連線變得較為重要,並域著積體電路逐漸縮小 之際’這些金屬連線會對線路效能產生嚴重地負面衝擊。由 於金屬線路之寄生電容及電阻會增加,因此會導致 顯著地下降,其巾最_簡耗在於電_流排及接地匯 流排之電壓降及關鍵訊號電路之電阻電容遲緩⑽扣㈣效 應。若是為了降低電__寬的金屬線路,則又會導致金 屬線路具有較高的電容。 曰 在現今的技射’當電感元件欲軸在轉體基底上 1342598 %,可以利用細線路的技術,.並且將電感元件形成在保護層 下。如此會使得電感元件很接近基底的表面,而電感元件與 基底之表面間的距離基本上是小於10微米,因此在矽基底内 會導致高電磁損耗的產生,且會降低電阻元件之品質參數。 美國專利公告第5,212,403號(Nakanishi)揭露一種形 成線路連線的方法,其中内部及外部之線路連線係形成在位 於晶片上之線路基底内,並且邏輯線路的設計會取決於線路 連線的長度。 美國專利公告第5 5〇1,〇〇6號((;故111如,Jr·的Μ )揭 露一種積體電路與線路基底之間具有絕緣層之結構而藉由 分散出去㈣腳可以是晶狀接點絲板之接點電性連接。 美國專利公告第5, 055, 907號(Jacobs)揭露一種整合型 半導體構,可以允許製造商將一薄膜多層線路形成在支撐 基板上或晶片上,藉以整合位在晶片外之電路。 吳國專利公告第5,1G6,461號(V〇lfs〇n et al.)揭露一 種多層連線結構,其係藉由TAB結構並利用聚醯亞胺 (polyimide)之介電層及魏層交互疊合於晶片上而成。 美國專#!公告第5,咖,767號(wenzei et al.)揭露一種 在PBGA、、’σ構中降低電阻電容遲缓效應之方法,其中多層金屬 層係分開配置。 、國專利Α告苐5, 686, 764號(Fulcher)揭露一種覆晶 12 基板’藉由將電源線與輪入輸出引線分開配置,可以降低電 阻電容遲緩效應。 美_说告第6, _,搬號(Α1_ et al.)揭露-種 利用兩層金屬層所形成之螺旋狀電感元件,其中此兩層金屬 層可以利用導通孔連接。 美國專利公告第5, 372, 967號(Sunda· et al·)揭露- 種螺旋狀電感元件。 美國專利公告第5, 576, _號(一)及第5, 884, 990號 (Burghartz et al.)揭露一種其他形式之職狀電感元件。 【發明内容】 因此本發明目的之—就是提供—種高效能之晶片結構, 尤其可以改善RF之效能。 本發明目的之二就是提供—種具有高品質係數之電感元 件的製造方法。 本發明目的之二就是可以利用石夕晶片來代替石中化鎵晶 片,並且在石夕晶片上可以製作出高品質係數之電感元件。 本發明目的之四就是可以使形成在矽基底表面上之電感 元件的頻率範固延伸。 本發明目的之五就是可以使形成高品質之被動元件於矽 基底的表面上。 有關於在保護層上製作厚介電層聚合物層及在此厚介電 層聚合物層上製作又寬又厚的金屬線路之製程可以參照美國 13 專利公告第6, 383, 916號。本發鴨延伸自細專利公告第 6, 383, 916號,並且在本發明還揭露可以形成高性能之電子 元件於保護層上或是厚介電層聚合物層上,:其中電子元件比 如是電感元件、電容元件或雜元件,糾,.树明還提供 -種將已經製作完成的被冑元件#合到晶.片之表面上的方 法。 為讓本發明之上述和其他目的、特徵、和優點能更明顯 易懂’下文特雜佳實關,尬合所關式,作詳細說明 如下: 【實施方式】 美國專利公告第6, 383, 916號係讓渡於與本發明相同之 讓渡人,其揭露一種晶片結構具有重配置線路層及金屬連線 層’係配置在介電时合_上,其巾介電財合物層係位 於傳統晶片之保護層上。保護層係位於積體電路上,而厚的 聚合物層係選擇性聽置在保護層上,寬的或厚的金屬連線 係位在保護層上。 美國專利公告第6, 303, 423號係讓渡於與本發明相同之 讓渡人其揭路一種形成具有高品質參數之電感元件於晶片 之保護層上的結構。錄具有高品質參數之賊元件可以應 用在高頻電路中’並且可以減少魏的損耗。在此案中還 揭露電容元件及電阻元件,可⑽成在矽基底的表面上,藉 以減少位於矽基底下之電子元件所引發出的寄生效應。 清參照第1圖,錄示依照翻專利公告第6, 383, 916 叙晶片結構_面示意圖。魏底半導體基底m比如是 砍基底)的表φ具有電晶體„及魏树(树示於第2 圖)絲底半導縣底10的表祕覆蓋有内部介電層 miLD) ’位於上述之電子元件上。金屬/介電層μ係位於内 部介電層12上,金屬/介電層14包括至少—層之介電層而 至少一金屬連線13係位在金屬/介電層14中,金屬連線13 倾成電子連接_路,啼上層之金柄具有料區域係 定義為電子接點16,這些電子接點16可以與位於石夕基底半 導體基底1G之表面上或表面内之電晶體u或其他元件電性 連接。保護層18係位於金屬/介電層14上,藉以避免移動離 子(比如是納離子)、濕氣、過渡金屬(比如是金、銀、銅)或 其他污染物進人到晶片内,其中保護層18比如是由氧石夕化合 物或氮矽化合物所構成之複合層。保護層18係用來保護位在 下面之比如是電晶體、多晶矽電阻元件或多晶矽—多晶矽電容 元件之電子元件及細金屬線路。 美國專利公告第6’383, 916號之關鍵步驟係起始於沈積 厚的聚合物層20開始,其中聚合物層2〇係沈積在保護層18 上。為了要與電子接點16連接,開口 22、36、38會穿過聚 合物層20及保護層18,並且會對準於電子接點16。透過位 於聚醯亞胺(polyimide)層聚合物層2〇内之開口 22、36、38, 電子接點16可以將電性延伸至聚合物層20中。 在較佳的情況下,聚合物層20之材質比如是聚醯亞胺 (polyimide) ’而聚合物層20比如是感光材料。而聚合物層 20之材質亦可以是苯基環丁烯(benzocyclobutene,BCB)、 聚亞芳香基醚(pary 1 ene)或者是以環氧樹脂為基礎之材料, 比如疋SU-8環氧樹脂(可以從Sotec M i crosysterns, Renens, Switzerland 獲得)。 在形成開口 22、36、38之後,可以進行一金屬化製程, 藉以形成圖案化寬金屬層金屬連接線路26、28,並且可以連 接電子接點16。而線路金屬連接線路26、28可以是任何設 计形式之寬度及厚度,以符合所需的電路設計,且線路金屬 連接線路26、28可以作為電源匯流排、接地匯流排或訊號匯 々IL排之用。經由打線導線或凸塊可以使線路金屬連接線路 26、28連接於晶片外之電路。 電子接點16係位在薄介電層金屬/介電層14(如第j圖 所示)的頂部,並且電子接點16之尺寸可以縮小,藉以減少 位於下面之金屬層的電容值。若是電子接點16 t尺寸過大 時,會影響金屬層之繞線。 在硬化之後,比如是聚醯亞胺之厚聚合物介電層聚合物 層20的厚度可以超過2微米’而聚合物介電層聚合物層2〇 之厚度比如是介於2微米到⑽微米之間,視電子設計之需 求而定。峨較厚吨邮胺層聚合⑽2“言,可以利用 多次旋塗及魏的巧,職雜亞絲合物薄膜。 美國專利A告第6,383, 916號揭露彻厚或寬之金屬金 屬連接、祕28卿私第1 ®麻之具林_的路徑 30、32、34 ’可以作為電路間的電性連接之用。相較於位在 下層之細線路金顧14 _金線13,賴寬之金屬金 屬連接線路28具有較小的電阻值及電容值,並且較容易製 造,且成本較低。 n明參照第2圖’其係修改自美國專利公告第6, 383, 916 號,並且還形成電感元件40於厚聚醯亞胺層聚合物層2〇上。 電感兀線4G係為平_形式,並且可以平躲基底半導體基 底1〇的表面,而透過多層丨2、14、18、20結構所構成之高 度’可以使得電感元件4〇遠離基底半導體基底1〇之表面。 第2圖綠示係以垂直於基底丰導體基底10之表面作剖面所形 成之電感το件40之剖秘構40。藉由寬及厚之金屬的設計, 可以減少電阻能量的損耗。射,可以_賴的方式,形 成比如是金、銀或銅之低電阻金屬,而其金麟度比如是大 約20微米。 相較於將電感元件形成於護層下之習知技術,藉由增 加電感70件與矽基底之間的距離,·可以減少矽基底1〇所產生 的電磁場’並且錢元件之品數可城高。電感元件可 17 以形成在賴層上’或者可以形成在位祕上之厚介電 層聚合物層(比如絲醯亞胺)上。另外,则寬且厚的金屬 所死>成之電感元件,具有較小的寄生電阻。. 本發明之另一重點,就是保護層18之開口 19的寬度可 以小至0.1微米。因此’電子接點16可以是很小的,如此可 以提升位在頂層之細線路金屬層之繞線能力,並且具有較低 之電容值。 而本發明之另一重要特徵,就是聚合物層20之開口 22、 36、38可以是大於保護層ι8之開口 19,而聚合物層2〇之開 口 22、36、38係對準於保護層18之開口 19 ^將聚合物層2〇 設計有較大的開口 22、36、38係為一種選擇性的設計,並且 較谷易裝作元成,且將聚合物層2〇設計有較大的開口 a、 36、38可以配合厚金屬層的設計使用,藉以完成本發明在形 成保遵層18後之金屬沈積製程。 第2圖繪示連線結構金屬連接線路26及電感元件4〇, 其中電感元件40包括兩個接點41、43,透過聚合物層2〇可 以與電子接點16電性連接。 另外,請參照第2圖,依照本發明之另一觀點,還可以 形成另一聚合物層於如第2圖所示的結構上。 第24a圖及第24b肩繪示本發明之另一特徵,其中連接 到1;感το件之接點的方式係不同於如第2 _秋兩個向下 1342598 連接的接點。如第24a圖所示,其中介電層聚合物層35係形 成在金屬連線金屬連接線路26及電感元件4〇上,而介電層 聚合物層35之材質比如是聚酿亞胺。開口接點開口施錢 通至電感7G件40之-端,並且可轉電感元件仙之一端暴 露於外。錢耕4G具H連接之接點及-向下連接之 接點39,其係為“-上—下,,的結構。 第24b睛示另夕卜種結構,其中具有兩個朝上的接點 開口施、撕’係暴露出電感元件40,其係為“均為朝上” 的結構。 在第24a圖及第24b圖中’電感元件之朝上的接點可以 透過打線的方式或是形成凸塊的方式與外部元件電性連接。 就打線製程而言’電感元件4Q元件之上表面必須要形成一可 與打線導線接合的金屬,其材質比如是金或銘。就凸塊連接 而έ,凸塊底層金屬(UBM)可以形成在朝上的接點開口中,藉 以形成凸塊。 在第24a圖及第24b ®中,糊形成與結構金屬連接線 路26及電感元件40相同之方法來形成連接線路,可以使電 感元件40經由接點開口 36a、38a與晶片上之其他接點或如 前所述之外部元件電性連接。 請參照第24c圖,其繪示本發明之另一特徵,其中一延 伸線路89會連接至電感元件4〇 ’而接點開口 36b會暴露出 延伸線路89 ’其中接點開口 36b的位置比如是在晶片的邊 緣,而可以方便進行打線製程,如此電感元件4〇可以透過延 伸線路89改變對外連接的位置。接點開口 38b的配置係如前 所述。延伸線路89、金屬結構金屬連接線路.26與電感元件 40係同時製作完成。 延伸線路89可以連接至電感元件4〇,藉以改變電咸元 件40對外連接的位置,其中延伸線路89可以具有向下連接 的接點(未繪示,但是此概念之前已敘述過),取代向上連接 的接點36b。 §電感元件的接點係位在中間區域時,比如是第24c圖 之開口接點開口 38b所暴露之接點,此時位在電感元件4〇 之中間區域的接點係無法藉由延伸線路89而改變其對外連 接的位置,但是位在電感元件40之中間區域的接點可以向上 連接或是向下連接。 第3圖繪示螺旋狀電感元件4〇之上視圖,其中電感元件 40係位在介電層聚合物層2〇之表面上,第2圖所示的電感 元件40係為第3圖中沿著剖面線2-2之剖面示意圖。 第4圖繪示電感元件4〇之剖面示意圖,藉由增加一導電 片44a可以隔絕電感元件40對基底半導體基底1〇的影響, 其中導電片44a係大致上位在電感元件4〇下,而導電片44a 比如是銅或金之導電材料。導電片44a係在保護層18之表面 20 ^42598 上延伸,且電感元件4〇係對準於導電片44a且位在導電片 44a上。導電片44a可以稍微地超過電感元件40之邊界區 域’如此更可以增進遮蔽基底半導體基底1〇的能力,藉以避 免基底半導體基底1〇受到電感元件40之電磁場的影響。 請參照第4圖,電感元件4〇至少百分之五十以上的區域 與半導體基底10之間係存在有導電片44a’在較佳的情況 下,電感元件40至少百分之八十以上的區域與半導體基底 10之間係存在有導電片44a,如此更可以增進遮蔽基底半導 體基底10的能力。 導電片44a可以電性連接於電感元件40之其中一電極 (如第4圖所示,導電片44a可以與電感元件4〇之最右端的 作為電極之接點43電性連接),而導電片44a可以是處在浮 動電壓之準位’或者是可贿其他的電解位連接,取決於 系統的電子設計。 製作導電片44a的方法及材質可以是利用如後所述之製 作金屬連接祕26及賴元件40的方法及材質。在製作導 電片44a時可以同時形成導體44,而藉由導體44可以將位 在上層之厚金屬連接至電子接點16,如第4圖所示。 第二聚合物層47可以是選雜地形成在元件4〇上 及金屬連躲路26上’可輯金·構提供額外的保護。 請參照第12圖至第23圖,其繪示依照本發明保護層上 21 形成電感元件或其他被動元件之方法。如第12圖所示,基底 80係為位在下層之介電層,而金屬接點81的材質比如是鋁。 藉由圖案化的步驟可以形成開口 82,貫穿保護層84,而開口 82可以暴露出金屬接點81。比如是聚醯亞胺之聚合物層86 可以是形成在保護層84上及金屬接點81上,而比如是聚酿 亞胺之聚合物層86比如是利用旋塗的方式完成,或者亦可以 利用網板印刷的方式完成,或者亦可以是利甩壓合聚合物乾 膜的方式完成。 第13圖係繪示形成聚合物層86之開口 87的製程,其中 聚合物層86之開口 87之最大寬度係大於保護層84之開口 82之最大寬度(請參見圖12第12圖),開口 87具有傾斜的 側壁85。在剛開始時’聚合物層86之開口 87具有垂直之側 壁85 ’然而在經過硬化步驟之後,側壁85會呈現傾斜的樣 式,而開口 87可以是呈現半錐形的樣式,而侧壁85的傾斜 角度比如是45度或是更大’基本上大約是介於5〇度到6〇 度之間。另外’侧壁85的傾斜角度亦可以是小至20度。 在本實施例中’較大的導通孔線路(vias)可以是穿過比 如是聚酿亞胺之聚合物層86,且對準於較小之位在下層之保 濩層84的開口 82 ’並且還連接位在下層之次微米金屬層。 隨著由次微米金屬層往寬金屬層級的方向,次微米金屬之導 通孔線路之尺寸可以是逐漸加大。 1342598 請繼續參照第13圖,其繪示依照本發明形成保護層上連 接線路及電感it件之方法及金屬結構。首先可㈣用滅鍵的 方式,形成-黏著/阻障層88,其材質包括觸合金、鈦氮 化合物、纽或奴氮化合物等,而黏著/阻障層88的厚度比如 是介於500埃(angStrom)到5000埃之間。接著,可以利用濺 鍍的方式形成比如是金的種子層90於黏著/阻障層兕上,其 中種子層90的厚度比如是介於300埃到3〇〇〇埃之間。 請參照第14圖,接著可以利用電鍍的方式,形成一厚金 屬層92,其材質比如是金,其中厚金屬層犯的厚度比如是 >m於1微米到20微米之間。而在進行電鍍製程之前,會先形 成厚光阻94,而光阻94的厚度大於或等於厚金屬層犯的厚 度,透過微影步驟’光阻94會暴露出種子層9〇,接著才以 電鍍的方式形成厚金屬層92。 在電鍍製程之後,可以將光阻94去除,如第15圖所示。 利用厚金顧92作為蝴罩蔽,並藉由_製程可以去除黏 著/阻障層88及種子層90,如第16圖所示。在圖示中,僅 繪不出電感元件40之其中一線圈,然而熟悉該項技藝者應 知,整個電感元件40可以在此步驟完成。 如第17圖及第18圖所示’厚金屬層92亦可以是僅填入 於開口 87中之部分區域’如此可以設計出線路密度高且線路 甚細之電感元件。而在本實施例中,聚合物層86的開口 87 23 1342598 之尺寸D比如是約15微米1電感元件40之金屬線路之門 距係小至4微米。因此,將位於聚合物層86之開n 金屬圖案化亦是本發明的重要特徵。 如前所述,可以利用濺鍍的方式,形成一黏著/阻障屏 88及比如是金的種子層9G,並且還形成—光阻%,如第^In Microwave Integrated Circuits (MMICas), the components of the electronic components are integrated with the basic processes of integrated circuit manufacturing. If the circuit for storing analog data and analog data is integrated with the circuit for digital data control and digital data storage and fabricated on a large semiconductor substrate, many significant advantages will be achieved. The advantages of integration include reducing manufacturing costs and reducing energy consumption. The spiral inductive component formed on the surface of the semiconductor substrate is limited by the actual size, which causes a parasitic capacitance between the circuit of the inductive component and the underlying substrate, and is affected by the resistive germanium substrate underlying. Lead to the occurrence of electromagnetic energy loss. When the resonant frequency of the trimming circuit suddenly drops, parasitic capacitance can have serious negative consequences for the LC circuit. It is worth noting that the electromagnetic field generated by the inductive component causes the thixing of the resistive material to generate a thirst. The current of the current produces a sharp energy; the energy loss of the energy can form a low-quality parameter of the inductance component. In addition, the quality parameter (Q) can be used to represent the performance of the inductor. The quality parameter is defined as Q = Es/El, where Es represents the energy stored in the reaction part of the component and E1 represents the energy lost in the reaction part of the component. When the quality of the component is higher, the resistance value of the component will become closer to zero, and the quality parameter of the component will be infinitely large. In the case of an inductive component formed on a germanium substrate, electromagnetic energy is significantly degraded due to the influence of the underlying resistive underlying substrate and the metal circuitry forming the inductive component. In terms of components, the quality parameters are used to measure the purity or susceptance of the component. However, the resistive metal circuit and dielectric loss of the base-resistance class degrade the quality parameters. In practice, the circuit is always equipped with some resistive components that waste energy, thus reducing the amount of energy that can be recovered. The quality parameter is unitless. For a separate component that is mounted on a printed circuit board (PCB), when the quality parameter is greater than 1 GG, the system is considered to have a high product f parameter; For an inductive component formed in an integrated circuit, the product f parameter is between about 3 and 10. Inductive components can be formed on large substrates with semiconductor components using conventional semiconductor processes. 'The parasitic capacitance generated by the inductive components at this time limits the upper limit of the frequency of the fiber. _ This sister is unacceptable in many ways of making money. Therefore, it is necessary to design an inductive component with a higher quality parameter, such as 50 or more. The parameter of the towel f is affected by the coaxiality of the circuit of the age c. ^Knowledge shooting 'will be lightly configured to each other _ components are missing for more than H quality parameters, tons of separate components to be integrated with the car (four) ship. However, when the inductive component and these peripheral elements are to be placed on the substrate of the material to form a large Wei road structure, the quality parameter of the wire cannot be reached. If a non-large-scale circuit structure is used, additional lines must be configured to connect the components of the device, and the lines used for connection in the form of a network also generate additional parasitic capacitance and resistance loss. In many applications of RF amplifiers, such as portable battery charging supplies, power consumption is a two important consideration at this time and the lower the better. By increasing the power consumption, the parasitic capacitance can be partially compensated for the resistance energy loss, but this method still has some limitations. All of the above problems occur in the rapidly expanding wireless products, such as mobile phones, where the integration of RF integrated circuits is one of the most important challenges. In addition, by significantly increasing the operating frequency, for example, increasing to between 10 GHz and 100 GHz, the above problem can be partially solved. However, under such a high operating frequency, the quality of the inductor element is affected by the base of the stone eve. The parameters will drop significantly. In order to enable the product to operate at this frequency, 'R&D^{large inductive components, the oblique (4) material other than shreds is used as the base for making the f-sensing components, such as sapphire or stone. Shenhua gallium (GaA_ is the base. Compared with the base substrate ι^_ some of the inductive components formed on the non-Shixia material substrate have lower substrate loss, because eddy current is not formed (eddy) There will be no loss of electromagnetic energy I. So it can be made and has an ancient. The inductive component of the parameter. And, the inductive component formed by the above method: produces less parasitic electric valley, and thus can be allowed to be higher. Operating at a frequency. However, if more complex applications are required, it is necessary to use germanium as a substrate to form the inductive component, because if a material other than germanium, such as gallium arsenide, is used, it is troublesome as a substrate. And when forming a semiconductor component, there are many technical challenges encountered. Since gallium arsenide is a semi-insulating material at a high frequency, it can be reduced because of arsenic. The electromagnetic loss caused by the gallium substrate can increase the quality parameters of the inductive component formed on the gallium arsenide substrate. However, the RF chip of gallium arsenide is very expensive, and if the KF wafer using gallium arsenide can be avoided, There is a better cost advantage in the process. Without sacrificing component performance (such as sacrificing component performance due to substrate loss), there are many ways to integrate the inductive component with the semiconductor environment. One way is to use the last name Or the micromachining method selectively removes the substrate at the bottom of the inductor element, thereby reducing the resistance of the substrate and the parasitic effect. Another method is to use a multi-layer metal layer connection. Aluminum, or copper metal layer wiring formed by damascene. Another method is to use a high-resistance tantalum substrate, which can resist loss, and the resistive loss generated by the substrate is significant. The ground affects the quality parameters of the inductance scale of the material f. In addition, the biased well (biased weli) can be placed in the job Under the components, it is possible to shout less inductive paving in the substrate. Another complicated method is to form an active inductive component, which can simulate the electronic characteristics of the inductive component. However, the inductive component can lead to high power. Consumption and «there is noise generation', so this method can be applied to low-power and high-frequency calving. All methods have the purpose of improving the quality parameters of the inductive components and reducing the thief components in manufacturing. On the table _, and the most important consideration is the part of the age of electromagnetic energy, this is because the electromagnetic energy will cause eddy currents in the Shi Xi substrate. When the volume of the integrated circuit is reduced, the cost per wafer will be reduced. And will enhance the performance of the crystal >1. The wire connection between the wire and other lines or systems becomes more important, and the integrated circuit is gradually reduced. Serious negative impact. Since the parasitic capacitance and resistance of the metal line increase, it will cause a significant drop. The most convenient consumption of the metal line is the voltage drop of the power_flow and ground bus and the delay of the resistance and capacitance of the key signal circuit (10). If it is to reduce the metal line of the electric __ wide, it will lead to a higher capacitance of the metal line.曰 In today's technology, when the inductive component is about 1342598% on the rotating substrate, fine-line technology can be used, and the inductive component is formed under the protective layer. This causes the inductive component to be in close proximity to the surface of the substrate, and the distance between the inductive component and the surface of the substrate is substantially less than 10 microns, which results in high electromagnetic losses in the crucible substrate and reduces the quality parameters of the resistive component. U.S. Patent No. 5,212,403 (Nakanishi) discloses a method of forming a line connection in which internal and external line connections are formed in a circuit substrate on a wafer, and the design of the logic line depends on the length of the line connection. . U.S. Patent Publication No. 5,5,1,6 ((1,111,Jr.) discloses a structure having an insulating layer between an integrated circuit and a circuit substrate, and by dispersing the (four) legs, it may be crystal. The contact of the wire is electrically connected. U.S. Patent No. 5,055,907 (Jacobs) discloses an integrated semiconductor structure that allows a manufacturer to form a thin film multilayer circuit on a support substrate or on a wafer. In order to integrate the circuit outside the wafer. Wu Guo Patent Publication No. 5, 1G6, 461 (V〇lfs〇n et al.) discloses a multilayer wiring structure which utilizes a TAB structure and utilizes polyimine ( The dielectric layer and the Wei layer of the polyimide are superimposed on the wafer. US Special #! Announcement No. 5, No. 767 (wenzei et al.) discloses a method for reducing the resistance and capacitance in the PBGA, 'σ structure. The method of mitigating effect, wherein the multi-layer metal layer is separately configured. The national patent report 苐 5, 686, 764 (Fulcher) discloses a flip chip 12 substrate 'by separating the power line from the wheel input and output leads, which can be reduced Resistor-capacitor slow effect. US _ tells the sixth, _, moving number (Α1_ et al.) A spiral-shaped inductor element formed by using two metal layers, wherein the two metal layers can be connected by via holes. U.S. Patent No. 5,372,967 (Sunda et al.) discloses a spiral Inductive components. U.S. Patent Nos. 5,576, _ (1) and 5,884,990 (Burghartz et al.) disclose another form of inductive component. [SUMMARY OF THE INVENTION] It is to provide a high-performance wafer structure, and in particular to improve the performance of RF. The second object of the present invention is to provide a method for manufacturing an inductor element having a high quality coefficient. The second object of the present invention is to replace the stone wafer. A gallium wafer is used in the stone, and a high-quality inductance element can be fabricated on the Shi Xi wafer. The fourth object of the present invention is to extend the frequency of the inductance element formed on the surface of the crucible substrate. It is possible to form a high-quality passive component on the surface of the germanium substrate. A thick dielectric layer polymer layer is formed on the protective layer and a thick dielectric polymer layer is formed thereon. A process for making a wide and thick metal line can be found in U.S. Patent No. 6,383,916, the disclosure of which is incorporated herein by reference. The electronic component is on the protective layer or on the thick dielectric layer polymer layer, wherein the electronic component is, for example, an inductive component, a capacitive component or a hybrid component, and the device also provides a bedding component that has been fabricated. The method of the above-mentioned and other objects, features, and advantages of the present invention can be more clearly understood. The following is a detailed description of the following: [Embodiment] U.S. Patent No. 6,383,916 is assigned to the same assignee as the present invention, which discloses a wafer structure having a reconfigured wiring layer and a metal wiring layer disposed in a dielectric junction. The upper dielectric layer of the towel is located on the protective layer of the conventional wafer. The protective layer is on the integrated circuit, while the thick polymer layer is selectively overlaid on the protective layer and the wide or thick metal wiring is tied to the protective layer. U.S. Patent Publication No. 6,303,423 is assigned to the same assignee as the present invention to provide a structure for forming an inductive component having a high quality parameter on a protective layer of a wafer. Recording thief elements with high quality parameters can be applied in high frequency circuits' and can reduce the loss of Wei. Also disclosed in this case are capacitive elements and resistive elements that can be (10) formed on the surface of the crucible substrate to reduce parasitic effects caused by electronic components located beneath the crucible substrate. Referring to Figure 1, the wafer structure is shown in accordance with Patent Publication No. 6, 383, 916. The surface of the Weidi semiconductor substrate m, such as the chopped base, has a crystal „ and Wei Shu (tree is shown in Fig. 2). The bottom of the semi-conducting county is covered with an internal dielectric layer miLD). On the electronic component, the metal/dielectric layer μ is on the inner dielectric layer 12, and the metal/dielectric layer 14 includes at least one dielectric layer and at least one metal wiring 13 is in the metal/dielectric layer 14. The metal connection 13 is electrically connected to the electronic circuit. The metal handle of the upper layer has a material region defined as an electrical contact 16, and the electronic contacts 16 can be electrically connected to or on the surface of the stone substrate 1G. The crystal u or other components are electrically connected. The protective layer 18 is located on the metal/dielectric layer 14 to avoid moving ions (such as nano ions), moisture, transition metals (such as gold, silver, copper) or other pollution. The material enters the wafer, wherein the protective layer 18 is, for example, a composite layer composed of an oxygen oxide compound or a nitrogen cerium compound. The protective layer 18 is used to protect the underlying layer such as a transistor, a polysilicon resistor or a polysilicon. Electrons of polycrystalline tantalum capacitor elements Components and fine metal lines. The key step in U.S. Patent Publication No. 6 '383, 916 begins with the deposition of a thick polymer layer 20 in which a polymer layer 2 is deposited on a protective layer 18. The contacts 16 are connected, and the openings 22, 36, 38 pass through the polymer layer 20 and the protective layer 18, and are aligned with the electronic contacts 16. Through the polymer layer 2 of the polyimide layer The openings 22, 36, 38, the electronic contacts 16 can extend electrically into the polymer layer 20. In the preferred case, the material of the polymer layer 20 is, for example, a polyimide layer and a polymer layer. 20 is, for example, a photosensitive material, and the material of the polymer layer 20 may also be benzocyclobutene (BCB), polyarylene ether (pary 1 ene) or epoxy-based material such as ruthenium. SU-8 epoxy resin (available from Sotec M crosysterns, Renens, Switzerland). After forming the openings 22, 36, 38, a metallization process can be performed to form patterned wide metal layer metal connection lines 26, 28 And the electronic contact 16 can be connected. The line metal connection lines 26, 28 may be of any design in width and thickness to conform to the desired circuit design, and the line metal connection lines 26, 28 may serve as a power bus, ground bus or signal sink IL The wire metal connection lines 26, 28 can be connected to the circuit outside the wafer via wire bonding wires or bumps. The electronic contacts 16 are tied to the thin dielectric metal/dielectric layer 14 (as shown in Figure j). The top, and the size of the electronic contacts 16 can be reduced to reduce the capacitance of the underlying metal layer. If the size of the electronic contact 16 t is too large, it will affect the winding of the metal layer. After hardening, the thickness of the polymeric dielectric layer polymer layer 20, such as polyimine, may exceed 2 microns' and the thickness of the polymeric dielectric layer 2, such as between 2 microns and (10) microns. Between, depending on the needs of electronic design.峨 Thicker ton of postal amine layer polymerization (10) 2 "In other words, it can be used for multiple spin coating and Wei Qiao, the application of the sub-filament film. US Patent No. 6,383, 916 discloses a thick or wide metal-metal connection, The path of 30, 32, 34' can be used as the electrical connection between the circuits. Compared with the fine line in the lower layer, the gold line 14 _ gold line 13, Lai Kuan The metal metal connection line 28 has a small resistance value and a capacitance value, and is relatively easy to manufacture and has a low cost. n. Refer to FIG. 2, which is modified from U.S. Patent No. 6,383,916, and also Forming the inductive component 40 on the polymer layer of the thick polyimide layer. The inductor wire 4G is in a flat form and can lie away from the surface of the base semiconductor substrate 1 through the plurality of layers 2, 14, 18, The height of the structure of the structure 20 can make the inductance element 4 〇 away from the surface of the base semiconductor substrate 1 。. The green diagram of the second embodiment shows the inductance τ of the surface 40 perpendicular to the surface of the base conductor substrate 10 Structure 40. With the design of wide and thick metal, the resistance can be reduced The amount of loss, radiation, can be formed into a low-resistance metal such as gold, silver or copper, and its golden stalk is, for example, about 20 microns. Compared with the conventional method of forming an inductor element under a protective layer. The technique, by increasing the distance between the inductor 70 and the crucible substrate, can reduce the electromagnetic field generated by the crucible substrate 1 and the number of components of the moieties can be high. The inductive component can be formed on the Lay layer' or It can be formed on a thick dielectric layer polymer layer (such as silk fibroimine). In addition, a wide and thick metal is killed> into an inductive component having a small parasitic resistance. Another important point is that the width of the opening 19 of the protective layer 18 can be as small as 0.1 micron. Therefore, the 'electronic contact 16 can be small, so that the winding capability of the fine-line metal layer at the top layer can be improved, and A lower capacitance value. Another important feature of the present invention is that the openings 22, 36, 38 of the polymer layer 20 can be larger than the opening 19 of the protective layer ι8, and the openings 22, 36, 38 of the polymer layer 2 Aligned with the opening of the protective layer 18 1 9 ^ The polymer layer 2〇 is designed with a larger opening 22, 36, 38 as a selective design, and is easier to install than the valley, and the polymer layer 2〇 is designed with a larger opening a 36, 38 can be used in conjunction with the design of the thick metal layer to complete the metal deposition process of the present invention after forming the conformal layer 18. The second figure shows the metal structure of the connection structure 26 and the inductance component 4, wherein the inductance component 40 includes two contacts 41, 43 through which the polymer layer 2 can be electrically connected to the electronic contact 16. In addition, referring to Fig. 2, another polymer layer can be formed according to another aspect of the present invention. In the structure as shown in Fig. 2. The 24th and 24b shoulders illustrate another feature of the present invention, wherein the connection to the 1; the contact of the sense is different from the second Connected contacts down 1342598. As shown in Fig. 24a, the dielectric layer polymer layer 35 is formed on the metal wiring metal connection line 26 and the inductance element 4, and the material of the dielectric layer polymer layer 35 is, for example, a polyimide. The open contact opening is applied to the end of the inductor 7G member 40, and one end of the transducible inductor element is exposed. Qiangeng 4G has a H-connected joint and a downward-connected joint 39, which is a structure of "-up-down,". Figure 24b shows an alternate structure in which two upwards are connected. The point opening and tearing exposes the inductive component 40, which is a "all upwards" structure. In Figures 24a and 24b, the contact of the inductive component can be wired or The way of forming the bumps is electrically connected to the external components. In terms of the wire bonding process, the upper surface of the component of the inductor component 4Q must form a metal that can be bonded to the wire bonding wire, and the material thereof is, for example, gold or gold. έ, the under bump metal (UBM) may be formed in the upward contact opening to form the bump. In the 24th and 24bth, the paste is formed in the same manner as the structural metal connection 26 and the inductive component 40. To form the connection line, the inductance element 40 can be electrically connected to other contacts on the wafer or external components as described above via the contact openings 36a, 38a. Referring to Figure 24c, another embodiment of the present invention is illustrated. Feature, one of the extension lines 89 will be connected to the electricity The sensing element 4〇' and the contact opening 36b expose the extension line 89', wherein the position of the contact opening 36b is, for example, at the edge of the wafer, and the wire bonding process can be facilitated, so that the inductance element 4 can be changed through the extension line 89. The position of the connection. The arrangement of the contact opening 38b is as described above. The extension line 89, the metal structure metal connection line .26 and the inductance element 40 are simultaneously fabricated. The extension line 89 can be connected to the inductance element 4〇 to change the electricity. The location where the salty component 40 is externally connected, wherein the extension line 89 can have a connector that is connected downward (not shown, but this concept has been previously described) instead of the connector 36b that is connected upwards. § The contact system of the inductor component In the middle region, for example, the contact exposed by the opening contact opening 38b of Fig. 24c, the contact located in the middle portion of the inductor element 4〇 cannot change the position of the external connection by the extension line 89. However, the contacts located in the middle of the inductive component 40 may be connected upwards or downwards. Figure 3 is a view of the spiral inductor component 4〇 The inductive component 40 is located on the surface of the dielectric layer polymer layer 2, and the inductive component 40 shown in FIG. 2 is a cross-sectional view along the section line 2-2 in FIG. 3. FIG. The cross-sectional view of the inductive component 4A can be used to insulate the influence of the inductive component 40 on the base semiconductor substrate 1 by adding a conductive strip 44a, wherein the conductive strip 44a is substantially above the inductive component 4, and the conductive strip 44a is, for example, copper. Or a conductive material of gold. The conductive sheet 44a extends over the surface 20^42598 of the protective layer 18, and the inductive element 4 is aligned with the conductive sheet 44a and is positioned on the conductive sheet 44a. The conductive sheet 44a may slightly exceed the inductance The boundary region of the component 40 is thus more capable of enhancing the ability to shield the base semiconductor substrate 1 , to prevent the base semiconductor substrate 1 from being affected by the electromagnetic field of the inductive component 40. Referring to FIG. 4, a conductive sheet 44a' is present between the region of the inductor element 4 〇 at least 50% or more and the semiconductor substrate 10. In the preferred case, the inductor element 40 is at least 80% or more. The conductive sheet 44a is present between the region and the semiconductor substrate 10, which further enhances the ability to shield the base semiconductor substrate 10. The conductive sheet 44a can be electrically connected to one of the electrodes of the inductive component 40 (as shown in FIG. 4, the conductive strip 44a can be electrically connected to the contact 43 of the rightmost end of the inductive component 4A as an electrode), and the conductive sheet 44a can be at the level of the floating voltage 'or other brittle connection, depending on the electronic design of the system. The method and material for producing the conductive sheet 44a may be a method and a material for producing the metal connection member 26 and the spacer member 40 as will be described later. The conductor 44 can be formed simultaneously in the fabrication of the conductive sheet 44a, and the thick metal in the upper layer can be connected to the electronic contact 16 by the conductor 44, as shown in Fig. 4. The second polymer layer 47 can be selectively formed on the element 4 and on the metal junction 26 to provide additional protection. Referring to Figures 12 through 23, there is shown a method of forming an inductive component or other passive component on a protective layer 21 in accordance with the present invention. As shown in Fig. 12, the substrate 80 is a dielectric layer located on the lower layer, and the material of the metal contact 81 is, for example, aluminum. The opening 82 can be formed by a patterning step through the protective layer 84, and the opening 82 can expose the metal contacts 81. For example, the polymer layer 86 of the polyimide may be formed on the protective layer 84 and the metal contact 81, and the polymer layer 86 such as the polyimide may be completed by spin coating, for example, or This can be done by screen printing, or it can be done by pressing the polymer dry film. Figure 13 is a diagram showing the process of forming the opening 87 of the polymer layer 86, wherein the maximum width of the opening 87 of the polymer layer 86 is greater than the maximum width of the opening 82 of the protective layer 84 (see Figure 12, Figure 12), opening 87 has a sloped side wall 85. At the beginning, 'the opening 87 of the polymer layer 86 has a vertical side wall 85'. However, after the hardening step, the side wall 85 will assume a slanted pattern, while the opening 87 may be in the form of a semi-tapered shape, while the side wall 85 The tilt angle is, for example, 45 degrees or more 'substantially between about 5 degrees and 6 degrees. Further, the angle of inclination of the side wall 85 may be as small as 20 degrees. In this embodiment, the 'large vias may be through the polymer layer 86, such as a poly-imine, and aligned with the opening 82' of the lower layer of the protective layer 84. And also connected to the sub-micron metal layer in the lower layer. The size of the via lines of the sub-micron metal may gradually increase as the sub-micron metal layer is oriented toward the wide metal level. 1342598 Continuing to refer to Fig. 13, there is shown a method and metal structure for forming a connection line and an inductor member on a protective layer in accordance with the present invention. Firstly, (4) forming an adhesion/barrier layer 88 by means of an extinguishing bond, the material of which includes a contact alloy, a titanium nitride compound, a neon or a nitrogen compound, and the thickness of the adhesion/barrier layer 88 is, for example, 500 Å. (angStrom) to 5000 angstroms. Next, a seed layer 90, such as gold, may be formed by sputtering to the adhesion/barrier layer, wherein the thickness of the seed layer 90 is, for example, between 300 angstroms and 3 angstroms. Referring to Figure 14, a thick metal layer 92 may be formed by electroplating, such as gold, wherein the thickness of the thick metal layer is, for example, > m between 1 and 20 microns. Before the electroplating process is performed, a thick photoresist 94 is formed, and the thickness of the photoresist 94 is greater than or equal to the thickness of the thick metal layer. Through the lithography step, the photoresist 94 exposes the seed layer 9〇, and then The thick metal layer 92 is formed by electroplating. After the electroplating process, the photoresist 94 can be removed, as shown in FIG. The adhesion/barrier layer 88 and the seed layer 90 can be removed by a thick film, as shown in Fig. 16. In the illustration, only one of the coils of the inductive component 40 is not shown, but it will be appreciated by those skilled in the art that the entire inductive component 40 can be completed in this step. As shown in Figs. 17 and 18, the thick metal layer 92 may be a portion of the region which is only filled in the opening 87. Thus, an inductance element having a high line density and a fine line can be designed. In the present embodiment, the size D of the opening 87 23 1342598 of the polymer layer 86 is, for example, about 15 microns. The gate pitch of the metal line of the inductor element 40 is as small as 4 microns. Therefore, patterning the n-metals located in the polymer layer 86 is also an important feature of the present invention. As described above, an adhesion/barrier screen 88 and a seed layer 9G such as gold may be formed by sputtering, and also formed as a photoresist %, such as ^
圖所示。接著可以電_方式形成比如是金的厚金屬層 92。之後,可轉細95去除,並且_掉先前位在級 95下方之黏著/阻障層88及種子層9〇,如第18圖所示。The figure shows. A thick metal layer 92, such as gold, can then be formed electrically. Thereafter, the fine 95 can be removed and the adhesive/barrier layer 88 and the seed layer 9 previously positioned below the level 95 are removed, as shown in FIG.
在本發明之另-實施例中,可以利用銅來作為位在保護 層上之金屬結射之厚金屬層的材質。·始之結構係如第 13圖所示’接著請參照第19圖,可以_雜的方式形成 比如是鉻或欽之黏著/阻障層⑽,其厚度比如是介於咖埃 到2000埃之間’接著’可以利用濺鑛的方式形成比如是銅之 種子層102,其厚度比如是介於2咖埃到⑽⑻埃之間。接 著’可以利用電鑛的方式形成比如是銅之厚金屬層1〇4,其 厚度比如是介於3微米到20微米之間,而可以利用光阻他 及傳統的微影製程定義出欲電鍍的區域。接著,可以選擇性 地利用電鍍的方式形成比如是鎳的金屬頂層1〇6,其中金屬 頂層106的厚度比如是介於oj微米到3微来之間。 請參照第20圖,接著可以將光阻94a去除並暴露出比如 是銅的種子層102。接著,可以利用比如是銅的厚金屬層1〇4 24 作為蝕刻罩蔽,並藉由蝕刻方式可以去除黏著/阻障層100 及比如是銅之種子層102,如第21圖所示。 如果有形成比如是鎳的金屬頂層1〇6,則在蝕刻黏著/阻 障層100及種子層1〇2的過程中,金屬頂層1〇6可以作為蝕 刻終止層’此時便可以使用對銅蝕刻速率較快的蝕刻劑來蝕 刻種子層102’如此可以減少厚金屬層1〇4之銅金屬的消耗。 在圖示中’僅繪示出電感元件4〇之其中一線圈,然而熟 悉該項技藝者應知’整個電感元件4〇可以在此步驟完成。 如第22圖及第23圖所示,厚金屬層104亦可以是僅填 入於開口 87中之部分區域,如厚金屬層1〇4填入於開口 87 中的部分厚金屬層92所示p如前所述,可以利用濺鍍的方 式,形成一黏著/阻障層1〇〇及比如是銅的種子層102,並且 還形成一光阻95a ’如第22圖所示。接著可以利用電鍍的方 式形成比如是銅的厚金屬層1〇4。之後,可以將光阻95a去 除,並且蝕刻掉黏著/阻障層1〇〇及種子層1〇2,如第23圖 所示。 請參照第5a圖’其金屬結構係如前所述’值得注意的 是,在本實施例中並未形成比如是聚醯亞胺之聚合物層於保 護層18上。電感元件l9a係直接形成在保護層18上,其中 用來形成電感元件19a之金屬線路的電阻值要愈低愈好,為 了達到上述目的’當在製作電感元件19a時,可以甩成比如 25 是金的厚金屬層。在上述之設計中,針對2· 4GHZ的應用,電 感兀件19a之品質參數可以從5提升至2〇。 如前所述,第5a圖之電感元件19a可以與其他的元件連 接,比如是與位在下層之接點連接,如第4圖所示,而電感 兀件19a之連接方向可以是“一上一下,,的結構,如第施 圖所示,或者電感元件19a之連接方向可以是“均為朝上” 的結構,如第24b圖所示。 而一聚合物層(未繪示)可以選擇性地形成於電感元件 19a 上。 另外’聚合物可以是形成在電感元件下,而不形成在 保護層上之其他地方,如此相較於面積較大之聚合物層,小 面積之聚合物塊具有較低的内應力,如第5b圖或第5c圖所 示’其分別繪示依照本發明形成於聚合物塊上之電感元件的 剖面示意圖及上視圖。每一聚合物塊上具有至少一電感元 件,其中第5c圖繪示第一電感元件40a及第二電感元件40b。 請參照第5b圖,聚合物塊20a之形成方式比如是先沈積 一聚合物層,然後再圖案化聚合物層,如此便形成聚合物塊 20a。而聚合物塊20a亦可以藉由網板印刷的方式所形成’或 是壓合乾膜而成。在形成聚合物塊20a之後,可以形成電感 元件40a、40b於聚合物塊20a上。 第5b圖之電感元件40a、40b之對外連接方法可以是如 1342598 則所述’其中電感兀件40b比如具有兩個朝下的接點彻、 43a ’其可以連接至電子接點16。*域元件他並不具有 : 接點,但是卻可以向上連接至外界電路,如前所述。 ,、 第5c圖係繪不依照本發明之電感元件的上視圖,而第 - 5b圖係在第5c圖中沿著剖面線5b-5b之剖面示意圖。如第 5c圖所示,聚合物塊20a之間係為相互隔離的,且聚合物塊 20a係僅形成在電感元件下,而其他未形成聚合物塊2〇a的 隹區域,保護層18可以暴露於外。 而另外的一聚合物保護層(未繪示)可以選擇性地形成在 電感元件40a、40b上。 而如第5b圖及第5c圖所示之聚合物塊亦可以形成在其 他的元件下,舉例而言,可以形成在比如是電阻元件及電容 元件之被動元件下。 第6a圖及第6b圖繪示依照本發明之另一較佳實施例。 # 如第6a圖所示’介電層聚合物層47係位在底層線圈60與上 層線圈62之間,而聚合物層20、47、64可以是利用如前所 述的材質所製成。而開口 66係位在最上層之聚合物層64中, 可以暴露出上層線圈62。 第6b圖繪示依照本發明另一較佳實施例之晶片結構的 剖面示意圖。其中底層線圈60可以直接形成在保護層18上。 第6c圖纟會示電感元件19a係為螺線管(solenoid)形式之 27 立體示意圖,其中電感元件19a係形成在保護層18上,電感 凡件19a係包括導通孔金屬23、底層金屬結構25及頂層金 屬結構27,其t導通孔金屬23係位在厚聚合物層聚合物層 20中,其係為垂直的金屬結構。透過導通孔金屬23可以使 底層金屬結構25及頂層金屬結構27電性連接。 第6d圖繪示電感元件19a係為螺線管形式之立體示意 圖,其中電感元件19a係形成在第一聚合物層29上,而電感 元件19a具有導通孔金屬23,位在形成於第一聚合物層29 上之第二聚合物層中。 第6e圖係繪示第6c圖及第記圖中螺線管形式之電感元 件的上視示意圖’其中透過導通孔金屬23可以使底層金屬結 構25及頂層金屬結構27電性連接。 第6f圖繪示第6c圖到第6e圖中之電感元件的剖面示意 圖,其中第6f圖係繪示第6e圖中沿著剖面線6f_6f之剖面 不意圖。 請參照第6g圖及第6h圖,其繪示依照本發明之超環面 (toroidal)形式之電感元件的示意圖,其中電感元件係類似 環繞形狀之螺線圈。在第6g圖中,其繪示電感元件之立體示 意圖,其中電感元件68係包括導通孔金屬23a、底層金屬結 構25a及頂層金屬結構27a ’而導通孔金屬23a係連接底層 金屬結構25a及頂層金屬結構27a。 28 1342598 第_會示第6g圖中環面(t〇r〇idai)形式之電感元件 68的上視不意圖。而電感元件68之繞線特點已在之前的較 佳實施例中闡述,在此便不再資述。 第7a圖緣示依照本發明<電容元件形成在基底半導體 基底ίο上的剖面示意圖,其愧緣層係位在賴層ΐδ上。 導電連接、線路層金屬/介電層14及接點電子接點16係位在基 底半導體基底10上,且賴層18係形成在導電連接線路層 金屬/介電層14上’而保護層18具有開σ,可以暴露出接點 電子接點16。 熟習該項技藝者應知,電容元件係由一下電極、一電容 介電層及一上電極所構成,而電容介電層係位在上電極與下 電極之間。第7a圖所示之電容元件具有一下電極42、一電 容介電層46及一上電極45。上電極45及下電極42比如是 利用如前所述之電鍍方式形成金或銅之厚金屬層而完成,而 可以選擇性地形成比如是聚醯亞胺之聚合物保護層於電容元 件上。電容元件之接點對外連接方式比如是如前所述,(電容 元件之接點比如是均朝下連接、一上一下的連接或是均朝上 連接)。 .... . - 下電極42的厚度比如是介於〇. 5微米到20微米之間, 介電層46的厚度比如是介於500埃到50000埃之間,而上電 極45的厚度比如是介於〇.5徵米到20微米之間。 29 1342598 如第7a圖所不之在保護層上形成電容元件之結構,具有 下列優點: : 1·可以減錢容胁與下树基底之·寄生電容。 2. 抑_厚絲層軸電容元件之電極,如此可以減 ,. 少、電容兀件之電阻值,特別是可以應用在無線的領域中。 3. 可以形成高介電常數續質錢容祕之上電極與下 躲之間’其材質比如是二氧化鈦(Ti〇2)、五氧化二鈕 • (Ta2〇5)、高分子聚合物、氮矽化合物(S·)或氧矽化合物 (Si〇2)等,如此可以提高電容元件之電容值。 而如第7a圖所示之電容元件亦可以形成在位於保護層 18上之聚合物層上,其概念係類似如第4圖所述之將電感元 件40形成在位於保護層is上之聚合物層2〇上的結構。 介電層46係為面介電常數之材質,比如是利用化學氣象 沈積的方式沈積氮矽化合物(以3队)、四乙烷基氧矽甲烷 籲 (TEGS)、五氧化二|5(硫)、二氧化鈦(TiQ2)、鈦酸鐵SrTi〇3) 或氮氧矽化合物(Si〇N)等。 第7b圖及第7c圖繪示電容元件之剖面示意圖。如第7b 圖所不,厚聚合物層聚合物層20可以形成在保護層18上, 並且透過圖案化製程’可以使厚聚合物層聚合物層2〇暴露出 接點電子接點16,而聚合物層2〇之導通孔的直徑係小於保 濩層開口之直徑。然而’在輯佳的情況下,聚合物層20之導 30 巧厶乃δ 通孔係與保護層開口連通,而聚合物層20之導通孔的直徑係 大於保護層開口之直徑。藉由厚聚合物層聚合物層20的配 置可以使下電極42、上電極45及介電層46之配置向上移 動約等於聚合婦2G之厚賴雜,如此電容元件配置可以 在更雜基底的地方。如前所述,比如是_亞胺之聚合物 層20的厚度可以是介於2微米到150微米之間。如此,電容 元件與位在下廣之金屬線路結構及梦基底之間的距離可以增 加,故可以大幅降低寄生電容的發生。 第7a圖及第7c圖均繪示電容元件之接點係向下連接, 而電容7L件亦可以是-上—下的連接方式,如第25圖所示, 或是電容元件均是朝上連接,如第24b圖所示的概念。 如第7a圖至第7c圖所示之電容元件之上電極45可以經 由位在上電極45上之聚合物層35之開口 37,向上與一電路 電性連接’如第25圖之剖面結構所示。其中介電層聚合物層 35係形成在電容元件之上電極45上,經由貫穿介電層聚合 物層35之開口 37可以暴露出電容元件之上電極45,藉以使 上電極45與一外部線路電性連接。 而一聚合物保護層(未繪示)可以選擇性地形成在如第 7a圖至第7c圖所示之電容元件上。 第δ圖繪示基底半導體基底1〇的剖面示意圖’基底半導 體基底10上形成有一保護層18,而電阻元件48係位在保護 31 1342598 層18上。熟習該項技藝者應知,電阻元件48係由能夠提供 電性阻值之材質所構成’且電流能夠留流經該材質。電阻元 件48之材質比如是鈕氮化合物(TaN)、鎳鉻合金(NiCr)、鎳 錫合金(NiSn)、鎢(W)、鈦鶴合金(Tiw)、鈦氮化合物(TiN)、 絡(Cr)、欽(Ti)、鎳(Ni)或鈕矽化合物(TaSi)等。在上述的 這些材質中’鎳鉻合金能夠提供最佳的電阻溫度係數 (Temperature Coefficient of Resistance) ,可以小至5 ppm/ C。電阻元件48之長度、厚度及寬度可以依照不同的應 用而設計。而可以應用如第7a圖至第7c圖所示之配置電容 元件的概念’來配置如第8圖所示之電阻元件48,其中電阻 元件48係形成在保護層18上。 第9a圖及第9b圖繪示依照本發明形成在厚聚合物層聚 。物層20上之電阻元件48的剖面示意圖,其中電阻元件48 可以與接點電子接點16連接。藉由增加電阻元件與基底之間 的距離(所增加的距離係大致上等於聚合物層2〇的厚度),可 乂降低電阻元件與基底之間的寄生電容效應,如此可以改善 電阻元件雜能(由於可叫少私電容的損耗,故可以提升 在高頻運作下的電性效能)。 如第8圖、第9a目及第%圖所示之電阻元件48的接點 均是向下接。然而電阻元件48亦可以是—上—下的連接, 如第26圖所示’或是電阻元件48之接點均是朝上連接,其 32 可以參考如第24b圖中電感元件40均是朝上連接的概念。 而另—聚合物層可以選擇性地形成在如第8圖、第9a 獨及第9b圖所示之電阻元件48上,藉以保護電阻元件48。 請參照第10圖及第11圖,其繪示依照本發明在保護層 上之另一種製程。在本實施例中,可以藉由形成凸塊使接點 電子接點16與位在上面之電子元件電性連接,比如是與已製 作完成之電感元件、電容元件、電阻元件或是其他的被動元 件電性連接。而連接金屬凸塊底層金屬5〇可以形成在聚合物 層20之開口内’其中聚合物層20之開口係對準於較小之保 護層18的開口’如此連接金屬凸塊底層金屬50可以與接點 電子接點16連接,作為凸塊底層金屬(UBM)之用。利用傳統 的電錄製程、植球製程或網板印刷製程,可以形成凸塊52 於凸塊底層金屬50上’而在助銲劑形成於凸塊52上之後, 可以進行回銲的步驟。接著,已製作完成的電子元件54可以 連接到凸塊52上’其中已製作完成的電子元件54具有銲料 53,如此可以提升接合性。 上述之製程係類似於常應用在電子元件與印刷電路板接 合的表面黏著技術。已製作完成的電子元件54比如是電感元 件、電容元件或是電阻元件。 第11圖繪示利用凸塊56及凸塊底層金屬50將已製作完 成的電子元件54直接形成於保護層18上的結構。 33 由於已製作完成的電子元件54並不是如習知技術係形 成在印刷電路板上,誠如第10誠第u騎示之已製作 完成的電子树54具有健的效能,且成本跡高。 而凸塊底層金屬50可以是如本發明之第12圖到第23 圖所不之金聽構,然而若是利驗作為厚麵層時凸塊 底層金屬50的厚度可以是介於〇.丨微米到2〇微米之間,在 較佳的情況下,凸塊底層金屬50係為較薄的尺寸,如此在製 作7G成之後’可以避免在凸塊底層金屬50之介面附近的凸塊 材質具有南濃度的金β 上述之被動元件之配置方式至少具有下列的優點: 1. 由於已製作完成的電子元件可以提供適當的參數,並 且可以接合在靠近晶片中線路的位置,因此藉由本發明之被 動元件的設計概念可以達到真正的系統化晶片的表現。 2. 由於已製作完成的電子元件可以接合在靠近晶片中線 路的位置,因此能夠減少寄生現象的發生。 3. 在本發明中,由於可以選擇具有適當設計參數之已製 作完成的電子元件裝配在保護層上,此種設計可以減少已製 作完成的電容元件及已製作完成的電感元件之電阻效應,為 了更清楚的說明’下面有針對習知技術與本發明作比較說明: 習知技術係利用細的金屬導線來製作電感元件,而若是 為了要減少電阻效應,必須製作較寬的線圈,則會使得電感 34 丄^42598 元件之表面面積增加。另外,習知技術會具有較大之電感元 件之寄生電容的現象’並且在基底内會有嚴重的渴電流損耗。 然而本發明’係採祕金屬層作為線路,因此可以減少 電阻效應。另外,聚合物還可以墊在被動元件與下層结構^ 間’如此可以減少寄生效應,由於寄生效應的減少會使得 共振頻率提高,故適合高頻電路的操作。 雖然本發明已以較佳實施例揭露如上,然其並非用以限 定本發明,任何熟習此技藝者,在不脫離本發明之精神和範 圍内’當可作錄之更動與潤飾,因此本發明之隔離範圍當 視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 第1騎示依照美國專利公告第6,戰916號之連接線 路結構的剖面示意圖。 第2圖纷不依照本發明之電感元件形成在厚聚酿亞胺層 上之剖面示意圓。 第3圖繪示依照本發明之電感元件之上視示意圖。 第4圖緣示依照本發明之晶片結構的剖面示意圖,其中 電感元件係$成在厚聚醢亞胺層上,並且藉由—導電材質可 以避免電感树影響到位在下層的祕底。 第如圖繪不依照本發明之電感元件形成在保護層上之 剖面示意圖。 第5b圖綠示依照本發明之多個電感元件形成在比如是 35 1342598 南分子聚合物之纟巴緣層上的剖面示意圖。 第5c圖繪不依照本發明之多個電感元件形成在比如是 兩分子聚合物之絕緣層上的上視圖。 第6a圖繪示依照本發明之變壓器形成在比如是高分子 聚合物之麟層上触面示如,射絕緣層躲在保護層 上0 第6b圖繪示依照本發明之變壓器的剖面示意圖,其中位 在下方的線獨係位在保護層上。 第6c圖繪不依照本發明另一較佳實施例之螺線管形狀 的電感元狀立獅賴,財魏元件雜在保護層上。 第6d圖缚不依照本發明另—較佳實施例之螺線管形狀 的電感元件之立體示意圖’其巾電感元件餘在比如是高分 子聚合物之絕緣層上’而絕緣層係位在健層上。 第6e圖係為第6c圖及第6d圖之電感元件的上視示意 圖。 第6f圖係為第6e圖中沿著剖面線6f 6f之剖面示意圖。 第6g圖繪示依照本發明之環形線圈形狀的電感元件之 立體示意圖。 第6h ’示第6g圖中環形線圈形狀的電感元件之上視 不意圖。 第7a圖繪示依照本發明之電容元件形成在保護層上的 36 Ϊ342598 剖面示意圖。In another embodiment of the invention, copper may be utilized as the material for the thick metal layer of the metal deposited on the protective layer. · The structure of the beginning is as shown in Fig. 13 'Next, please refer to Figure 19, which can be formed in a way such as chrome or a bonding/barrier layer (10), the thickness of which is, for example, between 20,000 Å and 2,000 Å. The 'then' can be formed by sputtering, for example, a copper seed layer 102 having a thickness of, for example, between 2 ga and (10) (8) angstroms. Then, a thick metal layer such as copper can be formed by means of electric ore, and the thickness thereof is, for example, between 3 micrometers and 20 micrometers, and the photoresist can be defined by the photoresist and the conventional lithography process. Area. Next, a metal top layer 1 比如 6 such as nickel may be selectively formed by electroplating, wherein the metal top layer 106 has a thickness of, for example, between oj and 3 micro. Referring to Figure 20, the photoresist 94a can then be removed and exposed to a seed layer 102 such as copper. Next, a thick metal layer 1 〇 4 24 such as copper may be used as an etch mask, and the adhesion/barrier layer 100 and the seed layer 102 such as copper may be removed by etching, as shown in FIG. If a metal top layer 1〇6 such as nickel is formed, the metal top layer 1〇6 can serve as an etch stop layer during the etching of the adhesion/barrier layer 100 and the seed layer 1〇2. Etching the faster etchant to etch the seed layer 102' can reduce the consumption of copper metal of the thick metal layer 1〇4. In the illustration, only one of the inductor elements 4A is shown, but it is known to those skilled in the art that the entire inductor element 4 can be completed in this step. As shown in FIGS. 22 and 23, the thick metal layer 104 may also be a portion filled only in the opening 87, as shown by a portion of the thick metal layer 92 in which the thick metal layer 1〇4 is filled in the opening 87. As previously described, an adhesion/barrier layer 1 and a seed layer 102 such as copper may be formed by sputtering, and a photoresist 95a' may also be formed as shown in FIG. A thick metal layer 1 比如 4 such as copper can then be formed by electroplating. Thereafter, the photoresist 95a can be removed, and the adhesion/barrier layer 1 and the seed layer 1〇2 are etched away, as shown in Fig. 23. Referring to Figure 5a, the metal structure is as described above. It is noted that a polymer layer such as polyimide is not formed on the protective layer 18 in this embodiment. The inductive element 19a is formed directly on the protective layer 18, wherein the lower the resistance of the metal line used to form the inductive element 19a, the better, in order to achieve the above purpose, when the inductive element 19a is fabricated, it can be formed, for example, 25 A thick metal layer of gold. In the above design, the quality parameter of the electronic component 19a can be raised from 5 to 2 for the application of 2.4 GHz. As mentioned above, the inductive component 19a of FIG. 5a can be connected to other components, such as a contact located at a lower layer, as shown in FIG. 4, and the connecting direction of the inductive component 19a can be "one." The structure of the structure, as shown in the figure, or the connection direction of the inductance element 19a may be a "all upwards" structure, as shown in Fig. 24b. A polymer layer (not shown) may be selected. Formed on the inductive component 19a. In addition, the polymer may be formed under the inductive component and not formed elsewhere on the protective layer, so that the polymer block of a small area is larger than the polymer layer having a larger area. Having a lower internal stress, as shown in FIG. 5b or FIG. 5c, which respectively show a cross-sectional view and a top view of an inductance element formed on a polymer block according to the present invention. Each polymer block has at least one Inductive component, wherein FIG. 5c illustrates the first inductive component 40a and the second inductive component 40b. Referring to FIG. 5b, the polymer block 20a is formed by depositing a polymer layer and then patterning the polymer layer. So shaped The polymer block 20a can be formed by screen printing or by pressing a dry film. After forming the polymer block 20a, the inductive elements 40a, 40b can be formed on the polymer block. 20a. The external connection method of the inductive elements 40a, 40b of FIG. 5b may be as described in 1342598, wherein the inductive element 40b has, for example, two contacts facing downward, 43a 'which can be connected to the electronic contacts 16 * Domain element does not have: a contact, but can be connected up to the external circuit, as described above, , Figure 5c depicts a top view of the inductive component not in accordance with the present invention, and the -5b system A cross-sectional view along section line 5b-5b in Fig. 5c. As shown in Fig. 5c, the polymer blocks 20a are isolated from each other, and the polymer block 20a is formed only under the inductance element, and the other The germanium region of the polymer block 2〇a is not formed, and the protective layer 18 may be exposed to the outside. Another polymer protective layer (not shown) may be selectively formed on the inductive elements 40a, 40b. The polymer block shown in Figure 5c can also be shaped Other components, for example, may be formed under passive components such as resistive components and capacitive components. Figures 6a and 6b illustrate another preferred embodiment in accordance with the present invention. #如图6a The dielectric layer polymer layer 47 is shown to be between the bottom layer coil 60 and the upper layer coil 62, while the polymer layers 20, 47, 64 may be made of the material described above. In the uppermost polymer layer 64, the upper layer coil 62 may be exposed. Fig. 6b is a cross-sectional view showing the structure of the wafer in accordance with another preferred embodiment of the present invention, wherein the bottom layer coil 60 may be formed directly on the protective layer 18. Figure 6c shows that the inductive component 19a is a perspective view of a solenoid in the form of a solenoid, wherein the inductive component 19a is formed on the protective layer 18, and the inductive component 19a includes the via metal 23 and the underlying metal structure. 25 and top metal structure 27, wherein the t-via metal 23 is in the thick polymer layer polymer layer 20, which is a vertical metal structure. The underlying metal structure 25 and the top metal structure 27 can be electrically connected through the via metal 23. Figure 6d is a perspective view showing the inductance element 19a in the form of a solenoid, wherein the inductance element 19a is formed on the first polymer layer 29, and the inductance element 19a has the via hole metal 23, which is formed in the first polymerization. In the second polymer layer on the layer 29. Fig. 6e is a top plan view showing the inductor element in the form of a solenoid in Fig. 6c and the figure, wherein the underlying metal structure 25 and the top metal structure 27 are electrically connected through the via metal 23. Fig. 6f is a cross-sectional view showing the inductance elements of Figs. 6c to 6e, wherein Fig. 6f is a cross-sectional view taken along line 6f_6f of Fig. 6e. Referring to Figures 6g and 6h, there are shown schematic views of a toroidal form of an inductive component in accordance with the present invention, wherein the inductive component is similar to a wrap around a shape. In Fig. 6g, a schematic perspective view of the inductive component is shown, wherein the inductive component 68 includes a via metal 23a, an underlying metal structure 25a and a top metal structure 27a', and the via metal 23a is connected to the underlying metal structure 25a and the top metal. Structure 27a. 28 1342598 The first view of the inductive component 68 in the form of a torus (t〇r〇idai) in the 6th diagram is not intended. The winding characteristics of the inductive component 68 have been described in the prior preferred embodiment and will not be described here. Fig. 7a is a schematic cross-sectional view showing the formation of a capacitor element on a base semiconductor substrate ίο according to the present invention, the rim layer of which is located on the layer ΐδ. The conductive connection, the wiring layer metal/dielectric layer 14 and the contact electronic contact 16 are on the base semiconductor substrate 10, and the Laminated layer 18 is formed on the conductive connection layer metal/dielectric layer 14 and the protective layer 18 With an open σ, the contact electronic contact 16 can be exposed. As is well known to those skilled in the art, the capacitive element is composed of a lower electrode, a capacitor dielectric layer and an upper electrode, and the capacitor dielectric layer is located between the upper electrode and the lower electrode. The capacitive element shown in Fig. 7a has a lower electrode 42, a dielectric dielectric layer 46 and an upper electrode 45. The upper electrode 45 and the lower electrode 42 are formed, for example, by forming a thick metal layer of gold or copper by electroplating as described above, and a polymer protective layer such as polyimide may be selectively formed on the capacitor element. The contact of the capacitive element to the external connection is as described above, (the contact of the capacitive element is, for example, a downward connection, a top-to-bottom connection or an upward connection). The thickness of the lower electrode 42 is, for example, between 微米. 5 μm and 20 μm, and the thickness of the dielectric layer 46 is, for example, between 500 Å and 50,000 Å, and the thickness of the upper electrode 45 is, for example. It is between 〇.5 levy to 20 microns. 29 1342598 If the structure of the capacitive element is formed on the protective layer as shown in Fig. 7a, it has the following advantages: 1. The loss of the memory and the parasitic capacitance of the underlying substrate can be reduced. 2. _ _ thick wire layer of the capacitor element of the electrode, so can reduce, less, the resistance value of the capacitor component, especially in the field of wireless. 3. It can form a high dielectric constant and continue to replenish the money between the electrode and the lower hiding. The material is, for example, titanium dioxide (Ti〇2), pentoxide oxide (Ta2〇5), high molecular polymer, nitrogen. The ruthenium compound (S·) or the oxonium compound (Si〇2) or the like can increase the capacitance value of the capacitor element. The capacitive element as shown in Fig. 7a can also be formed on the polymer layer on the protective layer 18, the concept of which is similar to that of the polymer element 40 formed on the protective layer is as described in Fig. 4. The structure on layer 2〇. Dielectric layer 46 is a material of surface dielectric constant, such as deposition of nitrogen bismuth compounds (3 groups) by chemical meteorological deposition, tetraethane oxymethane (TEGS), pentoxide 5 | ), titanium dioxide (TiQ2), iron titanate SrTi〇3) or oxynitride compound (Si〇N). 7b and 7c are schematic cross-sectional views showing the capacitor element. As shown in FIG. 7b, a thick polymer layer polymer layer 20 may be formed on the protective layer 18, and the thick polymer layer polymer layer 2 may be exposed through the patterning process to expose the contact electronic contacts 16 The diameter of the via of the polymer layer 2 is smaller than the diameter of the opening of the layer. However, in the case of a good combination, the conductive layer 20 is in contact with the opening of the protective layer, and the diameter of the via hole of the polymer layer 20 is larger than the diameter of the opening of the protective layer. By the configuration of the thick polymer layer polymer layer 20, the arrangement of the lower electrode 42, the upper electrode 45 and the dielectric layer 46 can be moved upwards to be equal to the thickness of the polymer 2G, so that the capacitive element configuration can be on a more heterogeneous substrate. local. As previously mentioned, the thickness of the polymer layer 20, such as _imine, can be between 2 microns and 150 microns. In this way, the distance between the capacitor element and the metal wiring structure and the dream substrate can be increased, so that the occurrence of parasitic capacitance can be greatly reduced. Figures 7a and 7c show that the contacts of the capacitive element are connected downwards, and the capacitor 7L can also be connected in an up-down manner, as shown in Figure 25, or the capacitive elements are facing upwards. Connect, as shown in Figure 24b. The upper electrode 45 of the capacitive element as shown in FIGS. 7a to 7c can be electrically connected to a circuit via the opening 37 of the polymer layer 35 on the upper electrode 45, as shown in the cross-sectional structure of FIG. Show. The dielectric layer polymer layer 35 is formed on the upper electrode 45 of the capacitor element, and the upper electrode 45 of the capacitor element is exposed through the opening 37 of the polymer layer 35 of the dielectric layer, so that the upper electrode 45 and an external line are formed. Electrical connection. A polymer protective layer (not shown) can be selectively formed on the capacitor elements as shown in Figs. 7a to 7c. The δth diagram shows a schematic cross-sectional view of the base semiconductor substrate 1'. A protective layer 18 is formed on the base semiconductor substrate 10, and the resistive element 48 is tied to the layer 31 of the protective 31 1342598. As will be appreciated by those skilled in the art, the resistive element 48 is constructed of a material that provides electrical resistance and current can flow through the material. The material of the resistive element 48 is, for example, a nitrogen compound (TaN), a nickel-chromium alloy (NiCr), a nickel-tin alloy (NiSn), a tungsten (W), a titanium-titanium alloy (Tiw), a titanium nitride compound (TiN), and a complex (Cr). ), Chin (Ti), nickel (Ni) or button compound (TaSi). Among the above materials, 'nickel-chromium alloys provide the best temperature coefficient of resistance, which can be as small as 5 ppm/C. The length, thickness and width of the resistive element 48 can be designed for different applications. Instead, the resistive element 48 as shown in Fig. 8 can be configured by applying the concept of arranging capacitive elements as shown in Figs. 7a to 7c, wherein the resistive element 48 is formed on the protective layer 18. Figures 9a and 9b illustrate the formation of a thick polymer layer in accordance with the present invention. A schematic cross-sectional view of resistive element 48 on object layer 20, wherein resistive element 48 can be coupled to contact electronic contact 16. By increasing the distance between the resistive element and the substrate (the increased distance is substantially equal to the thickness of the polymer layer 2〇), the parasitic capacitance effect between the resistive element and the substrate can be reduced, thus improving the resistance of the resistive element. (Because the loss of the private capacitor can be called, the electrical performance under high frequency operation can be improved). The contacts of the resistive element 48 as shown in Fig. 8, Fig. 9a and Fig. % are all connected downward. However, the resistive element 48 can also be an up-down connection, as shown in FIG. 26 or the contacts of the resistive element 48 are connected upwards, and the 32 can refer to the inductive component 40 as shown in FIG. 24b. The concept of connection. The other polymer layer can be selectively formed on the resistive element 48 as shown in Fig. 8, the 9a and 9b, thereby protecting the resistive element 48. Referring to Figures 10 and 11, there is shown another process on the protective layer in accordance with the present invention. In this embodiment, the contact electronic contact 16 can be electrically connected to the electronic component located thereon by forming a bump, such as an inductive component, a capacitive component, a resistive component or other passive components. The components are electrically connected. And connecting the metal bump underlying metal 5〇 can be formed in the opening of the polymer layer 20, wherein the opening of the polymer layer 20 is aligned with the opening of the smaller protective layer 18, so that the metal bump underlying metal 50 can be connected with The contact electronic contacts 16 are connected for use as bump underlying metal (UBM). The step of reflowing can be performed after the flux is formed on the bumps 52 by a conventional electrical recording process, a ball placement process, or a screen printing process. Next, the finished electronic component 54 can be attached to the bump 52. The electronic component 54 that has been fabricated has solder 53 so that the bondability can be improved. The above process is similar to the surface bonding technique commonly used in the bonding of electronic components to printed circuit boards. The finished electronic component 54 is, for example, an inductive component, a capacitive component or a resistive component. Fig. 11 is a view showing the structure in which the completed electronic component 54 is directly formed on the protective layer 18 by using the bump 56 and the bump underlayer metal 50. Since the electronic component 54 that has been fabricated is not formed on a printed circuit board as in the prior art, the electronic tree 54 which has been completed as shown in the 10th is a healthy performance and has a high cost. The bump underlayer metal 50 may be a gold auditory structure as shown in Figures 12 to 23 of the present invention. However, if it is a thick mask, the thickness of the under bump metal 50 may be between 〇. Between 2 〇 micrometers, in the preferred case, the under bump metal 50 is a relatively thin size, so that after the 7G is formed, the bump material near the interface of the under bump metal 50 can be prevented from having a south. The concentration of gold β The configuration of the passive components described above has at least the following advantages: 1. Passive components of the present invention are provided because the fabricated electronic components can provide appropriate parameters and can be bonded to locations near the circuitry in the wafer. The design concept can achieve the performance of a truly systematic wafer. 2. Since the fabricated electronic component can be bonded to a position close to the line in the wafer, the occurrence of parasitic phenomena can be reduced. 3. In the present invention, since the fabricated electronic component having the appropriate design parameters can be selected to be mounted on the protective layer, such a design can reduce the resistance effect of the fabricated capacitor component and the completed inductor component, in order to reduce the resistance effect of the fabricated capacitor component and the completed inductor component. More clearly, 'the following is a description of the prior art and the present invention: The prior art uses a thin metal wire to make an inductive component, and if it is to reduce the resistance effect, a wider coil must be made, which would The surface area of the inductor 34 丄^42598 component increases. In addition, conventional techniques can have a phenomenon of parasitic capacitance of a large inductive component and have a severe thirst current loss in the substrate. However, the present invention uses a metal layer as a line, so that the resistance effect can be reduced. In addition, the polymer can also be placed between the passive component and the underlying structure. Thus, the parasitic effect can be reduced, and the resonance frequency can be increased due to the reduction of the parasitic effect, so that it is suitable for the operation of the high-frequency circuit. While the present invention has been described above in terms of the preferred embodiments thereof, it is not intended to limit the invention, and the invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of isolation is subject to the definition of the scope of the patent application. [Simple description of the drawings] The first ride shows a cross-sectional view of the connection line structure according to US Patent Publication No. 6, No. 916. Fig. 2 shows a schematic cross-sectional circle formed on the thick polyimide layer in accordance with the inductive component of the present invention. Figure 3 is a top plan view of an inductive component in accordance with the present invention. Figure 4 is a schematic cross-sectional view of the wafer structure in accordance with the present invention, wherein the inductive component is formed on the thick polyimide layer and the conductive material is used to prevent the inductive tree from affecting the underlying layer. The cross-sectional view of the inductive component not in accordance with the present invention formed on the protective layer is shown. Figure 5b is a schematic cross-sectional view showing the formation of a plurality of inductive elements in accordance with the present invention on a layer of a barrier layer such as 35 1342598 South Molecular Polymer. Figure 5c depicts a top view of a plurality of inductive elements not in accordance with the present invention formed on an insulating layer such as a two molecule polymer. Figure 6a is a cross-sectional view showing the transformer according to the present invention formed on a layer of a polymer such as a polymer layer, wherein the insulating layer is hidden on the protective layer. The line in the lower position is on the protective layer. Fig. 6c is a diagram showing the shape of a solenoid in the shape of a solenoid which is not in accordance with another preferred embodiment of the present invention. Figure 6d is a perspective view of a solenoid-shaped inductive component not in accordance with another embodiment of the present invention, wherein the inductive component of the towel is on an insulating layer such as a polymer, and the insulating layer is in the health On the floor. Figure 6e is a top plan view of the inductive components of Figures 6c and 6d. Figure 6f is a schematic cross-sectional view along section line 6f 6f in Figure 6e. Fig. 6g is a perspective view showing the inductance of the toroidal coil in accordance with the present invention. The 6h'' indicates that the inductive element of the toroidal coil shape in Fig. 6g is not intended. Fig. 7a is a schematic cross-sectional view showing the 36 Ϊ 342598 formed on the protective layer by the capacitor element according to the present invention.
第7a-7b至7c圖繪示依照本發明之電 如是高分子聚合物之絶緣層上的剖面示意圖 位在保護層上。 容元件形成在比 ’其中絕緣層係7a-7b to 7c are schematic cross-sectional views on the insulating layer of the polymer according to the present invention on the protective layer. The capacitive element is formed in the ratio
第8圖繪示依照本發明之電阻元件形成在保護層上 面示意圖。 ° 第9a圖及帛%圖繪示依照本發明之電阻元件形成 在比如是高分子聚合物之厚絕緣層上__意圖,其中厚 絕緣層係位在保護層上。Figure 8 is a schematic view showing the formation of a resistive element in accordance with the present invention on a protective layer. The Fig. 9a and 帛% diagrams show that the resistive element according to the present invention is formed on a thick insulating layer such as a polymer, in which the thick insulating layer is tied to the protective layer.
第10圖繪示依照本發明之晶片結構的剖面示意圖,盆中 已製作完成的電子元件係利用表面黏紐雜著於比如是高 分子聚合物之厚絕緣層上。 第11 _錄照本發明之晶片結構的剖面示意圖,其中 已製作完成的電子元件_絲轉著技術黏著於保護層 上0Figure 10 is a schematic cross-sectional view of a wafer structure in accordance with the present invention in which the fabricated electronic components are interspersed with a thick insulating layer such as a high molecular polymer using surface bonds. 11th is a schematic cross-sectional view of the wafer structure of the present invention, in which the completed electronic component _ wire transfer technology is adhered to the protective layer.
第12圖至第18 _示依照本發明以金為材質之金屬結 構的抽’其巾金屬結構係穿過比如是高分子聚合物 之絕緣層。 第19圖至第23圖繪示依照本發明以銅為材質之金屬結 冓的面示意圖,其中金屬結構係穿過比如是高分子聚合物 之絕緣層。 37 1342598 第24a圖至第24c圖繪示依照本發明另一種連接電感元 件的方法。 第25圖及第26圖分別繪示依照本發明另一種連接電容 * 元件及電阻元件的方法。 【主要元件符號說明】 10 :矽基底半導體基底 11 :電晶體 12 :内部介電層 13 :金屬連線 • 14 :金屬/介電層 16 :電子接點 18 :保護層 19 :開口 . 19a :電感元件 20 :聚合物層 22 :開口 20a :聚合物塊 23 :導通孔金屬 23a :導通孔金屬 25:底層金屬結構 25a :底層金屬結構 27 :頂層金屬結構 27a :頂層金屬結構 • 26 :線路金屬連接線路 28 :線路金屬連接線路 29 :第一聚合物層 22 :開口 ' 30 :路徑 32 :路徑 - 34 :路徑 35 :介電層聚合物層 36 :開口 36a :開口接點開口 - - · ... · ... 36b:接點開口 37 :開口 . .· . · ' : ί 38 :開口 38a :開口接點開口 38b :接點開口 39 :接點 38 1342598 40 :電感元件 40a :第一電感元件 40b :第二電感元件 40c :電感元件 41 :接點 41a :接點 j· 0 42 :下電極 43 :接點 . 43a :接點 44 :導體 44a :導電片 45 :上電極 46 :介電層 47 :第二聚合物層 • 48 :電阻元件 50 :連接金屬凸塊底層金屬 52 :凸塊 53 :銲料 54 :已製作完成的電子元件 56 :凸塊 60 :底層線圈 62 :上層線圈 64 :聚合物層 66 :開口 68 :電感元件 80 :基底 81 :金屬接點 • 82 :開口 84 :保護層 85 :侧壁 86 :聚合物層 87 :開口 88 :黏著/阻障層 89 :延伸線路 90 :種子層 - 92 :厚金屬層 94 :光阻 4 94a :光阻 95 :光阻 4 i 95a :光阻 100 :黏著/阻障層 39 1342598 102 :種子層 104 :厚金屬層 106 :金屬頂層Figs. 12 to 18 show the metal structure of the metal material in accordance with the present invention. The metal structure of the metal is passed through an insulating layer such as a polymer. 19 to 23 are schematic views showing the surface of a metal crucible made of copper in accordance with the present invention, wherein the metal structure is passed through an insulating layer such as a polymer. 37 1342598 Figures 24a through 24c illustrate another method of connecting an inductive component in accordance with the present invention. 25 and 26 respectively illustrate another method of connecting a capacitor* element and a resistor element in accordance with the present invention. [Main component symbol description] 10: germanium base semiconductor substrate 11: transistor 12: inner dielectric layer 13: metal wiring • 14: metal/dielectric layer 16: electronic contact 18: protective layer 19: opening. 19a: Inductive element 20: polymer layer 22: opening 20a: polymer block 23: via metal 23a: via metal 25: underlying metal structure 25a: underlying metal structure 27: top metal structure 27a: top metal structure • 26: line metal Connection line 28: line metal connection line 29: first polymer layer 22: opening '30: path 32: path - 34: path 35: dielectric layer polymer layer 36: opening 36a: open contact opening - - . .. · ... 36b: contact opening 37: opening. . . . . ' : ί 38 : opening 38a : open contact opening 38b : contact opening 39 : contact 38 1342598 40 : inductive element 40a : first Inductive component 40b: second inductive component 40c: inductive component 41: contact 41a: contact j·0 42: lower electrode 43: contact. 43a: contact 44: conductor 44a: conductive sheet 45: upper electrode 46: Electrical layer 47: second polymer layer • 48: resistance element 50: connecting metal bump underlying metal 52: bump 53: solder 54: fabricated electronic component 56: bump 60: bottom layer coil 62: upper layer coil 64: polymer layer 66: opening 68: inductive element 80: substrate 81: metal contact • 82: opening 84: protective layer 85: side wall 86: polymer layer 87: opening 88: adhesion/barrier layer 89: extension line 90: seed layer - 92: thick metal layer 94: photoresist 4 94a : photoresist 95 : photoresist 4 i 95a : photoresist 100 : adhesion / barrier layer 39 1342598 102 : seed layer 104 : thick metal layer 106 : metal top layer