TWI325186B - Led chip package structure using ceramic material as a substrate - Google Patents

Led chip package structure using ceramic material as a substrate Download PDF

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Publication number
TWI325186B
TWI325186B TW096102114A TW96102114A TWI325186B TW I325186 B TWI325186 B TW I325186B TW 096102114 A TW096102114 A TW 096102114A TW 96102114 A TW96102114 A TW 96102114A TW I325186 B TWI325186 B TW I325186B
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Taiwan
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conductive
light
emitting diode
package structure
layer
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TW096102114A
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TW200832737A (en
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Bily Wang
Jonnie Chuang
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Harvatek Corp
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Priority to TW096102114A priority Critical patent/TWI325186B/zh
Priority to US11/976,478 priority patent/US7671373B2/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483Containers
    • H01L33/486Containers adapted for surface mounting

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Led Device Packages (AREA)

Description

1325186 九、發明說明: 【發明所屬之技術領域】 作方極,封褒結構及其製 構及其製作方法 發光二極體晶片封I结 【先前技術】 請參閲第-圖所示,其係為習知直立式 片封裝結構之剖面示意圖。由圖中可知,習知之直立:: 極體晶片封裝結構係包括:一絕緣基底2 a、一;‘ 木a、一發光二極體晶片3 a及一螢光膠體4 a。 a ’料電架2 3係具有二個分別延該絕緣基底1 的兩相反側邊彎折二次之導電接腳2 Q a 電接腳20a、2la之下端面可與一電路板 產生電性接觸,並且該導電接腳2 〇 a、2 1 a分別 具有一正電極區域2 0◦ 3及-負電極區域2 1 〇 a。
再者,錢光二極體晶片3 a係具有_正電極端3 〇 你=貞電極端31〇a,並且該發光二極體晶片3 a 2接設置在該導電接腳2 Q a Jl,錢得該正電極端3 a直接與該導電接腳2 Q a之正電極區域2 q 〇 a產 電I"生接觸,而5亥發光一極體晶片之負電極端HQ ^系透過-導線6 a與該導電接腳2丄a之負電極區域2 1 0 a產生電性連接。 最後’該螢光膠體4 a係覆蓋在該發光二極體晶片3 a上 切* Γ 光二極體晶片3a。藉此,習知之直立 ==封裝結構係可產生向上投光(如箭4 請參閱第二圖及第三圖所示,其 =極體晶片封I结構之立體示意圖及第H = =由圖中可知,習知之側式發光二極體晶36士= 包括:-絕緣基底lb、一導電架2b、裝 片3 b及—螢光膠體4b。 a先-柽體曰曰 b的二電ί 2 具有二個分別延該絕緣基底1 勺側邊‘弯折二二人之導電接腳2 0 b、2丄b,以 ^導電接腳2Qb、21b之側端面可與—電路板^ 生電性接觸,並且該導電接腳2◦b、2 1 -正電極區域2〇〇b及一負電極區域21〇b。L有 再者,該發光二極體晶片3 b係具有—正 〇13及一負電極端31〇,,並且=30 ==該,接腳20b上,以使得該正= 直接亥‘電接腳2 0 b之正電極區域2 〇 〇乜產 生電性接觸’而該發光二極體晶片3b之負電極端3】〇 b係透過-導線6 b與該導電接腳2工b之負電極區择2 1 0 b產生電性連接。 最後,該螢光膠體4 b係覆蓋在該發光二極體晶片3 b上’以保護該發光二極體晶片3 b。藉此,習知之侧式 發光二極體晶>}封裝結構係可產生側向投光(如第三圖之 箭頭所示)之發光效果。 1325186 第四圖係為本發明以陶瓷為基板之發光二極體晶片封裝結 構之製作方法的第一實施例之流程圖; 第五A圖至第五C圖係為以陶瓷為基板之發光二極體晶片 封裝結構之製作方法的第一實施例之製作流程示意 圖; 第六圖係為以陶瓷為基板之發光二極體晶片封裝結構的第 一實施例之剖面示意圖; 第七圖係為本發明第一實施例之發光二極體晶片的第一種 設置方式之側視示意圖; 第八圖係為本發明第一實施例之發光二極體晶片的第二種 設置方式之側視示意圖; 第九圖係為本發明第一實施例之發光二極體晶片的第三種 設置方式之側視示意圖; 第十圖係為本發明發光二極體晶片的第四種設置方式之側 視示意圖; 第十一圖係為本發明以陶瓷為基板之發光二極體晶片封裝 結構之製作方法的第二實施例之流程圖; 第十二圖係為本發明以陶瓷為基板之發光二極體晶片封裝 結構的第二實施例之側視剖面圖;以及 第十三圖係為本發明第一實施例之以陶瓷為基板之發光二 極體晶片封裝結構於側式狀態之立體示意圖。 【主要元件符號說明】 [習知]

Claims (1)

1325186 十、申請專利範圍: 1、一種以陶瓷為基板之發光二極體晶片封裝結構,其包 括: 一陶瓷基板,其具有一本體、及複數個彼此分開且分 別從該本體之其中三面延伸出之突塊; 一導電單元,其具有複數個分別成形於該等突塊表面 之導電層; 一中空陶瓷殼體,其固定於該陶瓷基板之本體的頂面 上以形成一容置空間,並且該容置空間係曝露出該 等導電層之頂面; 複數個發光二極體晶片,其分別設置於該容置空間 内,並且每一個發光二極體晶片之正、負電極端係 分別電性連接於不同之導電層;以及 一封裝膠體,其填充於該容置空間内,以覆蓋該等發 光二極體晶片。 2、 如申請專利範圍第1項所述之以陶瓷為基板之發光二 極體晶片封裝結構,其中該陶瓷基板之本體的側面係 具有複數個分別形成於每兩個突塊之間之半穿孔。 3、 如申請專利範圍第1項所述之以陶瓷為基板之發光二 極體晶片封裝結構,其中該本體與該中空陶瓷殼體係 為兩個相互配合之長方體。 4、 如申請專利範圍第1項所述之以陶瓷為基板之發光二 極體晶片封裝結構,其中該導電單元更進一步包括: 一第一導電單元,其具有複數個分別成形於該等突塊 18 1325186
表面之第一導電層; 一硬度強化單元,其具有複數個分別成形於該等第一 導電層上之硬度強化層;以及 一第二導電單元,其具有複數個分別成形於該等硬度 強化層上之第二導電層; 藉此,該等第一導電層、該等硬度強化層及該等第二 導電層係依序組合成該導電層。 5、 如申請專利範圍第4項所述之以陶瓷為基板之發光二 極體晶片封裝結構,其中該第一導電層係為銀膏層。 6、 如申請專利範圍第4項所述之以陶瓷為基板之發光二 極體晶片封裝結構,其中該硬度強化層係為鎳層。 7、 如申請專利範圍第4項所述之以陶瓷為基板之發光二 極體晶片封裝結構,其中該第二導電層係為金層或銀 層。 8、 如申請專利範圍第1項所述之以陶瓷為基板之發光二 極體晶片封裝結構,其中該導電單元更進一步包括: 一第一導電單元,其具有複數個分別成形於該等突塊 表面之第一導電層;以及 一第二導電單元,其具有複數個分別成形於該等第一 導電層上之第二導電層,其中每一個第二導電層係 為一硬度強化導電層; 藉此,該等第一導電層及該等第二導電層係組合成該 導電層。 9、 如申請專利範圍第8項所述之以陶瓷為基板之發光二 19 1325186 打年如/E?雙早 L:Jml 極體晶片封裝結構,其中該第一導電層係為銀膏層。 1 0、如申請專利範圍第8項所述之以陶瓷為基板之發光 二極體晶片封裝結構,其中該第二導電層係為金層或 銀層。 1 1、如申請專利範圍第1項所述之以陶瓷為基板之發光 二極體晶片封裝結構,其中該容置空間係以朝上的方 式,以使得該等導電層之底面接觸於一電路板。 1 2、如申請專利範圍第1項所述之以陶瓷為基板之發光 二極體晶片封裝結構,其中該容置空間係以朝向側面 的方式,以使得該等導電層之側面接觸於一電路板。 1 3、如申請專利範圍第1項所述之以陶瓷為基板之發光 二極體晶片封裝結構,其中該等導電層係分成複數個 正極導電部及負極導電部。 1 4、如申請專利範圍第1 3項所述之以陶瓷為基板之發 光二極體晶片封裝結構,其中該發光二極體晶片之 正、負電極端係分別設置於每一個發光二極體晶片之 上表面;藉此,透過打線的方式,以使得每一個發光 二極體晶片之正、負電極端分別透過兩導線而電性連 接於相鄰之正極導電部及負極導電部。 1 5、如申請專利範圍第1 3項所述之以陶瓷為基板之發 光二極體晶片封裝結構,其中該發光二極體晶片之 正、負電極端係分別設置於每一個發光二極體晶片之 下表面與上表面;藉此,透過打線的方式,以使得每 一個發光二極體晶片之正電極端直接電性連接於相對 20 fl"^\ 日 L. •〖充 應之正極導雷都 w. _ . L-一.·— 稍】) 極端Μϋπ " ^母一個發光二極體晶片之負電 部W透過-導線而電性連接於相對應之負極導電 1匕如申請專利範圍第2 3項所述之以陶 下表面;η:,於每-個發光二極體晶片之 二極體晶;之正式’以使得每-個發光 錫球而電性連接㈣^別透過複數個相對應之 光2Ϊ利範圍第13項所述之以陶究為=發 極肢曰日片封裝結構,其中該發光二極體晶片之 正、負電極端係分別設置於每一個發光二極體晶片之 ^表面’並且每-個發光二極體晶片係分別設置於每 一個突塊之間;藉此,透過打線的方式,以使得每一 個發,二極體晶片之正、負電極端分別透過兩導線而 電性連接於相鄰之正極導電部及負極導電部。 1 8、一種以陶瓷為基板之發光二極體晶片封裝处構之掣 作方法,其包括: … " 提供-陶£基板,其具有-本體、及複數個彼此分開 且为別從該本體之其中三面延伸出之突塊; 分別成形複數個導電層於該等突塊之表面; 固定一中空陶瓷殼體於該陶瓷基板之本體的頂面上以 形成一容置空間,並且該容置空間係曝露出該等導 電層之頂面;
1325186 分別設置複數個發光二極體晶片於該容置空間内,並 且每一個發光二極體晶片之正、負電極端係分別電 性連接於不同之導電層;以及 填充一封裝膠體於該容置空間内,以覆蓋該等發光二 極體晶片。 1 9、如申請專利範圍第1 8項所述之以陶瓷為基板之發 光二極體晶片封裝結構之製作方法,其中該陶瓷基板 之本體的側面係具有複數個分別形成於每兩個突塊之 間之半穿孔。 2 0、如申請專利範圍第1 8項所述之以陶瓷為基板之發 光二極體晶片封裝結構之製作方法,其中該本體與該 中空陶瓷殼體係為兩個相互配合之長方體。 2 1、如申請專利範圍第1 8項所述之以陶瓷為基板之發 光二極體晶片封裝結構之製作方法,其中該等導電層 係組合成一導電單元,並且該導電單元更進一步包括: 一第一導電單元,其具有複數個分別成形於該等突塊 表面之第一導電層; 一硬度強化單元,其具有複數個分別成形於該等第一 導電層上之硬度強化層;以及 一第二導電單元,其具有複數個分別成形於該等硬度 強化層上之第二導電層; 藉此,該等第一導電層、該等硬度強化層及該等第二 導電層係依序組合成該導電層。 2 2、如申請專利範圍第2 1項所述之以陶瓷為基板之發 22 rI325186 光二極體晶片封裝結構之製作方法,其中該第一導電 層係為銀膏層。 2 3、如申請專利範圍第2 1項所述之以陶瓷為基板之發 光二極體晶片封裝結構之製作方法,其中該硬度強化 層係為鎳層。 2 4、如申請專利範圍第2 1項所述之以陶瓷為基板之發 光二極體晶片封裝結構之製作方法,其中該第二導電 層係為金層或銀層。 2 5、如申請專利範圍第1 8項所述之以陶究為基板之發 光二極體晶片封裝結構之製作方法,其中該等導電層 係組合成一導電單元,並且該導電單元更進一步包括: 一第一導電單元,其具有複數個分別成形於該等突塊 表面之第一導電層;以及 一第二導電單元,其具有複數個分別成形於該等第一 導電層上之第二導電層,其中每一個第二導電層係 為一硬度強化導電層; 藉此,該等第一導電層及該等第二導電層係組合成該 導電層。 2 6、如申請專利範圍第2 5項所述之以陶瓷為基板之發 光二極體晶片封裝結構之製作方法,其中該第一導電 層係為銀膏層。 2 7、如申請專利範圍第2 5項所述之以陶瓷為基板之發 光二極體晶片封裝結構之製作方法,其中該第二導電 層係為金層或銀層。 23 8、如申請專利範圍第 ~—- 光二極體晶片封癸处m e項所述之以陶瓷為基板之發 係以朝上的方式7、r之製作方法,其中該容置空間 電路板。χ以使㈣等導電層之底面接觸於- 9二如巾請專利範8 t二極體晶片封農結為純之發 (丁、以朝向側面的方*,、 /、中該谷置空間 於一電路板。式,以使得該等導電層之侧面接觸 光二極第18項所述之以陶瓷為基板之發 俜八t r装結構之製作方法,1中該等導電# 固正極導電部及負極導電部 申。月專利範圍第3 〇項 先二極體晶片封穿,士嗜夕制2 乂陶尤為基成之發 體晶片之正、其中該發光二極 體曰曰Μ夕μ主電極端係分別設置於每—個發光二極 一^發光透過打線的方式,以使得每 性連接於相鄰之正極導電部及負極導電= 如2專利範圍第30項所述之以陶究為基板之發 肢晶片封袭結構之製作方法,其中該發光二極 :曰曰片之正、負電極端係分別設置於每一個發光二極 組晶片βί下表面與上表面;藉此,透過打線的方式, 以使得每一個發光二極體晶片之正電極端直接電性連 接於相對應之正極導電部,並且每一個發光二極體晶 片之負電極端則透過一導線而電性連接於相對應之負 24 1325186 極導電部 曰 顿无 3 3光如項所述切陶板之發 體晶片之正、負電極端係分別:中該發先一極 體晶片之下表面;藉此,透過覆3::個發光二極 -個發光二極體晶片之正、負;:的方式’以使得每 相對應之錫球而電性連接於^極端分別透過複數個 導電部。 钱巧目#之正極導電部及負極 3 4光如第3 〇項所述之以陶究為基板之發 ㈡::片=結構之製作方法,其中該 丧r極端係分別設置於每-個發光二極 並且每-個發光二極體晶片係分別 。又置於母—個突塊之間;藉此,透過打線的 使得每-個發光二極體晶片之正、負電極端分別透過 :導線而電性連接於相鄰之正極導電部及負極導電 如巾請專利範圍第18項所述之以喊為基板之發 =-極體晶m结構之製作方法,其中該中空陶究 殼體係利用⑻溫陶究共燒技術(L〇w-Temperature Cofired Ceramics,LTrr、,I” X ^ 體的頂面上。cc) μ定於該喊基板之本 25
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