1323011 六、發明說明： 【發明所屬之技術領域】 本發明的實施例大體上係有關於一種蝕刻方法。詳士 之’本發明係有關於用於蝕刻具有受控制的製程結果分 配的方法。 【先前技術】 • 在積體電路的製造中，各式製程參數的精準控制是在 一基材内達到一致的結果，以及達到基材到下一基材之 間可重復的結果所必需的。在製程期間，在溫度及整個 基材的溫度梯度上的變動對於物質沉積，蝕刻率，級階 覆蓋，特徵結構錐形角，及半導體元件的其它參數而言 是不利的。因此，在產生在該基材上的一預定的溫度分 佈圖樣是達到高產量的關鍵要求之一。 2003 年版的 internati〇nal Techn〇1〇gy R〇admap f〇r • Semiconductors記載了在電晶體閘極關鍵尺寸（CD)上的 減小對於未來的蝕刻技術而言將會是一項重要的挑戰。 因此，有許多的工作已被完成，用以研究閘極蝕刻製程 參數在控制CD的能力上的影響，因為閘極cd對於一元 件的最終效能有著重大的影響。已有數種關於閘極CD 控制之不同的笨略被發表，包括有光阻整剪及閘極硬光 罩蝕刻化學物的控制《前者的方法可將光阻尺寸減小到 低於光阻的橫向蝕刻可微影地達到的尺寸，而後者的方 4 法則依賴蝕刻在硬光罩蝕刻期間被再沉積到側壁上之副 產物來控制橫向蝕刻相對於垂直蝕刻的量並使橫向蝕刻 鈍化。蝕刻副產物造成的側壁鈍化並不單單侷限在硬光 罩钱刻步驟上’其亦會在閘極主蝕刻，軟著陸，及所有 蝕刻步驟期間發生❶ 钱刻副產物的沉積速率被預期可遵守副產物的氣相濃 度及副產物的黏著係數。黏著係數已被使用在氣體-表面 反應機構中用以描述一入射的氣相物種被吸收到一表面 中的可能性，且此係數典型地被近似為被反應性地吸收 到一表面上的物種數對總入射物種數的比例。 然而’傳統的基材托盤並不具有足夠的機構來控制在 該基材上之基材溫度分佈。不能控制基材溫度均勻性對 於在一單一基材内及在基材與基材之間的製程均勻性， 元件良率及經過處理的基材的整體品質具有一不利的影 響。 因此，在此技藝中對於一種用於蝕刻一基材之改良的 方法存在著需求。 【發明内容】 本發明的實施例大體上提供用來蝕刻一基材的方法。 在一實施例中’該方法包括決定一基材溫度目標曲線 (profile) ’其對應在一基材上之蝕刻副產物的一均勻的沉 積速率，優先地調節一基材支撐件的一第一部分相對於 該基材支撐件的一第二部分的溫度用以獲得在該基材上 的該基材溫度目標曲線，及蝕刻在該被優先地調節之基 材支撐件上的該基材。 在另一實施例中，該方法包括提供一第一製程控制旋 鈕用來實施一第一製程條件，其中該第一製程條件是由 製程結果的一第一分配來代表；提供一第二製程控制旋 紐用來實施一第二製程條件，其中該第二製程條件是由 製程結果的一第二分配來代表；將該第一及第二製程控 制旋鈕兩者設定至一預定的設定，其中該第一製程控制 旋鈕選擇氣體注入該處理室的位置，及該第二製程控制 旋紐選擇該基材支撐件的溫度曲線。 在另一實施例中，該方法包括提供一基材至一處理室 中，該處理室具有一可選擇的物種分配於該處理室内， 及具有仏向丨·®1·度控制之基材支撐件，其中一由該基材 支樓件所引起的溫度曲線及物種分配選擇包含一控制參 數組，用一第一控制參數組蝕刻一第一物質層，及用第 二控制參數組蝕刻第二物質層，其中該第一及第二參數 組不相同。 【實施方式】 該閘極银刻製程的—示意圖被示於第圖中。吾人 已在實驗中觀察到閘極蝕刻CD偏移與基材溫度有一很 強的關連性’現將揭示此-關係’且展示該閘極钱刻副 產物黏著係數與基材溫度的相依性，這讓在整個基材上 的製程結果分配的控制成為可能。 飯刻副產物的此-再沉積速率被預期會遵循副產物的 氣相濃度及這些副產物的黏著係數。黏著係數已被使用 在氣體-表面反應機構中用以描述一入射的氣相物種102 被吸收到一表面（被顯示為一閘極結構100)中的可能 性，且此係數典型地被近似為被反應性地吸收到一表面 上的物種數對總入射物種數的比例β該黏著係數與表面 溫度的相依性的分析已被用來描述在矽膜的取向附生的 生長期間的雜質等級及二氧化矽在基材上之級階覆蓋沉 積行為。這兩個模型使該黏著係數和吸收，去吸附及 氣相物種在該表面上的反應速率之間的競爭產生關聯 性°因此’負值的黏著係數可被解讀為蝕刻良率。使用1323011 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION Embodiments of the present invention generally relate to an etching method. The present invention relates to a method for etching with a controlled process result assignment. [Prior Art] • In the fabrication of integrated circuits, precise control of various process parameters is necessary to achieve consistent results within a substrate and to achieve repeatable results between the substrate and the next substrate. Variations in temperature and temperature gradient across the substrate during processing are detrimental to material deposition, etch rate, level coverage, feature cone angle, and other parameters of the semiconductor component. Therefore, a predetermined temperature distribution pattern produced on the substrate is one of the key requirements for achieving high throughput. The 2003 edition of internati〇nal Techn〇1〇gy R〇admap f〇r • Semiconductors documented that the reduction in critical gate size (CD) of the transistor will be an important challenge for future etching techniques. . Therefore, much work has been done to investigate the effect of gate etch process parameters on the ability to control CDs because gate cd has a significant impact on the ultimate performance of a component. There have been several abbreviations about the different control of the gate CD, including photoresist trimming and gate hard mask etch chemistry control. "The former method can reduce the photoresist size below the photoresist. The lateral etch can be measurably sized, while the latter method relies on etching by-products that are redeposited onto the sidewalls during the hard mask etch to control the amount of lateral etch relative to vertical etch and passivate the lateral etch. The sidewall passivation caused by etching by-products is not limited to the hard mask engraving step. It also occurs during the gate main etch, soft landing, and all etching steps. The deposition rate of by-products is expected to be observed. The gas phase concentration of by-products and the adhesion coefficient of by-products. Adhesion coefficients have been used in gas-surface reaction mechanisms to describe the possibility of an incident gas phase species being absorbed into a surface, and this coefficient is typically approximated as a species that is reactively absorbed onto a surface. The ratio of the number of pairs of total incident species. However, conventional substrate trays do not have sufficient mechanisms to control the substrate temperature distribution on the substrate. The inability to control substrate temperature uniformity has a detrimental effect on process uniformity within a single substrate and between the substrate and the substrate, component yield, and overall quality of the treated substrate. Accordingly, there is a need in the art for an improved method for etching a substrate. SUMMARY OF THE INVENTION Embodiments of the present invention generally provide methods for etching a substrate. In one embodiment, the method includes determining a substrate temperature target profile 'corresponding to a uniform deposition rate of etch byproducts on a substrate, preferentially adjusting a first portion of a substrate support A temperature relative to a second portion of the substrate support is used to obtain a target temperature profile of the substrate on the substrate, and the substrate is etched onto the preferentially conditioned substrate support. In another embodiment, the method includes providing a first process control knob for implementing a first process condition, wherein the first process condition is represented by a first assignment of process results; providing a second process control The knob is configured to implement a second process condition, wherein the second process condition is represented by a second assignment of the process result; setting the first and second process control knobs to a predetermined setting, wherein the knob The first process control knob selects a position at which the gas is injected into the processing chamber, and the second process control knob selects a temperature profile of the substrate support. In another embodiment, the method includes providing a substrate to a processing chamber having an optional species dispensed within the processing chamber, and a substrate support having a 丨·®1 degree control The temperature profile and species distribution selection caused by the substrate support member includes a control parameter set, a first control layer group is used to etch a first material layer, and a second control parameter group is used to etch the second substance a layer, wherein the first and second parameter sets are different. [Embodiment] A schematic diagram of the gate silver etching process is shown in the figure. We have observed in the experiment that the gate etch CD offset has a strong correlation with the substrate temperature, which will now reveal this-relationship and demonstrate the dependence of the gate adhesion coefficient on the substrate temperature. This makes it possible to control the distribution of process results across the substrate. This redeposition rate of the by-product of the meal is expected to follow the gas phase concentration of the by-products and the adhesion coefficient of these by-products. The adhesion coefficient has been used in a gas-surface reaction mechanism to describe the likelihood that an incident gas phase species 102 will be absorbed into a surface (shown as a gate structure 100), and this coefficient is typically approximated as The ratio of the number of species that are reactively absorbed onto a surface to the total number of incident species. The analysis of the dependence of the adhesion coefficient on the surface temperature has been used to describe the level of impurities during the growth of the epitaxial growth of the ruthenium film and The level of the cerium oxide on the substrate covers the deposition behavior. These two models correlate the adhesion coefficient with the competition between absorption, desorption and the rate of reaction of the gas phase species on the surface. Thus the 'negative adhesion coefficient can be interpreted as the etching yield. use
Bennet等人的方程式結合Langmuir的去吸附理論，溫度 相依性S*可被表示為：Bennet et al.'s equation combined with Langmuir's desorption theory, temperature dependence S* can be expressed as:
^adsjeff) V PNaqxA-^\ s*(T) = l kT J ⑴ 其中P為該副產物的分壓，NA為Avogadro數，m為 該吸附物種的分子重量，R為理想氣體常數，T為溫度， 及為用於沉積的能量與用於表面反應的能量兩者間 的差異。假設不論早先的情況為何，該蝕刻副產物均勻 地再沉積到杯h古 任何表面位置上，所以表面覆蓋率可被忽 此1假叹是合理的，因為在閘極蝕刻期間鈍化層被觀 '、、厚度典型地大於一單一的單層（m〇n〇layer)的厚 度。 可直接從公式（1)中被擷取出來的兩個重要的蝕刻製 程參數為到達該表面的物種通量及基材溫度。這兩個可 調譜的配方（recipe)參數對於鈍化物種在閘極側壁上的 黏著係數有重大的影響，因此該閘極CD偏移在蝕刻之 後。在公式（1)中之顯然的複雜性在於Rads 一項，其不易 被決定且本身具有一些溫度的相依性。為了此分析，項 將被用作為一配適參數（行⑴叫parameter)起將於下文中 作進一步說明。 為了要測試物種通量及基材溫度對於閘極蝕刻製程的 影響’具有一多晶矽閘極堆之圖案化的基材被製造出 來°用來將基材形成圖案之光罩被設計為用在9〇ηιη技 術節點上。蝕刻實驗是在由Applied Materials公司所製 造之設有DPS II矽蝕刻室的Centura® DPS蝕刻系統中 實施的。基材係在一標準的閘極蝕刻室中使用一個四步 驟製程（突破，主蝕刻’軟著陸，及過度蝕刻）來蝕刻。 預飯刻及後姓刻的CD在一由Applied Materials公司製 造的VeraSEM®度量系統上被測量。 基材溫度對於平均CD偏移的影響（CD偏移被界定為 後蝕刻CD減預蝕刻CD)可在第2圖中被清楚地看出。 該資料顯示提高基材溫度造成平均閘極線寬變窄，這與 的溫度下在閘側壁上的鈍化物種較少的理論吻 «。第2圖中之黏著係數的最配適曲線緊緊地跟隨著平 均CD偏移資料且使用公式（1)來加以計算，其中被 假疋為 0.250eV 及 Rads=9E13 atoms/cm2s。為了要確保此 適參數的值，Rads，是合理的，Rads的一獨立的計算可 使用下面的公式（2)的CD偏移資料來實施： iCDBias)pN.^adsjeff) V PNaqxA-^\ s*(T) = l kT J (1) where P is the partial pressure of the by-product, NA is the Avogadro number, m is the molecular weight of the adsorbed species, R is the ideal gas constant, and T is The temperature, and the difference between the energy used for deposition and the energy used for surface reaction. It is assumed that the etching by-product is uniformly redeposited to any surface position of the cup h, regardless of the earlier situation, so the surface coverage can be neglected because the passivation layer is viewed during the gate etching. The thickness is typically greater than the thickness of a single monolayer (m〇n〇layer). Two important etch process parameters that can be extracted directly from equation (1) are the flux of species reaching the surface and the substrate temperature. These two tunable recipe parameters have a significant effect on the adhesion coefficient of the passivated species on the gate sidewalls, so the gate CD offset is after etching. The obvious complexity in equation (1) lies in the Rads term, which is not easily determined and has some temperature dependence. For this analysis, the term will be used as a matching parameter (line (1) called parameter) as will be further explained below. In order to test the effect of species flux and substrate temperature on the gate etch process, a patterned substrate with a polysilicon gate stack was fabricated. A reticle used to pattern the substrate was designed for use in 9 〇ηιη on the technology node. The etching experiment was carried out in a Centura® DPS etching system equipped with a DPS II(R) etching chamber manufactured by Applied Materials. The substrate is etched using a four-step process (breakthrough, main etch 'soft landing, and over etch) in a standard gate etch chamber. CDs for pre-meal and post-sequence were measured on a VeraSEM® metrology system manufactured by Applied Materials. The effect of substrate temperature on the average CD offset (CD offset is defined as post-etched CD minus pre-etched CD) can be clearly seen in Figure 2. This data shows that increasing the substrate temperature causes the average gate line width to narrow, which is less than the theoretical kiss of the passivation species on the sidewall of the gate at temperatures. The most suitable curve of the adhesion coefficient in Fig. 2 is closely followed by the average CD shift data and is calculated using the formula (1), which is assumed to be 0.250 eV and Rads = 9E13 atoms/cm2s. In order to ensure the value of this appropriate parameter, Rads is reasonable. A separate calculation of Rads can be implemented using the CD offset data of equation (2) below: iCDBias)pN.
Rads = 2M (2) §然，公式（2)所得到之Rads的平均值與在所考量的溫 度範圍内經由配適程序所獲得的數值相符。介於這三個 測試（r_)的平均CD偏移與基材溫度之間的關係顯示 •〇_8607nm/°C的一平均變化率。在黏著係數上的相應百 分比變化，S*，為_〇·2%π。示於第2目中之黏著係數 的計算範圍亦與CL基團入射到一被充能的矽基電極上 所獲得的數值相符》 第2圖的CD偏移平均值上的_標準差棒為在基材⑶ 偏移不均句性内的測量。不均句性的程度對於所有三個 基材溫度都是-致的’在邊緣區域被觀察到的線寬比在 中心區域的線寬小。在條件與這參個測試類似的情況 下’於基材溫度均勻性内之測量顯#出，胃基材溫度範 園小於±1C ’ H意謂著’這些例子中於基材線寬不均勾 性内被觀察到的係導因於除了基材溫度以外的其它東 西〇 1323011 以前的工作顯示，在基材邊緣處的CD偏移上的減小 可以是藉由降低在此基材範圍内之副產物濃度來造成。 此濃度梯度是因為在基材邊緣處相對於基材中心處的一 更有效率之蝕刻副產物去除所產生的。其結果為，對於 一給定的基材溫度而言，在基材邊緣處之局部（1〇cal)的 吸附率在吸附地點的緊鄰周圍處，即，閘極側壁，被降 低。鈍化物種之局部分壓可藉由饋入氣體注入到該室中 之位置來加以部分地控制。第3圖顯示模擬的結果其 顯示三種不同的氣體注入設計。當氣體在室的頂部以一 垂直該基材表面的方向上被注入到室中（在第3圖中被標 註為中心氣體饋入），因為對流流動的增加所造成之氣體 速度的增加而使得在中心處之先驅物種的密度實際上被 降低。相反地，當氣體在室頂端處於一平行於該基材表 面的方向上被注入到室中時（在第3圖中被標註為側邊氣 體饋入），流至基材表面的氣流是更為擴散性的，且可獲 得一更均勻的先驅物種的分配結果。 藉由利用基材溫度與黏著係數之間的關係以及蝕刻副 產物在該蝕刻室内的知識，基材CD偏移均勻性可藉由 引入多溫度區於該靜電夾頭（ESC)内被最佳化。一典型的 閘極蝕刻製程之蝕刻副產物的徑向分配及黏著係數的一 相應的徑向要求被示於第4圖中。因為黏著係數隨著溫 度的改變在小的溫度範圍内幾乎是線性的，所以預測的 溫度曲線能夠非常接近地反映局部氣相物種分配。因 此，對於基材的邊緣區域而言，所想要的基材溫度必需 10 要比較低’用以補償因為抽泉所造成之純化物種的減 少。實際上’此局部的基材表面溫度降低可提高鈍化物 種的黏著係數’用以保持一固定且均勻之到達到該基材 表面之被吸附物種的通量，及均勻的閘極線寬。 第5圖顯示三個例子：一處於均勻溫度的基材，一具 有雙區ESC之佳化的狀態’及一被故意不當調整的製程 用以突顯控制在整彻基材上的CD偏移的能力。均勻基 材溫度條件之在基材邊緣處之較小閘極線寬在第5圖被 觀察到’當ESC的溫度被分為兩個區域（其中外區的溫度 低於内區的溫度）時可達到中心對邊緣偏移均勻性上的 一顯著的改善。ESC在均勻溫度的CD偏移範圍為 15.3nm，及雙區ESC的CD偏移範園為9.5nm，其改善 率達37.9%。第三個例子顯示的是中心對邊緣基材溫度 差的一誇大的情形’其結果為該CD偏移被故意朝向正 值調整用以突顯出隨著基材溫度控制CD偏移的能力。 在最低的基材溫度時，有更多的副產物在侧壁被吸收且 造成的一反逆的效果為邊緣線寬變得比基材中的線寬還 要寬。 综言之’平衡吸附理論可被用來解釋在CD偏移均勻 性於電晶體閘極蝕刻製程期間被觀察到的趨勢。詳言 之’银刻副產物的黏著係數的溫度相依性是很顯著的。 因此，一具有多個可獨立地控制的溫度區之ESC(如，在 DPS Π矽蝕刻室中所設置者）對於關鍵蝕刻應用（如，閘 極蝕刻）而言是最佳的。相同的現象亦很可能發生在側壁 1323011 鈍化對於CD效能而言是很關鍵的其它應用上，譬如鋁 ' 線的蝕刻或接點或介層孔的介電蝕刻。 • 本文中所描述的蝕刻製程可被使用在電漿蝕刻室中， . 譬如’一 HART蝕刻反應器，一 HART TS蝕刻反應器， 一解耦合的電漿源（DPS)，DPS II，或DPS Plus，或 CENTURA®蝕刻系統的DPS DT蝕刻反應器，所有這些 設備都可向設在美國加州Santa Clara市的Applied Materials公司購得。其它製造廠商的電漿蝕刻室亦可被 鲁 用來實施本發明。該DPS反應器使用13.5 6MHz的感應 電漿源來產生及維持一高密度電漿及一 13.56MHz源偏 Μ功率來將一基材偏壓《該電漿及偏壓源的解耦合 (decoupled)本質讓離子能量及離子密度可被獨立地控 制。該DPS反應器在來源及駢壓功率，壓力，及蝕刻氣 體化學物上的改變提供一寬闊的製程窗口且使用一終點 系統來決定該製程的終點。 φ 第6圖顯示一可被用來實施本發明示範性蝕刻反應器 600的示意圖。示於本文中之該蝕刻反應器6〇〇的特定 實施例是為了舉例的目地而被提供的，其不應被用來限 ‘制本發明的範園。 蝕刻反應器600大體上包括一處理室61〇，一氣體面 板638及一控制器64〇。該處理室61〇包括一導電本體 (壁）630及一天花板62〇，它們圍起一處理空間。處理氣 體從該氣體面板63 8被提供至該室610的處理空間。 控制器640包括一中央處理單元（cpu)644，一記憶體 12 1323011 642 ’及支援電路646 »控制器64〇被耦接至該蝕刻反應 器600的控制構件並控制它們，製程在該室61〇中被實 施，以及可促進與積體電路代工廠的資料庫之間的一非 必要的資料交換。 在所描述的實施例中’天花板620是一大致平的構 件。處理室610的其它實施例可具有其它種類的天花 板，如圓頂型夭花板。在天花板610上方設置有一天線 其包含一或多個感應線圈元件（在圖中示出的是兩個同 軸線圈元件）。天線612被耦接至一配接網絡及射頻電漿 電源618。電力被供應至天線612且在處理期間感應地 輕接至形成在該室100内之電漿。或者，室100可藉由 使用一電源684而利用電容電漿耗接，這將於下文中詳 細說明。 該氣體面板638被耦接至一或多個喷嘴，使得經過該 等喷嘴進入到該室中的義流可被控制，藉以控制在該室 中之物種分配。該一或多個噴嘴被建構及/或安排成可實 施製程氣體流位置，製程氣體流的流動方向或在該室内 之物種分配等功能中的至少一者。 在一實施例中，一具有至少兩個出口埠604，606之喷 嘴608被提供用以耦接至該室本體610的天花板620。 出口埠604 ’ 606被建構來分別引起一直接及一間接的氣 流方向至該室中。例如，該第一出口埠604可提供一直 接氣流方向’即，產生一大致垂直於該基材表面之氣流 進入到該室中。該第二出口埠606可提供一間接的氣流 13 =向’即產生-大致平行於該基材表面之氣流進入到該 室中’或在另-實施例中，被導引在—相對於該基材的 表面小於或等於60度的入射角度的方向上。一或多個出 口埠604, 606可被設置在分開的喷嘴6〇8上（即，每個 喷嘴一個出〇谭）。 一托盤組件616被設置在該處理室6〇〇的内部空間6〇6 内之在喷嘴608底下的位置處。該托盤組件616在處理 期間固持該基材614。該托盤組件616大體上包括複數 個舉升銷（未示出）被設置成穿過該托盤組件，它們被建 構將基材從托盤組件616上舉起，方便以一傳統的方式 與一機器人（未示出）交換該基材614。 在一實施例中’該托盤組件616包括一安裝板662, 一基座664及一靜電夾頭666。該安裝板662被耦接至 該室本體630的底部612且包括用來安排管路的通道， 譬如流體管線，電力線及感應器導線等等，通至該基座 664及夾頭668。 靜電夹頭666或基座664中的至少一者包括至少一非 必要的嵌埋式加熱器6 7 6，至少一非必要的喪埋式絕緣 體674’及複數根導管它們流體地耦接至一提供一溫度 調節流體的流體源672。在一示於第6圖的實施例中， 一加熱器676被示範性地顯示在耦接到一電源供應器 678的該靜電夾頭666中，而被一環形絕緣體674分隔 開的兩個導管668 ’ 670則被顯示在該基座664中。導管 668 ’ 670及加熱器676可被用來控制該托盤組件616的 1323011 溫度，藉以加熱及/或冷卻該靜電夾頭666，藉以至少部 分地控制放置在該靜電夹頭666上的基材614的溫度。 形成在該基座664内的兩個分離的冷卻導管668，670 界定至少兩個可獨立地控制的溫度區域。額外的冷卻導 管及/或導管布局亦可被安排用以界定額外的溫度控制 區域。在一實施例中，第一冷卻導管668被安排在該第 二冷卻導管670的徑向内側，使得溫度控制區域是同心 圓的區域。導管668，670可以是被徑向定向，或具有其 它形狀的結構。冷卻導管668，670可被耦接至一溫控的 熱傳流體的單一來源，或可被分別地耦接至一分離的熱 傳流體源》 該絕緣體674是用一物質製成的，該物質具有的導熱 係數不同於與其相鄰之該基座664的區域的物質的導熱 係數。在一實施例中，該絕緣體674具有的導熱係數小 於該基座664導熱係數。在第6圖所示的實施例中，該 基座664是用鋁或其它金屬物質所製成的。在一進一步 的實施例中，絕緣體674可用一具有一非等方向性（即， 導熱係數是與方向有關）的物質製成。該絕緣體674是用 來局部地改變托盤組件616經由該基座664到達導管 668 ’ 670的熱傳速率，相對於經由該基底664之不具有 一絕緣體於熱傳路徑上的鄰近部分的熱傳速率。一絕緣 體674被橫向地設置在該第—及第二冷卻導管⑽，_ 之間’用以在該托盤組件616的該等溫度控制區域之間 提供加強的熱絕緣。 15 1323011 在示於第6圖的實施例中，該絕緣體674被設置在導 s 668 ’ 670之間，藉以阻礙橫向熱傳遞及促成該托盤組 件616的橫向溫度控制區域。因此，藉由控制插入件的 數量，形狀，大小，位置及熱傳係數，則靜電夾頭666 及放在其上的基材614的溫度曲線就可被控制。雖然示 於第6圖中的該絕緣體674是一環形的圓環但該絕緣 體674的形狀可以有許多不同的形狀。 一非必要的導熱膏或黏膠（未示出）可被施用在該基座 664與靜電夾頭666之間。該導電膏有助於靜電夾頭666 與該基座64之間的熱交換。在一示範性的實施例中該 黏膠機械性地將該靜電夾頭666黏結到該基座664上。 或者’該托盤組件616可包括一硬體（如，夾子，螺釘， 及類此者）其被設計來將該靜電夾頭666固定到基座664 上。 該靜電夾頭666與該基座64的溫度係使用複數個感應 器來監測。在示於第6圖的實施例中，一第一溫度感應 器690及一第二溫度感應器692被徑向間隔地設置，使 得第一溫度感應器690可將該托盤組件616的一中心區 域的一公制的溫度表示提供給該控制器650，而該第二 溫度感應器692可將該托盤組件616的一周邊區域的一 公制的溫度表示提供給該控制器650。 該靜電夾頭666被設置在該基座664上且被一蓋環648 所圍。該靜電失頭666可用鋁，陶瓷，或其它適合在製 程期間支撐該基材614的材質製成。在一實施例中，該 16 1323011 靜電夾頭666是陶瓷。或者，該靜電夾頭666可用_真 空夾頭，機械式夾頭或其它適當的基材支撐件來取代。 該靜電夾頭666大體上是用陶瓷或類似的介電材質製 成且包含至少一用一夾頭電源682來控制的夾持電極 680。該電極680(或設置在該夾頭666或該基座664内的 其它電極）可非必要地被糕接至一或多個RF電源用以維 持一用製程氣體及/或其它氣體形成的電漿於該室6〇〇 内。在示於第6圖的實施例中，電極680被耦接至一 RF 電源及配接電路684，它能夠產生一用來維持一用製程 氣體形成的電漿於該室600内之RF訊號。 靜電夾頭666亦可包括複數個通道（未示出），如溝槽， 匕們被形成在夾頭的基材支擇表面上且被流體地輕接至 一熱傳氣體（或背側氣體）的來源（未示出）》在操作時，背 側氣體（如’氦氣（He))在控制的壓力下被提供至該通道 中，用以加強介於該靜電夾頭666與該基材614之間的 熱傳遞。傳統地，至少該靜電夾頭的基材支撐表面被提 供可抵抗基材製程期間所使用之化學物及溫度的塗層。 第7-9圖為可在室100或其它適當的處理室中實施之 蝕刻製程700，800，900的實施例的流程圖。每一製程 都可被用來製造示於第l〇A_F及UA_C圖中的結構。雖 然製程700，800，900是用來製造第1〇A F圖中的閘極 結構及在第11A-C圖中的淺溝渠隔離（STI)結構，但該等 製程亦可被有利地用來钱刻其它結構。製程7〇〇, 8〇〇, 9〇〇可被用纟控制每一製程結果的橫向分配。例如，製 17 1323011 程700 ’ 800，900可被用來產生蝕刻製程結果的一大致 均勻的中心至邊緣分配’其中製程結果包括蝕刻深度、 CD偏移、微負載(microloading)、側壁輪廓、鈍化、钱 刻率、步階覆蓋性、特徵結構錐度角及底切（undereutting) 中的至少一者。 第7圖的製程700開始於步驟702，決定一基材溫度 目標曲線其相應於蝕刻副產物在一基材上的均勻沉積速 率。在步驟704’ 一基材支撐件的一第一部分的溫度相 對於該基材支撐件的一第二部分被偏好地調整，用以獲 得該基材溫度目標曲線於該基材上《在步驟7〇6，該基 材在該經過偏好地調整的基材溫度上被蝕刻。 第8圖的製程800開始於步驟802，一用來實施一第 一製程條件製程控制旋鈕被提供，其中該第一製程條件 是用製程結果的第一分配來代表。在步驟8〇4，一用來 實施一第二製程條件製程控制旋鈕被提供，其中該第二 製程條件是用製程結果的第二分配來代表。在步驟8〇6， 該第一及第二製程控制旋紐兩者都被設定在一預定的設 定位置，用以產生製程結果的一第三分配，其中該製程 結果的第三分配不同於製程結果的第一及第二分配。在 步驟808，一放置在一設置在一處理室内的基材支撐件 上的基材被蝕刻，該處理室具有被設定在該預定的設定 位置之第一及第二製程控制旋鈕，其中該第一製程控制 旋鈕選擇氣體注入到該處理室的位置及該第二製程控 制旋叙選擇該基材支擇件的溫度曲線。 18 1323011 第9圖的製程900在步驟9〇2開始，其提供一基材至 . 處理至中，該處理室具有一可選擇的物種分配於該處 • 理室内及—具有橫向溫度控制之基材支撐件，其中-由 該基材支撐件所引發的溫度曲線及一物種分配的選擇包 含了 一控制參數組。在步驟904,使用第一控制參數組 來蝕刻一第一物質層。在步驟906 ,使用一第二控制參 數組來蝕刻一第二物質層，其中該第一與第二控制參數 組是不相同的。方法900可在一單一層的遞增蝕刻期間 實施，其中每一遞增蝕刻步驟都如一層的蝕刻步驟般地 被對待。 飯刻方法700，800，900可被用來製造一值極結構， 如第10A-F圖所示的順序。控制旋鈕的設定及/或調整， 物種分配’製程氣體流的方向，製程氣體的注入位置及 基材及/或基材支撐件的溫度曲線可在該薄膜堆1〇〇的任 何一層的蝕刻期間或在各層的蝕刻之間被實施。 _ 首先參照第l〇A圖，一薄膜堆100被提供，它包括一 光阻層1002，一 BARC層1004，一硬罩層1006，一閘 極電極層1008及一設置在一基材1〇14上的閘極介電 層。該閘極介電層可包括一高k層1010及一非必要的底 下多晶矽層1012。該基材1〇14可以是半導體基材，矽 基材’玻璃基材及類此者中的任何一種。包含該薄膜堆 1000在内的層可用一或多種適當的傳統沉積技術，譬 如’原子層沉積（ALD) ’物理氣相沉積（PVD)，化學氣相 沉積（CVD)，電漿強化的CVD(PECVD)，及類此者來製 19 1323011 造。該薄膜堆1000可由設在美國加州Santa Clara市的 Applied Materials 公司所製造的 CENTURA® ， PRODUCER®，ENDURA®及其它半導體基材製程系統用 來沉積。在示於第10A圖的實施例中，BARC層1004的 一部分透過形成在該光阻層 1002上的一或多個孔洞 1016而被露出來。該薄膜堆經由這些孔洞1016而被蝕 刻。 薄膜堆1000的蝕刻包括首先蝕刻該BARC層1004。 該B ARC層1004典型地為一有機材質，以方便光阻層 1002被形成圖樣。在BARC層1004的蝕刻期間，流入 到該處理室中的製程氣體流被大致相等的分到第一出口 埠604及第二出口埠606，用以控制在處理室内的物種 分配。在其它實施例中，蝕刻該BARC層1004可在從出 口埠604提供100%的流體到從出口埠606提供100%的 流體之間變動，包括了界定於它們之間之埠604至埠606 的整個流體比例。在BARC層1004如第10B圖所示地已 被蝕刻之後，孔洞1016被用來蝕刻硬罩層1006，如第 10C圖所示。 硬罩層1006可以是Si02，Si03，SiON或其它適當的 物質。在蝕刻硬罩層1006期間，進入到該處理室内的製 程氣體的至少50%會是從出口埠606被提供的。在其它 實施例中，該硬罩層蝕刻使用的氣體流分配在出口埠 604，606之間是大致相等的，或者是在出口埠604，606 之間的比例是約25 : 75。在另一實施例中，該製程氣體 20 1323011 流最好是從出口埠606被提供。當該硬罩層1〇〇6被蝕刻 之後’該閘極電極層1008即被蝕刻，如第10D圖所示。 該閘極電極層1008可包含一多晶矽層或一沉積在一 多日日珍層上的金屬層。該多晶梦層可以是α-Si或c-Si。 適合使用在該閘極電極層1008上的金屬層包括有鶴 (W) ’氮化鎢（wSi)，多晶矽鎢（W/poly)，鎢合金，钽（Ta)， 氮化纽（TaN)，矽化钽氮化物（TaSiN)，氮化鈦（TiN)，或 它們的組合。 閘極電極層1008的蝕刻可分段為主蝕刻步驟，軟著陸 (soft landing)钱刻步驟及過度姓刻（over etch)步驟。每一 個步驟都具有一或多個製程參數依據本發明被不同地設 定。例如，在主蝕刻及軟著陸蝕刻步驟時，最好是讓製 程氣體流經出口埠604，而在過度餘刻步驟時則平均地 從出口埠604，606提供。在其它實施例中，該過度蝕刻 步驟最好是讓製程氣體流經出口埠606。適用來姓刻間 極電極層1008的製程氣體包括HBr，BC13，HC1，氣氣 (Ch)，三氟化氮（NF3) ’六氟化硫氣體（SF6)，及含碳與敦 氣體，如，CF4，CHF3，C4F8，中的至少一者。 數種製程參數在蝕刻期間會被調整。在一實施例中， 該室壓被調整於約2mTorr至約lOOmTorr之間。一介於 約100瓦至約1500瓦之間的RF源功率可被施加用以維 持一由製程氣體形成的電漿。 在蝕刻該閘極電極層1008之間，該閘極介電層被银 刻。適合的閘極介電層的物質包括，但不侷限於，氧化 21 丄 物層，一含氮層，一氧化物與含氮層的混合層，至少一 或多層氧化物層夾住一含氮層，等等。在一實施例中， 該閘極介電層物質為一高k物質（高k物質具有大於4 〇 的介電㊉數）。向k物質的例子包括二氧化給（Hf〇2)，二 氧化錯（Zr〇2)，矽氧化铪（HfSi〇2)，矽氧化锆（ZrSi〇2)， 二氧化鈕（Ta〇2) ’氧化鋁，摻雜了二氧化铪的鋁，鉍锶 鈦（BST) ’及鉑錯鈦（ΡΖΤ)，等等。 在示於第10Α-Ε圖的實施例中，該閘極介電層被顯示 為面Κ層1010及一多晶石夕層1〇丨2。該多晶石夕層1〇12 可如上文所述地被蝕刻。該高尺層1010可藉由將該層 1010曝露在一含一氧化碳的電漿及一含齒素的氣體中來 被蝕刻。在蝕刻閘極介電層之後，該光阻層1〇〇2可藉由 使用一剝除製程，譬如藉由曝露到一含氧電漿中，而被 去除掉，如第10F圖所示。 蝕刻方法700，800，900可被用來製造一淺溝渠隔離 (sti)結構，如第11A_C圖所示的順序。控制旋鈕物種 釦配，製程氣體流的方向，製程氣體注入位置及基材及/ 或基材支撐件的溫度曲線的設定及/或調整可在蝕刻該 薄膜堆的任何一層期間或蝕刻各層之間被實施。 首先參照第11A圖，該薄膜堆11〇〇包括一光阻層11〇2 及’儿積在一基材1106上的多晶矽層11〇4。該基材11〇6 可以疋半導體基材，矽基材，玻璃基材及類此者中的任 何一者。在示於第11A圖的實施例中，部分的多晶矽層 1104透過一或多個形成在該圖樣化的光阻層1102上的 22 1323011 孔洞1108而被外露。該薄膜堆丨1〇〇係透過該等孔洞ii〇8 被姓刻，用以形成該淺溝渠隔離（STI)結構。 該多晶石夕層1104係使用一含鹵素氣體’譬如Cl2， BC13，HC1，HBr，CF4及類此者’而被蝕刻，如第UB 圖中所示。該多晶石夕層的钱刻可用鈍化沉積步驟被圓柱 形地實施。多晶矽層的蝕刻可包括主蝕刻步驟，軟著陸 (soft landing)餘刻步驟及過度姓刻（over etch)步驟，其中 方法700，800，900可如上文所述地在這些蝕刻步驟中 的至少一個步驟中被實施。在蝕刻該多晶矽層11〇4之 後，該光阻層1102可藉由使用一剝除製程，譬如藉由曝 露到一含氧電漿中，而被去除掉，如第11C圖所示。 因此，一蝕刻製程已被提供，其可控制製程結果橫向 地跨越一基材的表面之分配。有利地，本發明的製程可 透過可調整的製程控制來獲得中心至邊緣之蝕刻深度、 CD偏移、微負載、側壁輪廟、純化、钱刻率、步階覆蓋 性、特徵結構錐度角及底切的實質上均勻分佈。 雖然以上所述係有關於本發明的實施例，但本發明的 其它及進一步實施例可在不偏離本發明的基本範圍下被 達成，且本發明的範圍翅由下面的申請專利範圍來界定 的》 【圖式簡單說明】 本發明之一更為特定的描述可藉由參照顯示於附圖中 23 1323011 之實施例而被作成’使得本發明之上述特徵，優點及目 地可被詳細地瞭解。然而’應注意的是，附圖中所示者 為本發明之典型的實施例，因此不應被認為是本發明範 . 圍的限制’因為本發明可以有其它等效的實施例》 第1A-B圖為閘極钱刻製程的示意圖； 第2圖為一圖表，其顯示平均cd偏移，基材溫度及 經過計算的黏著係數之間的關係； 第3圖為一圖表 '其顯.示產物質量分數（mass fraction) 與經過標準化的距離之間的關係； 第4圖為一圖表，其顯示蝕刻副產物通量與基材板徑 之間的關係； 第5圖為一圖表，其顯示CD偏移與基材半徑之間的 關係； 第6圖為一依據本發明的實施例之示範性半導體基材 製程室的示意圖； # 第7-9圖為可第6圖的製程室或其它製程室中實施之 飯刻製程的實施例的流程圖； 第10A-F圖顯示用來製造一結構的—連串順序的實施 例’該結構可使用第7圖，第8圖的方法，及/或第9圖 的方法來蝕刻；及 第11A-C圖顯示用來製造一結構的一連串順序的實施 例’該結構可使用第7圖’第8圖的方法，及/或第9圖 的方法來蝕刻。 為了便於瞭解，相同的標號被用來代表在所有圖中之 24 1323011 相同的元件。而且，一個實施例的元件及特徵可在沒有 進一步的詳述之下被包含到其它的實施例中。Rads = 2M (2) § However, the average value of Rads obtained by equation (2) corresponds to the value obtained by the fitting program within the temperature range considered. The relationship between the average CD offset and the substrate temperature between these three tests (r_) shows an average rate of change of 〇_8607 nm/°C. The corresponding percentage change in the adhesion coefficient, S*, is _〇·2%π. The calculation range of the adhesion coefficient shown in item 2 also coincides with the value obtained by the CL group incident on a charged ruthenium-based electrode. The _ standard deviation bar on the CD offset average of Fig. 2 is Measurement within the substrate (3) offset unevenness. The degree of unevenness is constant for all three substrate temperatures. The line width observed in the edge region is smaller than the line width in the central region. Under the condition that this condition is similar to the test, the measurement within the temperature uniformity of the substrate shows that the temperature of the stomach substrate is less than ±1C 'H means that the thickness of the substrate is not uniform in these examples. The observed in the sex is due to something other than the substrate temperature 〇 1323011 previous work shows that the reduction in CD offset at the edge of the substrate can be reduced by reducing the substrate The by-product concentration is caused. This concentration gradient is due to a more efficient removal of etch byproducts at the edge of the substrate relative to the center of the substrate. As a result, for a given substrate temperature, the local (1 〇 cal) adsorption rate at the edge of the substrate is reduced in the immediate vicinity of the adsorption site, i.e., the gate sidewall. The partial pressure of the passivated species can be partially controlled by the injection of gas into the chamber. Figure 3 shows the results of the simulation showing three different gas injection designs. When gas is injected into the chamber at the top of the chamber in a direction perpendicular to the surface of the substrate (labeled as center gas feed in Figure 3), the gas velocity due to the increase in convective flow increases. The density of the pioneer species at the center is actually reduced. Conversely, when the gas is injected into the chamber at a top end of the chamber in a direction parallel to the surface of the substrate (labeled as side gas feed in Figure 3), the gas flow to the surface of the substrate is more It is diffuse and a more uniform distribution of precursor species can be obtained. By utilizing the relationship between substrate temperature and adhesion coefficient and knowledge of etching byproducts in the etching chamber, substrate CD offset uniformity can be optimally achieved by introducing multiple temperature zones within the electrostatic chuck (ESC). Chemical. A corresponding radial requirement for the radial distribution of the etch byproduct of a typical gate etch process and the adhesion coefficient is shown in FIG. Since the adhesion coefficient is almost linear over a small temperature range as the temperature changes, the predicted temperature profile can very closely reflect the local gas phase species distribution. Therefore, for the edge region of the substrate, the desired substrate temperature must be relatively low to compensate for the reduction in purified species due to pumping. In fact, the reduction in surface temperature of the substrate can increase the adhesion coefficient of the passivation species to maintain a uniform and uniform flux to the adsorbed species on the surface of the substrate, and a uniform gate linewidth. Figure 5 shows three examples: a substrate at a uniform temperature, an optimized state with a two-zone ESC, and a process that is intentionally improperly adjusted to highlight CD offsets that are controlled on the entire substrate. ability. The uniform gate temperature condition of the smaller gate width at the edge of the substrate is observed in Figure 5 'When the temperature of the ESC is divided into two regions (where the temperature of the outer region is lower than the temperature of the inner region) A significant improvement in center-to-edge offset uniformity can be achieved. The ESC has a CD shift range of 15.3 nm at a uniform temperature, and the CD offset range of the two-zone ESC is 9.5 nm, and the improvement rate is 37.9%. The third example shows an exaggerated case of center-to-edge substrate temperature difference. The result is that the CD offset is intentionally oriented toward positive values to highlight the ability to control CD offset with substrate temperature. At the lowest substrate temperature, more by-products are absorbed at the sidewalls and a reversal effect is that the edge line width becomes wider than the line width in the substrate. In summary, the equilibrium adsorption theory can be used to account for trends observed during CD offset uniformity during the transistor gate etch process. In detail, the temperature dependence of the adhesion coefficient of the silver in-situ by-product is significant. Therefore, an ESC having a plurality of independently controllable temperature zones (e.g., those disposed in a DPS Π矽 etch chamber) is optimal for critical etch applications (e.g., gate etch). The same phenomenon is also likely to occur in other applications where sidewall 1323011 passivation is critical for CD performance, such as etching of aluminum wires or dielectric etching of contacts or via holes. • The etching process described herein can be used in a plasma etch chamber, such as a 'HART etch reactor, a HART TS etch reactor, a decoupled plasma source (DPS), DPS II, or DPS. Plus, or DPS DT Etch Reactor for CENTURA® Etching Systems, all of which are available from Applied Materials, Inc., Santa Clara, California. Plasma etch chambers from other manufacturers may also be used to practice the invention. The DPS reactor uses a 13.56 MHz inductive plasma source to generate and maintain a high density plasma and a 13.56 MHz source bias power to bias a substrate "decoupled" of the plasma and bias source. The essence allows ion energy and ion density to be independently controlled. The DPS reactor provides a wide process window for changes in source and pressure power, pressure, and etch gas chemistry and uses an endpoint system to determine the endpoint of the process. φ Figure 6 shows a schematic diagram of an exemplary etch reactor 600 that can be used to practice the present invention. The particular embodiment of the etch reactor 6A shown herein is provided for illustrative purposes and should not be used to limit the scope of the invention. Etch reactor 600 generally includes a processing chamber 61, a gas panel 638 and a controller 64A. The processing chamber 61 includes a conductive body (wall) 630 and a ceiling 62〇 that enclose a processing space. Processing gas is supplied from the gas panel 63 8 to the processing space of the chamber 610. The controller 640 includes a central processing unit (cpu) 644, a memory 12 1323011 642 'and a support circuit 646 » a controller 64 〇 coupled to the control member of the etch reactor 600 and controlling them, the process being in the chamber 61 It is implemented and facilitates an exchange of non-essential data with the database of founder circuit foundries. In the depicted embodiment, the ceiling 620 is a generally flat member. Other embodiments of the processing chamber 610 can have other types of ceilings, such as dome-shaped stencils. An antenna is disposed above the ceiling 610 and includes one or more inductive coil elements (two coaxial coil elements are shown in the figures). Antenna 612 is coupled to a mating network and radio frequency plasma power source 618. Power is supplied to the antenna 612 and inductively coupled to the plasma formed within the chamber 100 during processing. Alternatively, chamber 100 may utilize capacitive plasma to draw by using a power source 684, as will be described in more detail below. The gas panel 638 is coupled to one or more nozzles such that the flow of fluid entering the chamber through the nozzles can be controlled to control species distribution in the chamber. The one or more nozzles are constructed and/or arranged to perform at least one of a process gas flow location, a flow direction of the process gas stream, or a species distribution within the chamber. In one embodiment, a nozzle 608 having at least two outlet ports 604, 606 is provided for coupling to the ceiling 620 of the chamber body 610. The outlet 埠 604 ' 606 is constructed to cause a direct and an indirect air flow direction into the chamber, respectively. For example, the first outlet port 604 can provide a continuous airflow direction', i.e., create a flow of gas substantially perpendicular to the surface of the substrate into the chamber. The second outlet port 606 can provide an indirect flow 13 = to generate a gas flow that is substantially parallel to the surface of the substrate into the chamber or, in another embodiment, to be guided - relative to the The surface of the substrate is in a direction less than or equal to an incident angle of 60 degrees. One or more outlet ports 604, 606 can be placed on separate nozzles 6A (i.e., one for each nozzle). A tray assembly 616 is disposed at a position below the nozzle 608 in the interior space 6〇6 of the processing chamber 6〇〇. The tray assembly 616 holds the substrate 614 during processing. The tray assembly 616 generally includes a plurality of lift pins (not shown) disposed through the tray assembly that are configured to lift the substrate from the tray assembly 616 for convenient communication with a robot in a conventional manner ( The substrate 614 is exchanged without being shown. In one embodiment, the tray assembly 616 includes a mounting plate 662, a base 664 and an electrostatic chuck 666. The mounting plate 662 is coupled to the bottom 612 of the chamber body 630 and includes passages for arranging tubing, such as fluid lines, power lines and sensor leads, etc., to the base 664 and the collet 668. At least one of the electrostatic chuck 666 or the pedestal 664 includes at least one non-essential embedded heater 677, at least one non-essential buried insulator 674' and a plurality of conduits that are fluidly coupled to one A fluid source 672 for temperature regulating fluid is provided. In the embodiment shown in Fig. 6, a heater 676 is exemplarily shown in the electrostatic chuck 666 coupled to a power supply 678, and two separated by an annular insulator 674. A conduit 668 '670 is shown in the base 664. The conduit 668 '670 and the heater 676 can be used to control the temperature of the 1323011 of the tray assembly 616 to heat and/or cool the electrostatic chuck 666 to at least partially control the substrate 614 placed on the electrostatic chuck 666. temperature. Two separate cooling conduits 668, 670 formed within the base 664 define at least two independently controllable temperature zones. Additional cooling conduits and/or conduit layouts can also be arranged to define additional temperature control zones. In an embodiment, the first cooling duct 668 is arranged radially inward of the second cooling duct 670 such that the temperature control area is a concentric area. The conduits 668, 670 can be radially oriented or have other shapes. The cooling conduits 668, 670 can be coupled to a single source of temperature-controlled heat transfer fluid or can be separately coupled to a separate heat transfer fluid source. The insulator 674 is made of a substance that is made of a substance The thermal conductivity is different from the thermal conductivity of the material of the region of the pedestal 664 adjacent thereto. In one embodiment, the insulator 674 has a thermal conductivity that is less than the thermal conductivity of the pedestal 664. In the embodiment shown in Fig. 6, the base 664 is made of aluminum or other metal material. In a further embodiment, insulator 674 can be formed from a material having an unequal orientation (i.e., thermal conductivity is related to direction). The insulator 674 is used to locally vary the rate of heat transfer of the tray assembly 616 to the conduit 668 ' 670 via the base 664 relative to the heat transfer rate through the substrate 664 that does not have an insulator on the heat transfer path. . An insulator 674 is laterally disposed between the first and second cooling conduits (10), _ to provide enhanced thermal insulation between the temperature control regions of the tray assembly 616. 15 1323011 In the embodiment shown in Fig. 6, the insulator 674 is disposed between the guides 668' 670 to thereby hinder lateral heat transfer and contribute to the lateral temperature control region of the tray assembly 616. Thus, by controlling the number, shape, size, position and heat transfer coefficient of the insert, the temperature profile of the electrostatic chuck 666 and the substrate 614 placed thereon can be controlled. Although the insulator 674 shown in Fig. 6 is an annular ring, the shape of the insulator 674 can have many different shapes. An optional thermal paste or glue (not shown) can be applied between the pedestal 664 and the electrostatic chuck 666. The conductive paste facilitates heat exchange between the electrostatic chuck 666 and the susceptor 64. In an exemplary embodiment, the adhesive mechanically bonds the electrostatic chuck 666 to the base 664. Alternatively, the tray assembly 616 can include a hardware (e.g., clip, screw, and the like) that is designed to secure the electrostatic chuck 666 to the base 664. The temperature of the electrostatic chuck 666 and the susceptor 64 is monitored using a plurality of sensors. In the embodiment shown in FIG. 6, a first temperature sensor 690 and a second temperature sensor 692 are radially spaced apart such that the first temperature sensor 690 can have a central region of the tray assembly 616. A metric temperature representation is provided to the controller 650, and the second temperature sensor 692 provides a metric temperature representation of a peripheral region of the tray assembly 616 to the controller 650. The electrostatic chuck 666 is disposed on the base 664 and surrounded by a cover ring 648. The electrostatic head 666 can be made of aluminum, ceramic, or other material suitable for supporting the substrate 614 during processing. In one embodiment, the 16 1323011 electrostatic chuck 666 is ceramic. Alternatively, the electrostatic chuck 666 can be replaced with a vacuum chuck, a mechanical chuck or other suitable substrate support. The electrostatic chuck 666 is generally constructed of ceramic or similar dielectric material and includes at least one clamping electrode 680 that is controlled by a chuck power supply 682. The electrode 680 (or other electrode disposed in the collet 666 or the pedestal 664) may optionally be spliced to one or more RF power sources for maintaining a power formed by process gases and/or other gases. The slurry was placed in the chamber 6 。. In the embodiment shown in Figure 6, electrode 680 is coupled to an RF power supply and mating circuit 684 which is capable of generating an RF signal for maintaining a plasma formed by the process gas in chamber 600. The electrostatic chuck 666 can also include a plurality of channels (not shown), such as grooves, which are formed on the substrate-receiving surface of the collet and fluidly coupled to a heat transfer gas (or back side gas) Source (not shown)", during operation, a backside gas (such as 'helium (He)) is supplied to the channel under controlled pressure to reinforce the electrostatic chuck 666 and the base Heat transfer between the materials 614. Conventionally, at least the substrate support surface of the electrostatic chuck is provided with a coating that is resistant to the chemicals and temperatures used during the substrate processing. 7-9 are flow diagrams of embodiments of an etch process 700, 800, 900 that may be implemented in chamber 100 or other suitable processing chamber. Each process can be used to fabricate the structures shown in Figures 1A_F and UA_C. Although the process 700, 800, 900 is used to fabricate the gate structure in the first AF map and the shallow trench isolation (STI) structure in the 11A-C diagram, these processes can also be advantageously used for money. Engraving other structures. Processes 7〇〇, 8〇〇, 9〇〇 can be used to control the lateral distribution of results for each process. For example, the system 17 1323011 700 '800, 900 can be used to generate a substantially uniform center-to-edge distribution of the etch process results' where the process results include etch depth, CD offset, microloading, sidewall profile, passivation At least one of money engraving rate, step coverage, characteristic structure taper angle, and undereutting. The process 700 of Figure 7 begins at step 702 by determining a substrate temperature target curve which corresponds to a uniform deposition rate of etch byproducts on a substrate. At step 704', a temperature of a first portion of the substrate support is preferentially adjusted relative to a second portion of the substrate support to obtain the substrate temperature target curve on the substrate. 〇6, the substrate is etched at the temperature of the preferentially adjusted substrate. The process 800 of Fig. 8 begins at step 802, where a process control knob for performing a first process condition is provided, wherein the first process condition is represented by a first assignment of process results. In step 8A4, a process control knob for performing a second process condition is provided, wherein the second process condition is represented by a second assignment of process results. In step 8〇6, both the first and second process control knobs are set at a predetermined set position for generating a third assignment of the process result, wherein the third assignment of the process result is different from the process The first and second assignments of the results. At step 808, a substrate placed on a substrate support disposed within a processing chamber having first and second process control knobs set at the predetermined set position, wherein the first A process control knob selects a position at which the gas is injected into the processing chamber and the second process control knob selects a temperature profile of the substrate support member. 18 1323011 The process 900 of FIG. 9 begins at step 9〇2, which provides a substrate to a process that has an optional species assigned to the chamber and has a lateral temperature control base. The material support, wherein - the temperature profile induced by the substrate support and the selection of a species distribution comprise a set of control parameters. At step 904, a first layer of control is used to etch a first layer of material. At step 906, a second layer of control is used to etch a second layer of material, wherein the first and second sets of control parameters are different. Method 900 can be practiced during an incremental etch of a single layer, with each incremental etch step being treated as an etch step of a layer. The rice carving method 700, 800, 900 can be used to fabricate a value pole structure, such as the sequence shown in Figures 10A-F. Control knob setting and / or adjustment, species distribution 'process gas flow direction, process gas injection location and substrate and / or substrate support temperature curve can be etched during any layer of the film stack 1 〇〇 Or between the etching of the layers. Referring first to FIG. 1A, a film stack 100 is provided which includes a photoresist layer 1002, a BARC layer 1004, a hard mask layer 1006, a gate electrode layer 1008, and a substrate 1 The gate dielectric layer on 14. The gate dielectric layer can include a high-k layer 1010 and an optional underlying polysilicon layer 1012. The substrate 1〇14 may be any of a semiconductor substrate, a ruthenium substrate, a glass substrate, and the like. The layer comprising the film stack 1000 can be subjected to one or more suitable conventional deposition techniques such as 'atomic layer deposition (ALD)' physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced CVD ( PECVD), and the like to make 19 1323011. The film stack 1000 can be deposited by CENTURA®, PRODUCER®, ENDURA® and other semiconductor substrate processing systems manufactured by Applied Materials, Inc. of Santa Clara, California. In the embodiment shown in Fig. 10A, a portion of the BARC layer 1004 is exposed through one or more holes 1016 formed in the photoresist layer 1002. The film stack is etched through the holes 1016. Etching of the film stack 1000 includes first etching the BARC layer 1004. The B ARC layer 1004 is typically an organic material to facilitate formation of the photoresist layer 1002. During the etching of the BARC layer 1004, the process gas streams flowing into the processing chamber are distributed substantially equally to the first outlet port 604 and the second outlet port 606 for controlling species distribution within the processing chamber. In other embodiments, etching the BARC layer 1004 can vary between providing 100% of the fluid from the outlet port 604 to providing 100% of the fluid from the outlet port 606, including the crucibles 604 to 606 defined between them. The entire fluid ratio. After the BARC layer 1004 has been etched as shown in FIG. 10B, the holes 1016 are used to etch the hard mask layer 1006 as shown in FIG. 10C. The hard mask layer 1006 may be SiO 2 , SiO 3 , SiON or other suitable material. During etching of the hard mask layer 1006, at least 50% of the process gas entering the processing chamber may be provided from the exit port 606. In other embodiments, the gas flow distribution used for the hard mask etch is substantially equal between the exit ports 604, 606, or the ratio between the exit ports 604, 606 is about 25:75. In another embodiment, the process gas 20 1323011 flow is preferably provided from an outlet port 606. After the hard mask layer 1 is etched, the gate electrode layer 1008 is etched as shown in Fig. 10D. The gate electrode layer 1008 can comprise a polysilicon layer or a metal layer deposited over a multi-day day. The polycrystalline dream layer can be alpha-Si or c-Si. The metal layer suitable for use on the gate electrode layer 1008 includes a crane (W) 'tungsten nitride (wSi), polycrystalline tantalum tungsten (W/poly), a tungsten alloy, tantalum (Ta), and a tantalum nitride (TaN). Tantalum nitride (TaSiN), titanium nitride (TiN), or a combination thereof. The etching of the gate electrode layer 1008 can be segmented into a main etch step, a soft landing process and an over etch step. Each step has one or more process parameters that are differently set in accordance with the present invention. For example, in the main etch and soft landing etch steps, it is preferred to have process gas flowing through the exit port 604 and, on an excessive residual step, evenly from the exit ports 604, 606. In other embodiments, the overetching step preferably passes the process gas through the exit port 606. The process gases applicable to the inter-electrode electrode layer 1008 include HBr, BC13, HC1, gas (Ch), nitrogen trifluoride (NF3), sulfur hexafluoride gas (SF6), and carbon and gas, such as At least one of CF4, CHF3, and C4F8. Several process parameters are adjusted during the etch. In one embodiment, the chamber pressure is adjusted between about 2 mTorr and about 100 mTorr. An RF source power between about 100 watts and about 1500 watts can be applied to maintain a plasma formed by the process gas. Between etching the gate electrode layer 1008, the gate dielectric layer is silvered. Suitable materials for the gate dielectric layer include, but are not limited to, an oxide 21 layer, a nitrogen-containing layer, a mixed layer of a single oxide and a nitrogen-containing layer, and at least one or more oxide layers sandwiching a nitrogen-containing layer Layer, and so on. In one embodiment, the gate dielectric layer material is a high-k material (the high-k material has a dielectric number greater than 4 )). Examples of the k-substance include dihydrogenation (Hf〇2), dioxin (Zr〇2), antimony oxide (HfSi〇2), zirconium oxide (ZrSi〇2), and dioxide (Ta〇2) 'Alumina, aluminum doped with cerium oxide, bismuth titanium (BST)' and platinum titanium (ΡΖΤ), and the like. In the embodiment shown in Fig. 10, the gate dielectric layer is shown as a facet layer 1010 and a polycrystalline layer 1〇丨2. The polycrystalline layer 1 12 can be etched as described above. The high-scale layer 1010 can be etched by exposing the layer 1010 to a carbon monoxide-containing plasma and a dentate-containing gas. After etching the gate dielectric layer, the photoresist layer 1 2 can be removed by using a stripping process, such as by exposing it to an oxygen-containing plasma, as shown in Fig. 10F. The etching methods 700, 800, 900 can be used to fabricate a shallow trench isolation (sti) structure, as shown in Figure 11A_C. Control knob species snap-in, process gas flow direction, process gas injection location, and temperature profile of the substrate and/or substrate support can be set and/or adjusted during etching of any layer of the stack or between layers Implemented. Referring first to Fig. 11A, the film stack 11 includes a photoresist layer 11〇2 and a polysilicon layer 11〇4 which is deposited on a substrate 1106. The substrate 11〇6 may be any one of a semiconductor substrate, a tantalum substrate, a glass substrate, and the like. In the embodiment shown in Figure 11A, a portion of the polysilicon layer 1104 is exposed through one or more of the 22 1323011 holes 1108 formed in the patterned photoresist layer 1102. The film stack 1 is passed through the holes ii 〇 8 to form the shallow trench isolation (STI) structure. The polycrystalline layer 1104 is etched using a halogen-containing gas such as Cl2, BC13, HCl, HBr, CF4 and the like, as shown in the UB diagram. The money engraving of the polycrystalline layer can be carried out cylindrically by a passivation deposition step. The etching of the polysilicon layer may include a main etching step, a soft landing residual step, and an over etch step, wherein the method 700, 800, 900 may be at least one of these etching steps as described above The steps are implemented. After etching the polysilicon layer 11〇4, the photoresist layer 1102 can be removed by using a stripping process, such as by exposing it to an oxygen-containing plasma, as shown in Fig. 11C. Thus, an etch process has been provided which controls the distribution of process results across the surface of a substrate laterally. Advantageously, the process of the present invention can achieve center-to-edge etch depth, CD offset, microload, sidewall wheeling, purification, money engraving, step coverage, feature structure taper angle, and through adjustable process control. The undercut is substantially evenly distributed. While the above is a description of the embodiments of the present invention, other and further embodiments of the present invention can be achieved without departing from the basic scope of the invention, and the scope of the invention is defined by the scope of the following claims. BRIEF DESCRIPTION OF THE DRAWINGS A more particular description of the present invention can be made in the <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; However, it should be noted that the embodiments shown in the drawings are exemplary embodiments of the present invention and therefore should not be considered as a limitation of the scope of the present invention as the invention may have other equivalent embodiments. -B is a schematic diagram of the gate etching process; Figure 2 is a graph showing the relationship between the average cd offset, the substrate temperature and the calculated adhesion coefficient; Figure 3 is a diagram of 'display. The relationship between the mass fraction of the product and the normalized distance is shown; Figure 4 is a graph showing the relationship between the flux of the etching by-product and the diameter of the substrate; Figure 5 is a graph The relationship between the CD offset and the substrate radius is shown; FIG. 6 is a schematic view of an exemplary semiconductor substrate processing chamber in accordance with an embodiment of the present invention; #7-9 is a process chamber of FIG. Flowchart of an embodiment of a cooking process implemented in other process chambers; FIGS. 10A-F are diagrams showing a series of sequential embodiments for fabricating a structure. The structure may use the method of FIG. 7 and FIG. And/or the method of Figure 9 to etch; and the 11A-C diagram shows Manufacturing Example of a structure of a sequential series of 'the structure of FIG 7' of FIG. 8 method, or methods, and / in Fig. 9 is etched. For ease of understanding, the same reference numerals are used to refer to the same elements in the 24 1323011 in all figures. Furthermore, the elements and features of one embodiment may be included in other embodiments without further recitation.
【主要元件符號說明】 100 閘極結構 102 氣相物種 600 蝕刻反應器 610 處理室 620 天花板 630 導電本體（側壁） 638 氣體面板 640 控制器 644 中央處理單元 646 支援電路 618 配接網絡及射頻電漿電源 612 天線 684 電源 604 第一出口谭 606 第二出口埠 608 喷嘴 614 基材 616 托盤組件 662 安裝板 664 基座 668 夹頭 666 靜電夾頭 676 嵌埋式加熱器 674 嵌埋式絕緣體 672 流體源 668,670 導管 690 第一溫度感應器 692 第二溫度感應器 650 控制器 648 環蓋 682 夾頭電源 680 夾持電極 684 RF電源及配接電路 702 決定一基材溫度目標曲線 ，其相應於蝕刻副產 物在一基材上的均勻沉積速率 25 1323011 704偏好地調整一基材支揮件的一第一部分相對於 •該基枯支樓件的一第二部分的溫度’用以獲得於該基 - 材上之該基材溫度目標曲線 706 蝕刻在經過偏好地調整的基材支撐件上之該基 材 802提供一用來實施一第一製程條件的製程控制旋 紐，其中該第一製程條件是用製程結果的第一分配來 代表 # 804提供一用來實施一第二製程條件的製程控制旋 鈕，其中該第二製程條件是用製程結果的第二分配來 代表 806將該第一及第二製程控制旋紐兩者設定至一預 定的設定，用以產生製程結果的一第三分配，其中該 製程結果的第三分配不同於製程結果的第一及第二分 配 • 8〇8蝕刻一放置在一設置在一處理室内的基材支撐 件上的基材，該處理室具有被設定在該預定設定之第 一及第二製程控制旋鈕，其中該第一製程控制旋鈕選 擇氣體注入到該處理室的位置，及該第二製程控制旋 钮選擇該基材支撐件的溫度曲線 902提供一基材至一處理室中，該處理室具有—可選 擇的物種分配於該處理室内及一具有橫向溫度控制之 基材支撐件，#中—由該基材支撐件所引發的溫度曲 線及一物種分配選擇包含了一控制參數組 26 1323011 904使用第一控制參數組來蝕刻一第一物質層 906使用一第二控制參數組來蝕刻一第二物質層，其 中該第一與第二控制參數組是不相同的[Main component symbol description] 100 gate structure 102 gas phase species 600 etching reactor 610 processing chamber 620 ceiling 630 conductive body (side wall) 638 gas panel 640 controller 644 central processing unit 646 support circuit 618 mating network and radio frequency plasma Power Supply 612 Antenna 684 Power Supply 604 First Exit Tan 606 Second Exit 埠 608 Nozzle 614 Substrate 616 Pallet Assembly 662 Mounting Plate 664 Base 668 Chuck 666 Electrostatic Chuck 676 Embedded Heater 674 Embedded Insulator 672 Fluid Source 668,670 conduit 690 first temperature sensor 692 second temperature sensor 650 controller 648 ring cover 682 chuck power supply 680 clamping electrode 684 RF power supply and mating circuit 702 determines a substrate temperature target curve corresponding to etching by-product A uniform deposition rate 25 1323011 704 on a substrate preferentially adjusts the temperature of a first portion of a substrate support relative to a second portion of the base member to obtain the substrate The substrate temperature target curve 706 is etched onto the substrate on the preferentially adjusted substrate support 802 provides a process control knob for implementing a first process condition, wherein the first process condition is to provide a process control knob for implementing a second process condition by using a first assignment of process results to represent #804. The second process condition is to use the second allocation of the process result to represent 806 to set both the first and second process control knobs to a predetermined setting for generating a third allocation of the process result, wherein the second process The third assignment of the process results is different from the first and second dispenses of the process results. 8. 8 etching a substrate placed on a substrate support disposed within a processing chamber having a set at the predetermined Setting the first and second process control knobs, wherein the first process control knob selects a position at which gas is injected into the processing chamber, and the second process control knob selects a temperature profile 902 of the substrate support to provide a substrate to In a processing chamber, the processing chamber has an optional species distributed in the processing chamber and a substrate support having lateral temperature control, #中—from the substrate support The induced temperature profile and a species distribution selection comprise a control parameter set 26 1323011 904 using a first set of control parameters to etch a first material layer 906 using a second set of control parameters to etch a second material layer, wherein The first and second control parameter groups are different
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