TWI294673B - Semiconductor package with heatsink - Google Patents
Semiconductor package with heatsink Download PDFInfo
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- TWI294673B TWI294673B TW092110108A TW92110108A TWI294673B TW I294673 B TWI294673 B TW I294673B TW 092110108 A TW092110108 A TW 092110108A TW 92110108 A TW92110108 A TW 92110108A TW I294673 B TWI294673 B TW I294673B
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- Prior art keywords
- heat sink
- wafer
- semiconductor package
- substrate
- stress
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
1294673 五、發明說明（1) '一~~ ---— 【發明所屬之技術領域】 本發明係關於一種具散熱片之半導體封裝彳，尤指一 牙可釋放該散熱片之應力的半導體封裝件。 【先前技術】1294673 V. INSTRUCTION DESCRIPTION (1) '1~~ ---- TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor package having a heat sink, and more particularly to a semiconductor package capable of releasing the stress of the heat sink. Pieces. [Prior Art]
FrRr^ti 球拇陣列（FllP —CHP Ball Grid Array， "V 封l件係為一種同時具有覆晶與球栅陣列之 π二構以使至少一晶片的作用表面（Act ive Surf ace) ΰ猎由夕數紅塊（S〇ider Bumps)而電性連接至基板 之一表面上，並於該基板之另一表面上植設 夕=作為輸入/輸出（I/O)端之銲球（Solder Ball);此一 封裝結構由於可大幅縮減體積，以使該封裝件中晶片與基 板之比例更趨接近，同時亦減去習知金線（Wire)之設&， 而可降低阻抗提昇電性，以避免訊號於傳輸過程中產生扭 曲，因此確已成為下一世代晶片與電子元件的主流封裝技 由於該覆晶式球柵陣列封裝的優越特性，使其多係運 用於高積集度（Integration)之多晶片封裝件中，以符該 ，電'^元件之體積與運算需求，惟此類電子元件亦由於其 高運算特性，使其於運作過程所產生之熱能亦將較一般& 裝件為高，因此，其散熱效果是否良好即成為該類封^ 術影響品質良率的重要關鍵；對習知之覆晶式球柵陣^封 裝件而言，由於其晶片上並無金線與銲線墊（Finger)之設 計，故可直接將用以進行散熱之散熱片（Heat sink)黏罗 於該晶片的非作用表面（Non-act ive Surf ace)上，而不沒需FrRr^ti Ball Thumb Array (FllP-CHP Ball Grid Array, "V seal l is a π-two structure with both flip chip and ball grid array to make at least one wafer's active surface ace ΰ The hunting is electrically connected to one surface of the substrate by S〇ider Bumps, and implanted on the other surface of the substrate as the input/output (I/O) end solder ball ( Solder Ball); this package structure can greatly reduce the volume, so that the ratio of the wafer to the substrate in the package is closer, and the conventional wire setting & Electrically, to avoid distortion of the signal during transmission, it has become the mainstream packaging technology for next-generation wafers and electronic components. Due to the superior characteristics of the flip-chip ball grid array package, it is used in high-product sets. In the multi-chip package of "Integration", the volume and operation requirements of the electrical components are used. However, due to its high computational characteristics, such electronic components will also generate more thermal energy during operation. & the assembly is high, so its heat dissipation Whether the effect is good or not is the key to affecting the quality yield of this kind of sealing technology; for the conventional flip-chip ball grid array package, there is no gold wire and wire bond pad design on the wafer. Therefore, the heat sink for heat dissipation can be directly adhered to the non-active surface of the wafer without unnecessary
17154^S.ptd 第7頁 1294673 五、發明說明（2) 透過熱性較差的封裝膠體（gncapSU 1 an t )來傳遞熱ϊ ’ 從而形成一晶片—膠黏劑—散熱片—外界的直接散熱路徑， 達至退較其他封裝件為佳的散熱功效。 例如美國專利第5，9 0 9，0 5 6號專利，即提出一具有散 熱片的覆晶式球柵陣列封裝件5，其係如第6A圖所示，於 -基板50上設置支撐件51 (sti f f ener)，並將散熱片52黏 置於該支撲件51上，而以一樹脂53 (Epoxy)、膠帶 ^Tab)、或密封材料（Seal )接合該散熱片52與晶片54，以 务揮散熱功效；或如第6 β圖所示的另一實施例，以一相變 ^ CPha^e Change)材料55接合該散熱片52與晶片54，並以 /圖所不之屏障環5 6 ( Dam R i ng )避免該相變化材料5 5於 化”漏出該散熱片與晶片之接合層；此外，該專利 ^ Η ^ t第6C圖所示的另一實施例，係於該散熱片52上形 環狀固定部52，，以藉其將散熱片52接置於 二^"柃赦：樣可以該散熱片52與晶片54之直接黏接而 發揮快速散熱的功效。 惟此類習知覆晶式球^ 用其無金線之覆晶式^計散熱設計，雖可利 54之方式提昇其散熱效率 ^將=片52直接接觸晶片 品質問題，此係由於散埶片：：一接置方法卻將產生其他 至基板材料等之熱膨晶片㈣、膠黏劑、甚17154^S.ptd Page 7 1294673 V. INSTRUCTIONS (2) Passing the heat of the poorly encapsulated colloid (gncapSU 1 an t ) to form a wafer—adhesive—heat sink—the direct external heat dissipation path , to achieve better heat dissipation than other packages. For example, in the U.S. Patent No. 5,900,056, a flip-chip ball grid array package 5 having a heat sink is provided, as shown in FIG. 6A, and a support member is disposed on the substrate 50. 51 (sti ff ener), and the heat sink 52 is adhered to the splicing member 51, and the heat sink 52 and the wafer 54 are bonded by a resin 53 (Epoxy), a tape (Tab), or a sealing material (Seal). To dissipate the heat dissipation effect; or as another embodiment shown in FIG. 6β, the heat sink 52 and the wafer 54 are bonded by a phase change material 55, and the barrier is The ring 5 6 ( Dam R i ng ) prevents the phase change material 5 from "leading out the bonding layer between the heat sink and the wafer; in addition, another embodiment shown in FIG. 6C of the patent is attached to The heat sink 52 has an annular fixing portion 52, so that the heat sink 52 can be attached to the heat sink 52 to directly bond the heat sink 52 to the wafer 54 to achieve rapid heat dissipation. However, such a conventional flip-chip ball is designed with its gold-free flip-chip type heat dissipation design, although it can improve its heat dissipation efficiency by means of 54. Quality problems, this is due to the loose film:: a method of attachment will produce other heat-expanding wafers (4), adhesives, etc.
Expansion, CTE)均不同，因二 1Clent 〇f Thermal 測試中經歷極大之溫度變化日±b §該封裝件5於後續可靠度 能因材料熱應變量之差異，^ *不同材料的接合表面即可 ” 產生熱應力並衍生各種品質Expansion, CTE) are different, because of the extreme temperature change in the 1Clent 〇f Thermal test, ±b § The reliability of the package 5 in the subsequent reliability can be due to the difference of the material thermal strain, ^ * the joint surface of different materials can be Generate thermal stress and derive various qualities
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17154石夕品.口七(117154 Shi Xipin. 口七(1
1294673 — -- . 五、發明說明（3) 問題’以前述散熱片5 2與晶片5 4之接合表面為例，一般散 熱片所使用之銅材料其熱膨脹係數平均約在1 6. 3 ρριηΛ： 左右’而作為晶片之矽材料其熱膨脹係數則僅約為2. 8至 3· 3 ppm/C ’因此，當此類封裝件5於封裝完成而欲進行 後續遠如溫度循環試驗（Thermal Cycling Test, TST)、 熱震試驗（Thermal Shock Test，TST)、或高溫儲存試驗 (High Temperature Storage Life Test， HTST)等可靠度 測試時，即可能因高溫環境或溫度急遽變化之影響而形成 各種熱應力之破壞。 因此，對前述之覆晶式球栅陣列封裝件5而言，當其 處於一增溫環境時，此時熱膨脹係數較大之散熱片5 2所產 生的膨脹熱變形量將較晶片5 4為大，並受該散熱片5 2之中 央部位與晶片5 4相互黏接的拘束影響而產生一彎曲 (B e n d i n g )，如第7 A圖之剖視圖所示，將導致該散熱片5 2 與晶片54向上魅曲（Warpage)，同時，由於該散熱片5 2内 所產生之熱膨脹應力係較晶片5 4為大，故其彎曲變形量亦 將大於晶片5 4而使兩者有脫層61 (Delaminati on )之虞， 進而可能導致黏接於該散熱片5 4外圍的支撐件5 1受壓變 形，或降低晶片5 4下方之銲塊5 7的連接品質等；此外，若 自三維受力圖的角度觀之，可如第7B圖所示，將該處於增 溫環境的散熱片5 2視為一受到兩正交力矩Μ !、Μ 2作用之板 塊（Ρ 1 a t e )，亦即以Μ !、Μ 2模擬該散熱片5 2受熱所承受之 彎曲力矩（Bending Moment)’此時’其上表面52 a之X、y 方向（如圖所示）將分別產生一最大拉伸熱應力σ 1σ 91294673 — -- . V. INSTRUCTION DESCRIPTION (3) Problem 'With the joint surface of the heat sink 5 2 and the wafer 5 4 as an example, the copper material used in the heat sink generally has an average thermal expansion coefficient of about 16.3 ρριηΛ: The thermal expansion coefficient of the wafer as the material of the wafer is only about 2.8 to 3.3 ppm/C. Therefore, when such a package 5 is completed in the package, it is intended to be subjected to a subsequent thermal cycle test (Thermal Cycling Test). , TST), Thermal Shock Test (TST), or High Temperature Storage Life Test (HTST) and other reliability tests, which may form various thermal stresses due to high temperature environment or rapid temperature changes. The destruction. Therefore, for the above-mentioned flip-chip ball grid array package 5, when it is in a warming environment, the amount of thermal expansion deformation generated by the heat sink 52 having a large thermal expansion coefficient at this time will be lower than that of the wafer 54. Large, and subject to the restraint of the central portion of the heat sink 52 and the wafer 5 4, a bend occurs, as shown in the cross-sectional view of FIG. 7A, which will result in the heat sink 5 2 and the wafer. 54 upward warpage (Warpage), at the same time, since the thermal expansion stress generated in the heat sink 52 is larger than that of the wafer 54, the bending deformation amount will be larger than that of the wafer 54 to cause the two to have the delamination 61 ( After the Delaminati on), the support member 51 adhered to the periphery of the heat sink 54 may be deformed under pressure or the connection quality of the solder bumps 57 under the wafer 54 may be lowered; From the perspective of the figure, as shown in Fig. 7B, the heat sink 52 in the warming environment is regarded as a plate (Ρ 1 ate ) which is subjected to two orthogonal moments Μ !, Μ 2, that is, Μ !, Μ 2 simulates the bending moment of the heat sink 5 2 subjected to heat (Bending Moment) 'The upper surface of X 52 a, y direction (as shown) to generate a maximum tensile thermal stress σ 1σ 9
17154 矽品.ptd 第9頁 1294673 五、發明說明（4) (下表面52b為最大收縮熱應力），而產生如第7C圖所示之 翹曲變形（圖式中係略為放大該散熱片5 2之高度以加強說 明），導致其中央部位向上突起，而與晶片5 4表面分離脫 層，同時，由於該散熱片5 2之四周均係與該環狀支撐件5 1 黏接，將令其產生一周圍拘束的邊界條件，導致該散熱片 5 2發生板殼挫曲（Buckle)之現象，且亦將使其上、下表面 5 2 a、5 2 b之四周與角緣位置受拘束而承受一最大應力。 反之，當該覆晶式球柵陣列封裝件5處於一降溫環境 時，此時熱膨脹係數較大之散熱片5 2所產生的收縮熱變形 量將較晶片5 4為大，並受該散熱片5 2之中央部位與晶片5 4 相互黏接拘束的影響而產生一彎曲，如第8A圖之剖視圖所 示，將導致該散熱片5 2與晶片5 4向下翹曲，同時，由於該 散熱片52内所產生之熱收縮應力係較晶片54為大，故其彎 曲變形量亦將大於晶片5 4而對晶片5 4產生一下壓力，進而 可能導致晶片54受壓而破損62 (Crack)，形成電子元件之 破壞；此外，若自三維受力圖的角度觀之，可如第8 B圖所 示，將該處於增溫環境的散熱片5 2視為一受到兩正交力矩 Μ丨、Μ 2作用之板塊，亦即以Μ丨、Μ 2模擬該散熱片5 2降溫所 承受之彎曲力矩，此時，其上表面5 2 a之X、y方向（如圖所 示）將分別產生一最大收縮熱應力cr !、σ 2 (下表面5 2 b為 最大拉伸熱應力），而產生如第8C圖所示之輕曲變形（圖式 中係略為放大該散熱片5 2之高度以加強說明），導致該散 熱片5 2之中央向下壓陷，同時，由於該散熱片5 2之四周均 係與該環狀支撐件5 1黏接，將令其產生一周圍拘束的邊界17154 .品.ptd Page 9 1294673 V. Inventive Note (4) (The lower surface 52b is the maximum contraction thermal stress), and the warp deformation as shown in Fig. 7C is generated (the heat sink 5 is slightly enlarged in the drawing) 2 height to enhance the description), causing the central portion to protrude upward, and separate from the surface of the wafer 504, and at the same time, since the heat sink 5 2 is adhered to the annular support member 5 1 , it will be Producing a surrounding boundary condition, causing a phenomenon of bucking of the heat sink 52, and also restricting the periphery and the edge of the upper and lower surfaces 5 2 a, 5 2 b Withstand a maximum stress. On the other hand, when the flip-chip ball grid array package 5 is in a cooling environment, the amount of shrinkage heat deformation generated by the heat sink 52 having a large thermal expansion coefficient at this time will be larger than that of the wafer 54 and subject to the heat sink. A curvature is generated by the influence of the central portion of the film 5 and the wafer 5 4, as shown in the cross-sectional view of Fig. 8A, which causes the heat sink 52 and the wafer 54 to warp downward, and at the same time, due to the heat dissipation The heat shrinkage stress generated in the sheet 52 is larger than that of the wafer 54, so that the amount of bending deformation will be greater than that of the wafer 54 and the wafer 54 will be under pressure, which may cause the wafer 54 to be crushed and broken 62 (Crack). Destruction of the electronic component is formed; in addition, if viewed from the perspective of the three-dimensional force diagram, the heat sink 52 in the warming environment can be regarded as being subjected to two orthogonal moments, as shown in FIG. 8B.板 2 function of the plate, that is, Μ丨, Μ 2 simulate the bending moment of the heat sink 5 2 cooling, at this time, the X, y direction of the upper surface 5 2 a (as shown) will be generated separately a maximum contraction thermal stress cr !, σ 2 (the lower surface 5 2 b is the maximum tensile thermal stress , resulting in a slight curvature as shown in FIG. 8C (the height of the heat sink 52 is slightly enlarged in the drawing to enhance the description), causing the center of the heat sink 52 to be depressed downward, and at the same time, due to the heat dissipation The periphery of the sheet 5 2 is adhered to the annular support member 51, which will create a surrounding boundary.
17154石夕品.口士(1 第10頁 1294673 五、發明說明（5) 大^:其丨、下表面Wax Mb之四周與角緣位置承受 脫I分：。|可能進而形成該散熱片52與支撐件51間之 此外’前述因溫度改變所致 放，即便其未於測試過程中產生=法順利釋 壞，亦可能於該散熱片52上應力最厂口種結構破17154 Shi Xipin. Routine (1 Page 10 1294673 V. INSTRUCTIONS (5) Large ^: The circumference and the edge of the Wax Mb on the lower surface and the corner edge are subjected to a de-I::|The heat sink 52 may be formed further. In addition to the above-mentioned "between the temperature change caused by the support member 51, even if it is not produced during the test, the method can be smoothly released, and the stress on the heat sink 52 may be broken.
Stress)，進而可能於後續溫度 時，加速材料疲勞（Fatigue)之f件運作 5 2、晶片5 4或支撐件5 !的接合處 亥政熱片 裝件5的結構組成。 免產生延伸裂縫，破壞該封 … 用：ft球栅ΐ陣列封裝技術…為顧及製程 上的特殊用述’亦有部分於該散熱片開孔之設 計，例如美國專利第5, 9 0 9, 0 5 7號專利，其係歹;該…晶片上 之散熱片開設複數個孔洞，以作為後續填膠製程之入口， 惟其孔洞並非開設於該散熱片上應力最大之位置，且為使 填膠速度易於控制，所開設之孔洞口徑勢必不可過大‘，故 該孔洞設計非但無法解決前述的熱應力問題，反而可能因 其孔洞口徑過小，而於孔洞周圍之應力不連續點產生應力 集中（Stress Concentration)現象，進而加速封裝結構之 破壞。 同時，美國專利第5, 9 9 8, 242號專利亦提出一封裝結 構，係於散熱片上開設一小孔以連接外加之真空泵浦 (Vacuum Pump)，並藉其作用而維持晶片周圍的真空環Stress), in turn, may accelerate the fatigue of the material at the subsequent temperature. 5 2. The junction of the wafer 5 4 or the support 5! The configuration of the Hezhen hot plate assembly 5. Free of the occurrence of extended cracks, destroying the seal... With: ft ball grid array packaging technology ... to take into account the special description of the process 'also has some design of the heat sink opening, such as US Patent 5, 9 0 9, Patent No. 0 5 7 , which is a system; the heat sink on the wafer has a plurality of holes to be used as an entrance for the subsequent filling process, but the hole is not located at the maximum stress on the heat sink, and the filling speed is Easy to control, the opening of the hole must not be too large, so the hole design can not solve the above thermal stress problem, but may be due to the pore diameter is too small, and the stress concentration around the hole creates stress concentration (Stress Concentration) Phenomenon, which in turn accelerates the destruction of the package structure. At the same time, U.S. Patent No. 5,989,242 also discloses a package structure in which a small hole is formed in the heat sink to connect an external vacuum pump, and the vacuum ring around the wafer is maintained by the action thereof.
17154矽品邛士(117154 designer gentlemen (1
$ 11頁 1294673 ； ； 五、發明說明（6) 境，惟此單一孔洞之設計亦同樣無法解決該散熱片上的熱 應力問題，尤其當所配置之散熱片係與晶片相互黏接時， 該小孔周圍更可能產生應力集中所導致的破壞現象。 因此，綜觀前述的習知封裝結構，可知不論其所採用 之散熱片接置方式為樹脂、膠帶、密封墊或相變化材料， 或者不論其係於該散熱片上開設用於填膠或抽真空之孔 洞，倘若無法將該散熱片於可靠度測試中所產生之熱應力 於測試過程即立即釋放，勢難以避免此一熱應力所致的材 料變形問題，進而亦難以阻絕諸如翹曲、挫曲、脫層、晶 片受壓及銲塊變形等品質問題，且也將加速長期使用後材 料疲勞破壞之可能性，而降低該類封裝件的可靠度、電性 與散熱效率。 是故，如何開發一種具有散熱片的半導體封裝件，以 令該散熱片接觸晶片而提昇散熱效率之時，復能同時兼顧 其熱應力之擴散問題，以避免該封裝件之材料魅曲、脫層 或晶片受損，確為此一研究領域所需迫切解決之課題。 【内容】 因此，本發明之一目的即在於提供一種可於散熱片中 應力最大之位置釋放其應力的具有散熱片半導體封裝件。 本發明之復一目的在於提供一種可減少晶片所受壓力 以避免晶片破損的具有散熱片之半導體封裝件。 本發明之另一目的在於提供一種可避免散熱片與晶片 間產生脫層的具有散熱片之半導體封裝件。 本發明之再一目的在於提供一種可避免散熱片、晶片$11 page 1294673; ; 5, invention description (6), but the design of the single hole can not solve the thermal stress problem on the heat sink, especially when the configured heat sink and the wafer are bonded to each other. It is more likely to cause damage caused by stress concentration around the hole. Therefore, looking at the above-mentioned conventional package structure, it can be known that the heat sink is connected to a resin, a tape, a gasket or a phase change material, or whether it is attached to the heat sink for filling or vacuuming. Holes, if the thermal stress generated by the heat sink in the reliability test cannot be released immediately during the test, it is difficult to avoid the problem of material deformation caused by the thermal stress, and it is difficult to prevent such as warpage, buckling, Quality problems such as delamination, wafer compression and solder bump deformation, and will also accelerate the possibility of material fatigue damage after long-term use, and reduce the reliability, electrical and heat dissipation efficiency of such packages. Therefore, how to develop a semiconductor package with a heat sink to make the heat sink contact the wafer to improve the heat dissipation efficiency, the complex energy also takes into account the diffusion of thermal stress to avoid the material of the package Damage to layers or wafers is a pressing issue for this area of research. [Embodiment] It is therefore an object of the present invention to provide a heat sink semiconductor package which can release its stress at a position where stress is greatest in the heat sink. It is a further object of the present invention to provide a semiconductor package having a heat sink that reduces the stress on the wafer to avoid breakage of the wafer. Another object of the present invention is to provide a semiconductor package having a heat sink which avoids delamination between the heat sink and the wafer. A further object of the present invention is to provide a heat sink and a wafer that can be avoided.
17154^&.ptd 第12頁 1294673 五、發明說明（7) 與基板發生翹曲變形的具有散熱片之半導體封裝件。 本發明之又一目的在於提供一種可確保銲塊連接品質 的具有散熱片之半導體封裝件。 ' 為達前述及其他目的，本發明所提供之具散熱片之半 V體封裝件，係包括：基板，係具有一第一表面與一相對 之第二表面；至少一晶片，係具有一第一表面與一相對之 第二表面，並以其第二表面設置於該基板之第一表面上且 電性連接至該基板；至少一支撐件，係設置於該基板之第 一表面上；散熱片，係設置於該支撐件上，以令該晶片位 於該散熱片與支撐件所定義而成之圍置空間中，並令該晶 片之弟一表面與該散熱片接觸，其中，該散熱片各邊連接 之角緣處之中的至少一組相互對稱位置，係分別開設有可 貫穿該散熱片之鏤空部，以藉該鏤空部釋放該散熱片之應 力；以及多數銲球，係植接於該基板之第二表面上。 該散熱片亦可設計成具有一平坦部與自該平坦部而朝 該基板方向延伸的支撐部，以藉該散熱片之支撐部取代該 支撐件，而令該支撐部設置於該基板之第一表面上，使該 晶片位於該平坦部與支撐部所定義而成之圍置空間中’旅 令該晶片之第一表面與該平垣部接觸，同時，該平坦部各 邊連接之角緣處之中的至少一組相互對稱位置，亦分別開 設有可貫穿該平坦部之鏤空部。 前述之鏤空部係為一具有足夠鏤空面積的鏤空孔槽’ 其係開設於該散熱片上之表面或其平坦部之各邊連接的角 緣處。為達至較佳的應力釋放功效，其開設位置係相互對17154^&.ptd Page 12 1294673 V. Description of the Invention (7) A semiconductor package having a heat sink which is warped with a substrate. It is still another object of the present invention to provide a semiconductor package having a heat sink which ensures the quality of solder bump connection. For the above and other purposes, a half-V body package having a heat sink according to the present invention includes: a substrate having a first surface and an opposite second surface; at least one wafer having a first a surface opposite to a second surface and having a second surface disposed on the first surface of the substrate and electrically connected to the substrate; at least one support member disposed on the first surface of the substrate; a sheet is disposed on the support member such that the wafer is located in a defined space defined by the heat sink and the support member, and a surface of the wafer is in contact with the heat sink, wherein the heat sink At least one of the symmetrical positions of the corner edges of the respective sides is respectively provided with a hollow portion through which the heat sink can be inserted to release the stress of the heat sink by the hollow portion; and the majority of the solder balls are spliced On the second surface of the substrate. The heat sink may be configured to have a flat portion and a support portion extending from the flat portion toward the substrate, so as to replace the support member with the support portion of the heat sink, and the support portion is disposed on the substrate a surface, the wafer is located in the surrounding space defined by the flat portion and the support portion, and the first surface of the wafer is in contact with the flat portion, and at the same time, the corners of the flat portions are connected At least one of the mutually symmetric positions is also provided with a hollow portion through which the flat portion can be inserted. The aforementioned hollow portion is a hollow hole groove having a sufficiently hollow area which is formed on the surface of the heat sink or at the corner where the sides of the flat portion are joined. In order to achieve better stress-relieving effect, the opening positions are mutually opposite.
17154矽品.ptd 第13頁 1294673 五、發明說明（8) 稱，同時復具有一足夠大的開設面積’以令該 應力可進行一均勾且有效的緩衝釋放。 本發明即係利用該複數個鏤空孔槽’以於 於溫度變化之環境而產生熱應力時’藉由該貫 孔槽釋放其熱應力’並緩和該散熱片之彎曲熱 散熱片與支撐件接觸之拘束區域所產生的熱應 於其應力產生處係鄰近於該孔槽，故可藉此一 於應力產生後即快速釋放’並令該應力無法繼 對該散熱片與晶片接觸之中央拘束區域所產生 言，則可於其擴散至該散熱片各邊角緣之孔槽 避免該散熱片與晶片的變形。 因此，本發明之具散熱片之半導體封裝件 於例如覆晶式球拇陣列封裝件寺封裝技術中， 熱片直接接觸晶片以提昇其散熱效率時，藉由 而釋放熱應力並阻止其擴散，從而可避免該封 如魅曲、脫層、sa片受4貝、麵塊破壞或材料疲 結構問題。 【實施方式】 弟1 A圖係為本發明之具有散熱片半導體封 實施例剖視圖’其係為一覆晶式球栅陣列封裝 散熱片上之 該封裝件處 穿散熱片之 變形；對該 力而言，由 孔槽設計而 續擴散，而 的熱應力而 時釋放，以 ’即可運用 以當將該散 該孔槽設計 裝件產生諸 勞等習知的 裝件的較佳 件1 e r )之基板 1 〇之第一表 ^ 1 〇 a的環狀 L撐件2 0與 (FCBGA)，包括一作為晶片承載件（chip Carri 1 Ο ’以録塊1 2電性連接至基板1 q且接置於基板 面1 0 a上的晶片11，接置於該基板i 〇之第一表佳 支撐件20 (St 1 f f ener Ring)，接置於該環狀」17154矽品.ptd Page 13 1294673 V. Inventive Note (8) It is said that it has a large enough opening area to enable the stress to be uniformly and effectively buffered. In the present invention, the plurality of hollow holes are used to generate thermal stress when the temperature changes environment, 'the thermal stress is released by the through hole groove' and the curved heat sink of the heat sink is contacted with the support member. The heat generated by the restrained area should be adjacent to the hole in the stress generation zone, so that the stress can be quickly released after the stress is generated, and the stress cannot be passed to the central restraint region where the heat sink is in contact with the wafer. As a result, it can be diffused to the holes of the corner edges of the fins to avoid deformation of the fins and the wafer. Therefore, the semiconductor package with the heat sink of the present invention is used in, for example, a flip-chip ball array package package technology, in which the heat sheet directly contacts the wafer to improve its heat dissipation efficiency, thereby releasing thermal stress and preventing diffusion thereof. Therefore, the seal can be avoided, such as enchantment, delamination, sa film, 4 block, face block damage or material fatigue structure problems. [Embodiment] FIG. 1A is a cross-sectional view of a heat sink semiconductor package embodiment of the present invention, which is a deformation of the package on a flip-chip ball grid array package heat sink through a heat sink; In other words, the hole is designed to continue to diffuse, and the thermal stress is released in time, so that it can be used to produce the preferred piece of the conventional assembly such as the groove. The first surface of the substrate 1 ^a, the annular L struts 20 and (FCBGA), including a chip carrier (chip Carri 1 Ο ' electrically connected to the substrate 1 2 and The wafer 11 placed on the substrate surface 10 a is attached to the first support member 20 (St 1 ff ener Ring) of the substrate i, and is placed in the ring shape.
17154矽品4七(1 第14頁 1294673 五、發明說明（9) 晶片1 1表面的散熱片3 0，以及植接於該基板1 〇之第二表面 1 0 b且與該多數鮮塊1 2電性連接的多數銲球1 3 ;其中，該 散熱片3 0之周圍各邊連接角緣處係分別開設有貫穿該散熱 片3 0的鏤空部31a。 … 該散熱片3 0係選用一錢有鎳的銅材料 (Ni-Plated-Cu)，將其製成具有約2〇至4〇密爾（mi υ之厚 度的板狀散熱片3 0，並於其表面開設預定之鏤空部3丨&， 此型材料與尺寸之散熱片30約可達至2至4 W/cni· k的熱傳 攻率；同時’該環狀支撐件2 0所選用之材料係與該散熱片 3 0相同，以避免其於接合表面發生熱膨脹係數不匹配（cte Mismatch)之翹曲或脫層情形，且由於該鍍鎳銅材料之熱 月^脹係數亦與習用之基板1 〇材料（例如環氧樹脂、聚亞酉^ 胺、BT樹脂或FR撕脂等）相近，故亦可令該環狀支標件 與基板1 0間產生翹曲或脫層之可能性降至最低，其中 ▲ 環狀支撐件20之高度約可設計成10至4〇密爾（ιηίυ'，並’ 4 值可視晶片1 1之厚度或配置層數而定。 /、 第1Β圖即為前述散熱片30之上視圖，本實施 片係為一方形散熱片30,其虛線所示分別為該晶 月欠2 Τ散熱片之外緣位置U’、以及該圍置成方框區/置於 支撐件2 0接置於該散熱片3 0之内緣位置2 〇， ^」衣狀 :件2。之相對外緣係與該散熱片3〇的外緣相互且二環狀支 中，圖示之鏤空部3 1 a即為本發明中 4片，其 釋放孔槽，其係分別開設於該散埶片’應力的應力 連接角緣處，且並未與該環狀支撑杜對私的四邊 千Z 〇接觸，以發揮其應17154矽品四七(1 Page 14 1294673 5. V. INSTRUCTION (9) The heat sink 30 on the surface of the wafer 1 1 and the second surface 10 b implanted on the substrate 1 and with the majority of the fresh block 1 2, the majority of the solder balls 1 3 are electrically connected; wherein the peripheral edges of the heat sinks 30 are respectively provided with hollow portions 31a penetrating the heat sinks 30. The heat sinks 30 are selected A nickel-based copper material (Ni-Plated-Cu) is formed into a plate-like heat sink 30 having a thickness of about 2 〇 to 4 〇 mil (a thickness of mi υ, and a predetermined hollow portion 3 is opened on the surface thereof.丨&, the heat sink 30 of this type of material and size can reach a heat transfer rate of about 2 to 4 W/cni·k; and the material selected for the annular support 20 is the heat sink 3 0 is the same to avoid the warpage or delamination of the thermal expansion coefficient mismatch (cte Mismatch) on the joint surface, and since the thermal expansion coefficient of the nickel-plated copper material is also the same as the conventional substrate 1 〇 material (for example, a ring) Oxygen resin, polyarylene oxide, BT resin or FR resin, etc.) are similar, so that the ring-shaped support member and the substrate 10 may be warped or delaminated. The energy properties are minimized, wherein ▲ the height of the annular support member 20 can be designed to be 10 to 4 mils (ιηίυ', and the value of 4 can be determined by the thickness of the wafer 11 or the number of layers to be arranged. /, 1st The figure is a top view of the heat sink 30. The embodiment is a square heat sink 30, and the dotted line shows the outer edge position U' of the heat sink, which is shown by a broken line, and the square is arranged in a box. The area/position support member 20 is placed at the inner edge position of the heat sink 30, 2 〇, ^" clothing shape: member 2. The opposite outer edge is mutually and bi-ringed with the outer edge of the heat sink 3〇. In the branch, the illustrated hollow portion 3 1 a is the four sheets in the present invention, and the release slot is respectively opened at the stress connection corner of the dilated sheet, and is not connected with the annular support. Du is in contact with the private side of the four sides to play its role
1294673 五、發明說明（ίο) 力釋放功能，同時，該應力釋放孔槽313之開設形狀係如 圖所示為一直角形溝槽，其邊緣轉折係對齊於該散孰片3〇 與環狀支撐件20之邊緣轉折’且該直角形溝槽3U係具有 一溝槽寬度d，該溝槽需具有一足夠之寬度，以令該應力 釋放孔槽31 a具有足夠大的面積’而可加強其應力釋放之 功效，此係由於H應办釋放孔槽3la之面積過小，例如 僅開設成一小孔徑貫穿孔或一細缝，則其應力釋放'能力非 但有限，且反而可能於該貫穿孔或細縫周圍之應力不連續 點形成應力集中（Stress Concentrati〇n)現象，導致g區 域應力的不正常放大，而〜難達至本發明之功效。 因此，本實施例之半導體封袭#1，即可萨 釋放孔槽31a，而於該散熱片30中央之晶片u^接處^生 應力、並於其表面向四角緣擴散時發揮緩衝的功效，以將 該應力於產生之同時即自該孔槽31a釋放掉，如第2a圖之 散熱片30立體視圖，當該封裝件丨處於一增溫環境時，由 於該散熱片30之熱膨脹係數較晶片i !為大， 埶 亦將大於該晶片"之變形量，導致其具有一向：輕曲』 勢，可視為如第7B圖所示之受到兩正交力矩M丨、M 2作用的 板1\此時該散熱片30之上表面3仏的X、y方向（如圖所 不別產生一最大拉伸熱應力σ !、σ 2(下表面為最大 ΐ::: f ΐ )，惟由於本實施例中已預先於該散熱片30與 件20拘束連接之角緣位置，貫穿開設有四應力 ila，故該熱應力將可於延伸至各角緣之孔槽3ia 位置日守釋& ’使得分布於該散熱片30上之熱應力大幅降1294673 V. Inventive Description (ίο) The force release function, at the same time, the opening shape of the stress relief hole 313 is a straight-shaped groove as shown in the figure, and the edge turning line is aligned with the dilated piece 3 环状 and the annular support The edge of the piece 20 is turned to turn 'and the right-angled groove 3U has a groove width d, and the groove needs to have a sufficient width so that the stress relief hole 31 a has a large enough area to strengthen it The effect of stress release is due to the fact that the area of the H release orifice 3la is too small, for example, only a small aperture through hole or a slit is formed, the stress release capability is not limited, but may be in the through hole or thin The stress concentration around the slit forms a stress concentration (Stress Concentrati〇n) phenomenon, which causes an abnormal enlargement of the stress in the g region, and it is difficult to achieve the effect of the present invention. Therefore, the semiconductor encapsulation #1 of the present embodiment can release the hole 31a, and the wafer is placed at the center of the heat sink 30, and the buffer is effective when the surface is diffused toward the four corners. In order to release the stress from the hole 31a at the same time as the generation, as shown in the perspective view of the heat sink 30 of FIG. 2a, when the package is in a warming environment, the thermal expansion coefficient of the heat sink 30 is higher. The wafer i! is large, and the 埶 will also be larger than the deformation amount of the wafer, resulting in a direct: light curvature, which can be regarded as a plate subjected to two orthogonal moments M丨, M 2 as shown in Fig. 7B. 1\ At this time, the X, y direction of the upper surface of the heat sink 30 is 3 ( (as shown in the figure, a maximum tensile thermal stress σ !, σ 2 (the lower surface is the maximum ΐ::: f ΐ )) In this embodiment, the four stress ila is inserted through the corner position of the heat sink 30 and the member 20, and the thermal stress will be extended to the position of the hole 3ia of each corner. ; 'The thermal stress distributed on the heat sink 30 is greatly reduced
17154矽品邛士(1 第16頁 向 延 使 晶 1294673 五、發明說明（11) 低’即可如第2B圖所干 不致形成該散熱減緩其輕曲變 降等相關問題，、也=^片11之分離或 3〇中的殘餘應力不致令該熱應力轉變 下I夕二忒封裝件1處於一降溫環ij 伸至四备续1，惟造成其翹曲之收縮 彳胃^ t 、、'蛉，藉由該應力釋放孔槽 HiΓ玄散熱片30上之熱應力大幅 π M t ί t或该散熱片3 0與環狀支撐件 f因h餘應力所形成的材料疲勞問 之曰T不例相同，故不再另以圖式說明 本發明中開設於該散熱片3〇周圍的 =^僅限於前述較佳實施例之形狀，一 ^ f散熱片3 0拘束區域的位置開設複數 〈二，積的孔槽即可，例如第3 A、3B、 =貫施例，係於該散熱片3 0各邊連接之 〇又’、有直角二角形3 1 b、對齊於該支撑^ 3 1 ~與該支撐件内緣直角成一傾斜之： 3 1 e等各種形狀的應力釋放孔槽，則亦 因此’根據前述各實施例可知，該 之鎮空孔槽的形狀、位置、甚至數量並 希J 僅品令其貫穿該散熱片3 0上未與晶 布位置 同時亦具有一足夠大的鎮空面 般而言’當開設於該散熱片30上之孔槽 形糕度，同時，亦 錄塊1 2連接品質下 成累積於該散熱片 L時，雖亦具有一 熱應力亦同樣可於 3 la而自然釋放’ 降低，而不致導致 2 0脫層之問題’也 題，其功效與前述 之。 應力釋放孔槽3 1 a 般而言，僅需於鄰 個相互對稱且具有 3C、3D圖所示之其 角緣位置，分別開 ¥内緣直角之方形 7形31d、圓弧形 丁收相同之功效。 散熱片3 0上所開設 無一定之設計限 片11接觸之對稱分 積即可；此外，一 數目愈多或其鏤空17154 product gentleman (1 page 16 to Yan Jingjing 1294673 V. Invention description (11) Low ' can be formed as shown in Figure 2B without causing the heat dissipation to slow down its related problems, such as =^^ The separation of the sheet 11 or the residual stress in the 3 不 does not cause the thermal stress to change, and the cooling element ij extends to the fourth continuous one, but causes the warpage of the warp. '蛉, by the stress relief hole, the thermal stress on the heat sink 30 is substantially π M t ί t or the fins 30 and the annular support f due to h residual stress caused by the material fatigue 问T The same is not the same, so the description of the present invention is not limited to the shape of the preferred embodiment, and the position of the restraint region of the heat sink 30 is plural. Second, the slot can be accumulated, for example, the 3A, 3B, and the embodiment are connected to each side of the heat sink 30, and have a right angled corner 3 1 b, aligned with the support ^ 3 1 ~ is inclined at right angles to the inner edge of the support member: 3 1 e and other shapes of stress relief holes, and therefore For example, the shape, position, and even the number of the empty hole slots of the town are only made to pass through the heat sink 30 without being at the same time as the position of the crystal cloth and having a sufficiently large air gap. The hole-shaped shape of the heat sink 30 is also formed. When the temperature of the block is also accumulated in the heat sink L, the thermal stress can also be released naturally at 3 la. Without causing the problem of 20 delamination, the effect is the same as above. The stress relief hole 3 1 a generally only needs to be adjacent to each other and has the angular position shown in 3C and 3D. , respectively, open the square of the right edge of the square shape 7-shaped 31d, the arc-shaped shape of the same effect. The symmetrical distribution of the contact of the design limited piece 11 is not provided on the heat sink 30; in addition, the more the number Or hollowed out
17154矽品.於(1 第17頁17154矽品.于(1 page 17
1294673 五、發明說明（12) 面積愈大，所發揮之應力釋放功政亦將愈佳，惟其設計時 亦需考量加工成本與是否將導致散熱效率降低等因素，端 視使用者的需求考量而定。 本發明之具有散熱片之半導體封裝件1的較佳實施 例，其製法係如第4A至4F圖所示，其係先如第4A圖所示提 供一基板1 0，該基板1 〇係選自環氧樹脂、聚亞醯胺、BT樹 脂或FR4樹脂等材料；復如第4B圖，以一熱固性的膠黏劑 4 1將一環狀支撐件2 0接置於該基板1 0上（圖示為該環狀支 撐件2 0之剖視圖），並使其於該基板1 〇上圍置成一區域； 第4C圖所示即係以覆晶之方式，將一晶片丨丨的作用表面 1 1 a藉由多數個銲塊1 2接置於該基板1 〇之表面上，以使該 晶片1 1與基板1 0電性連接，並令該晶片Η位於該環狀支撐 件2 0所圍置之區域中，同時，復以一回銲（R e f丨〇 w )製程將 該封裝件加熱至約1 8 〇°C，以固定該多數個銲塊1 2，並於 清洗（(：16811)製程中清洗掉殘留之助銲劑（1?11^);第4])圖 則係以一底部填膠（Under f i 1 1 )材料42 (通常為一熱固性 樹脂）充填於各銲塊12之間，並進行固化（Curing)以支撐 晶片1 1重量’同時定位各銲塊丨2且避免銲塊丨2發生變形； 接著’如第4E圖所示，分別於該晶片u之非作用表面nb 與该裱狀支撐件20之表面上塗佈一導熱膠43 (Thermal Conductive Adhesive)，以將該開設有應力釋放孔槽3U 之散熱片3 0黏接於該晶片i i與環狀支撐件2 〇上，並令該散 熱片3G之邊緣與該環狀支撐件2()之外緣切齊，且使該晶片 11位於該散熱片30與環狀支撐件2〇所定義出之容置空間441294673 V. INSTRUCTIONS (12) The larger the area, the better the stress release strategy will be, but the design cost also needs to consider the processing cost and whether it will lead to the reduction of heat dissipation efficiency, etc. set. A preferred embodiment of the semiconductor package 1 having a heat sink according to the present invention is as shown in FIGS. 4A to 4F, and a substrate 10 is provided as shown in FIG. 4A. A material such as an epoxy resin, a polyamidamine, a BT resin or an FR4 resin; as in FIG. 4B, a ring-shaped support member 20 is attached to the substrate 10 by a thermosetting adhesive 41. The figure shows a cross-sectional view of the annular support member 20, and is arranged on the substrate 1 to form a region; FIG. 4C shows the application surface of a wafer cassette in a flip chip manner. 1 a is placed on the surface of the substrate 1 by a plurality of solder bumps 12 to electrically connect the wafer 11 to the substrate 10, and the wafer is placed around the annular support 20 In the region, at the same time, the package is heated to about 18 〇 ° C by a reflow process (R ef 丨〇 w ) to fix the plurality of solder bumps 1 2 and cleaned ((:16811) The residual flux (1?11^) is cleaned during the process; the 4]) plan is filled with an underfill material (Under fi 1 1 ) material 42 (usually a thermosetting resin). Between the blocks 12, and curing (Curing) to support the weight of the wafer 1 ' while positioning each of the solder bumps 2 and avoiding deformation of the solder bumps 2; then 'as shown in FIG. 4E, respectively Applying a thermal conductive adhesive 43 (Thermal Conductive Adhesive) to the surface of the action surface nb and the support member 20 to bond the heat sink 30 with the stress relief hole 3U to the wafer ii and the annular support 2, and the edge of the heat sink 3G is aligned with the outer edge of the annular support 2 (), and the wafer 11 is located in the heat sink 30 and the annular support 2 Space 44
1294673 ~ ~~ ' : ' ' --— 五、發明說明（13) 中·’最後，如第4F圖所示，於該基板1 〇之下表面1 Ob植接 上多數銲球1 3，以藉由貫穿該基板1 0之多數導電貫孔 (V i a)電性連接該銲球1 3與晶片11，而使晶片11可藉由該 多數銲球1 3而電性連接至外界之電路板。 而由於該散熱片3 0上係開設有該應力釋放孔槽3丨a， 因此，該散熱片30與環狀支撐件20所圍置之容置空間44係 可藉由該複數個孔槽3 1 a而與外界連通，故前述第4D圖之 底部填膠（Underf i 1 1)製程亦可於該散熱片30接置完成後 才進行，亦即以該應力釋放孔槽3丨3作為填膠之入口 (A c c e s s )，而於該熱固性樹脂材料進入該容置空間4後充 填於各銲塊1 2之間，可另收提昇該封裝件J量產效率之 效0 此外’前揭實施例之設計均係為一平板型散孰片3〇， 並將該散熱片30接置於基板10上之環狀支撐件2〇而使其與 該晶片1 1之非作用表面丨丨b接觸，惟本發明之半導體萝、 減且省：環狀支撑件20之設計，而直接將該散 熱片3 2$又计成具有一平坦部3 3與自該平 !。方向延伸的環狀支擇部34,而使該平坦； 撐部34—體成型，以如第5圖所示藉： 熱片32設置於基板10之表面上，並令該支晶拉' 4而將該散 部33與支樓，34所定義而成之容置空間仏中，== 11之:M:用表面1 ib與該平坦部33以一導 接“曰 中，邊平坦部33上係同樣開設有可貫穿該散H廊、 釋放孔槽31a，*同樣可於溫度環境變化，而使該散熱應片力1294673 ~ ~~ ' : ' ' --- V. Inventive Note (13) ·· Finally, as shown in Figure 4F, on the surface 1 of the substrate 1 Ob implanted a majority of solder balls 1 3 to The solder ball 13 and the wafer 11 are electrically connected through a plurality of conductive vias (Via) of the substrate 10, so that the wafer 11 can be electrically connected to the external circuit board by the majority of the solder balls 13. . The heat dissipation plate 30 and the accommodating space 44 surrounded by the annular support member 20 can be formed by the plurality of holes 3 . 1 a is connected to the outside, so the bottom fill (Underf i 1 1) process of the 4th drawing can also be performed after the heat sink 30 is completed, that is, the stress relief hole 3丨3 is used as a filling The inlet of the glue (A ccess ), and after the thermosetting resin material enters the accommodating space 4, is filled between the solder bumps 12, and can further improve the mass production efficiency of the package J. For example, the design is a flat-type diffuser 3〇, and the heat sink 30 is attached to the annular support member 2 on the substrate 10 to make contact with the non-active surface 丨丨b of the wafer 11. However, the semiconductor of the present invention is reduced in the design of the annular support member 20, and the heat sink 3 2$ is directly counted to have a flat portion 3 3 and a flat portion thereof. The direction extending portion of the annular portion 34 is made flat; the struts 34 are integrally formed to be borrowed as shown in FIG. 5: the heat sheet 32 is disposed on the surface of the substrate 10, and the branch is pulled '4 And the scatter portion 33 and the support space, 34 are defined as the accommodating space ,, == 11: M: the surface 1 ib and the flat portion 33 are connected by a 曰, 边, the flat portion 33 The upper system is also open to extend through the loose H gallery and release the slot 31a, and the same can be changed in the temperature environment, so that the heat dissipation should be force
17154 矽品.ptd 第19頁 1294673 五、發明說明（14) u 3 0與晶片11黏接之部位產生熱應力時，藉該應力釋放孔才曰 31a釋放並阻絕該熱應力之擴冑，亦可達至前述之本發明 功效。 本發明之具散熱片半導體封裝件1，其散熱片、30之形 狀並非僅如前述實施例所示為一方形，其形狀可視設計者 之封裝需求而定，而該散熱片30上所開設之應力釋放孔槽 的位置、形狀與數量亦可隨該散熱片30之形狀而隨之變 更；此外，前述實施例中所採之環狀支撐件2 0係為一圍置 成方形框的支撐件，惟其設計亦同樣有諸多選擇，且亦不 限於環狀設計，僅需達至接設於該基板1 0上而可支撐該散 熱片3 0之功能即可。 綜上所述，本發明之具散熱片半導體封裝件，確具有 可於散熱片中應力最大之位置釋放其應力的功效，同時， 復可減少晶片所受壓力，並避免散熱片、晶片與基板間產 生脫層或翹曲變形，進而可阻絕銲塊連接品質降低或材 疲勞破壞等習知結構問題。 ^ 惟以上所述者，僅為本發明之具體實施例而已，並 用以限定本發明之範圍’舉凡熟習此項技藝者在本發日’卜 揭示之精神與原理下所完成的一切等效改變或修饰7 所 於同一散熱片上開5又不同形狀之孔槽專，仍應皆由後述 專利範圍所涵蓋。 '之17154 .品.ptd Page 19 1294673 V. Description of the invention (14) When the thermal stress is generated in the portion where the bonding of the wafer 31 and the wafer 11 is generated, the stress relief hole is released and the expansion of the thermal stress is prevented. Up to the aforementioned effects of the present invention. In the heat sink chip package 1 of the present invention, the shape of the heat sink, 30 is not only a square as shown in the foregoing embodiment, and the shape thereof may be determined by the designer's packaging requirements, and the heat sink 30 is provided. The position, shape and number of the stress relief holes may also be changed according to the shape of the heat sink 30. In addition, the annular support member 20 taken in the foregoing embodiment is a support member that is arranged in a square frame. However, the design also has many options, and is not limited to the ring design, and only needs to be connected to the substrate 10 to support the function of the heat sink 30. In summary, the heat sink semiconductor package of the present invention has the effect of releasing stress in the position where the stress is greatest in the heat sink, and at the same time, reducing the pressure on the wafer and avoiding the heat sink, the wafer and the substrate. Debonding or warping deformation occurs, which in turn can prevent conventional structural problems such as reduced solder joint quality or material fatigue damage. The above is only the specific embodiment of the present invention, and is intended to limit the scope of the present invention. All equivalent changes made by those skilled in the art in light of the spirit and principles disclosed herein. Or modify the 7 holes on the same heat sink to open 5 different shapes, which should still be covered by the patent scope mentioned later. '
17154石夕品.口士(117154 Shi Xipin. Routine (1
1294673 圖式簡單說明 【圖式簡單說明】 第1 A圖係本發明之具散熱片半導體封裝件的較佳實施 例剖視圖； 第1 B圖係第1 A圖所示之半導體封裝件的散熱片上視 圖， 第2 A及2 B圖係第1 A圖所示之半導體封裝件於增温時的 熱應力施力示意圖； 第3A至3D圖係本發明之具散熱片半導體封裝件的散熱 片各實施例上視圖； 第4A至4F圖係本發明之具散熱片半導體封裝件的製法 流程圖， 第5圖係本發明之具散熱片半導體封裝件的另一實施 例剖視圖； 第6A至6C圖係美國專利第5, 9 0 9, 0 5 6號專利之習知具 散熱片半導體封裝件的各種實施例剖視圖； 第7A圖係習知具散熱片半導體封裝件於增溫時的熱應 力施力不意圖， 第7B及7C圖係第7A圖所示之半導體封裝件的散熱片於 增溫時之熱應力施力不意圖， 第8A圖係習知具散熱片半導體封裝件於降溫時的熱應 力施力示意圖；以及 第8B及8C圖係第8A圖所示之半導體封裝件的散熱片於 降溫時之熱應力施力示意圖。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a cross-sectional view of a preferred embodiment of a heat sink semiconductor package of the present invention; FIG. 1B is a heat sink of a semiconductor package shown in FIG. FIG. 2A and FIG. 2B are schematic diagrams showing thermal stress applied to the semiconductor package shown in FIG. 1A during warming; FIGS. 3A to 3D are heat sinks of the present invention having a heat sink semiconductor package. 4A to 4F are a flow chart of a method for fabricating a heat sink semiconductor package of the present invention, and Fig. 5 is a cross-sectional view showing another embodiment of the heat sink chip package of the present invention; Figs. 6A to 6C A cross-sectional view of various embodiments of a heat sink semiconductor package having a heat sink semiconductor package according to the patent of U.S. Patent No. 5,900,060; FIG. 7A is a view showing a thermal stress applied to a heat sink semiconductor package during warming. It is not intended that the heat sink of the semiconductor package shown in FIG. 7B and FIG. 7C is not intended to be subjected to thermal stress during temperature increase, and FIG. 8A is a conventional heat sink semiconductor package for cooling. Schematic diagram of thermal stress application; and 8B and The 8C diagram is a schematic diagram of the thermal stress applied to the heat sink of the semiconductor package shown in Fig. 8A at the time of cooling.
17154石夕品.口士(1 第21頁 1294673 圖式簡單說明 1 半 導 體 封 裝 件 10 基 板 10a 基 板 第 — 表 面 10b 基 板 第 二 表 面 11 晶 片 1 Γ 晶 片 外 緣 接 置 位 12 銲 塊 13 銲 球 20 環 狀 支 撐 件 2(Γ 支 撐 件 接 置 位 置 30 散 熱 片 3 0a 散 熱 片 上 表 面 31a 應 力 釋 放 孔 槽 31b 應 力 釋 放 孔 槽 31c 應 力 釋 放 孔 槽 31d 應 力 釋 放 孔 槽 31e 應 力 釋 放 孔 槽 32 散 熱 片 33 散 熱 片 平 坦 部 34 散 熱 片 支 撐 部 35 容 置 空 間 41 膠 黏 劑 42 底 部 填 膠 材 料 43 導 熱 膠 44 容 置 空 間 5 半 導 體 封 裝 件 50 基 板 51 支 撐 件 52 散 熱 片 52’ 散 熱 片 固 定 部 5 2a 散 熱 片 上 表 面 52b 散 熱 片 下 表 面 53 樹 脂 層 54 晶 片 55 相 變 化 材 料 56 屏 障 環 57 銲 塊 61 脫 層 62 晶 片 破 損 d 孔 槽 寬 度 M 力 矩 o 應 力17154 石夕品. 口士(1 Page 21 1294673 Schematic description 1 Semiconductor package 10 Substrate 10a Substrate - Surface 10b Substrate second surface 11 Wafer 1 晶片 Wafer outer edge connection position 12 Solder block 13 Solder ball 20 Annular support member 2 (Γ Support member attachment position 30 Heat sink 3 0a Heat sink upper surface 31a Stress relief hole 31b Stress relief hole 31c Stress relief hole 31d Stress relief hole 31e Stress relief hole 32 Heat sink 33 Heat dissipation Sheet flat portion 34 Heat sink support portion 35 accommodating space 41 Adhesive 42 Underfill material 43 Thermal conductive adhesive 44 accommodating space 5 Semiconductor package 50 Substrate 51 Support member 52 Heat sink 52' Heat sink fixing portion 5 2a Heat sink Surface 52b heat sink lower surface 53 resin layer 54 wafer 55 phase change material 56 barrier ring 57 solder bump 61 delamination 62 wafer breakage d hole Slot width M force moment o stress
17154#A.ptd 第22頁17154#A.ptd Page 22
Claims (1)
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| TW092110108A TWI294673B (en) | 2003-04-30 | 2003-04-30 | Semiconductor package with heatsink |
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| TW092110108A TWI294673B (en) | 2003-04-30 | 2003-04-30 | Semiconductor package with heatsink |
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| TWI294673B true TWI294673B (en) | 2008-03-11 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8767409B2 (en) | 2012-02-08 | 2014-07-01 | Universal Scientific Industrial (Shanghai) Co., Ltd. | Stacked substrate structure |
| TWI455664B (en) * | 2012-10-18 | 2014-10-01 | Zhen Ding Technology Co Ltd | Connecting substrate and package on package structure |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8575746B2 (en) | 2006-07-20 | 2013-11-05 | Samsung Electronics Co., Ltd. | Chip on flexible printed circuit type semiconductor package |
| TWI550804B (en) * | 2015-05-19 | 2016-09-21 | 力成科技股份有限公司 | Chip package structuer |
| TWI771610B (en) * | 2019-09-02 | 2022-07-21 | 矽品精密工業股份有限公司 | Electronic package, carrier structure and manufacturing method thereof |
| CN112530885A (en) * | 2019-09-18 | 2021-03-19 | 江苏长电科技股份有限公司 | Chip packaging structure and packaging method |
| CN111755340A (en) * | 2020-06-30 | 2020-10-09 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method and semiconductor packaging structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8767409B2 (en) | 2012-02-08 | 2014-07-01 | Universal Scientific Industrial (Shanghai) Co., Ltd. | Stacked substrate structure |
| TWI455664B (en) * | 2012-10-18 | 2014-10-01 | Zhen Ding Technology Co Ltd | Connecting substrate and package on package structure |
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| TW200423348A (en) | 2004-11-01 |
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