TW486750B - Methods for forming ultrashallow junctions in semiconductor wafers using low energy nitrogen implantation - Google Patents

Methods for forming ultrashallow junctions in semiconductor wafers using low energy nitrogen implantation Download PDF

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TW486750B
TW486750B TW090108750A TW90108750A TW486750B TW 486750 B TW486750 B TW 486750B TW 090108750 A TW090108750 A TW 090108750A TW 90108750 A TW90108750 A TW 90108750A TW 486750 B TW486750 B TW 486750B
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implanting
nitrogen
boron
energy
semiconductor wafer
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Sandeep Mehta
Naushad Kizhakevariam
Ukyo Jeong
Jinning Liu
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Varian Semiconductor Equipment
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

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Abstract

A method for forming a shallow junction in a semiconductor wafer includes the steps of implanting a dopant material, such as boron, into the semiconductor wafer for forming a shallow junction, implanting nitrogen into the semiconductor wafer at an energy less than 10 keV, and activating the dopant material by thermal processing of the semiconductor wafer at a selected temperature for a selected time to form the shallow junction. The energy of the nitrogen is selected such that the implanted depth of the nitrogen is approximately equal to or less than the implanted depth of the dopant material. The nitrogen dose is preferably greater than about 2.5E14/cm<SP>2</SP>. The step of implanting nitrogen may be performed before or after the step of implanting the dopant material.

Description

486750 A7 B7 五、發明說明（/ ) 發明之領域 (請先閱讀背面之注意事項再填寫本頁) 本發明關於用以在半導體晶圓內以離子植入法形成超 淺接面之方法，特別關於以使用低能量而將氮及摻雜材料 植入半導體晶圓以形成超淺接面之方法。 ； 發明背景 離子植入係一標準技術以導引傳導率變化之摻雜材料 進入半導體晶圓。在傳統離子植入系統中，理想之摻雜材 料在一離子源中離子化，離子被加速以形成規定能量之離 子束’且離子束被導入晶圓之表面。離子束中之高能離子 貫穿半導體材料之本體，並嵌入半導體材料之晶格中。於 離子植入後’該半導體晶圓係被退火，以活化該摻雜材料 。退火涉及加溫半導體晶圓至規定之溫度及時閬。 半導體工業中一知名趨勢，係爲較小、較快速之裝置 。特別是，在半導體裝置中之橫向尺寸及特性深度正降低 之中。現行技術之半導體裝置需要接面深度少於1000埃， 甚至需要接面深度在200埃之等級或更少。 經濟部智慧財產局員工消費合作社印製 摻雜材料之植入深度由植入半導體晶圓之離子之能量 決定。以低植入能量可獲得淺接面。但用以啓動植入摻雜 劑材料之退火程序，造成摻雜材料自半導體晶圓區之擴散 。此一擴散之結果，接面之深度因退火而增加。爲反制此 一由退火引起之接面增加，植入能量可降低，俾理想接面 深度在退火之後可以獲得。此方法可提供滿意結果，但超 淺接面除外。在退火期間造成之摻雜材料之擴散，可以降 低植入能量可獲得接面深度之限度可達成。 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 一 486750 A7 B7 五、發明說明（上） (請先閱讀背面之注意事齋再填寫本頁) 可利用迅速熱處理以使退火期間引起之擴散最小。但 大幅改變退火程序，如降低退火溫度，將降低啓動之摻雜 劑之量，並影響半導體裝置之作業特性。曾有許多努力選 擇熱處理參數，其可達到摻雜劑材料之活化，而能限制摻 雜材料之擴散。 ' 降低植&gt;入能量及修改熱處理參數之策略，在製造業中 帶來嚴重限制。當離子植入器之植入能量降低時，離子束 電流劇烈降低，因而限制每一機器之晶圓輸出。此外，以 低能量離子源及低效率作業，此舉可導致增加之維護需求 及降低機器可用率。對於大多數次-250毫微米頻道長度裝 置而言，熱處理係以迅速熱退火器完成。對於長度爲130 毫微米及更少之通道長度而言，建議利用尖峰退火程序， 其中，以快速上升及下降率，晶圓之最後溫度之時間係幾 乎爲零。但由於難以控制退火程序之溫度，尖峰退火處理 可導致晶源摻雜均勻性及重複性之退化。 經濟部智慧財產局員工消費合作社印製 二基本機構限制了以離子植入及熱處理方法形成超淺 接面。首先，在活化期間，摻雜材料如硼之擴散可由數機 構發生。包括硼之固有擴散及機構引起之瞬時增加之擴散 (TED)。此增加之擴散係由於植入或熱處理期間引進之空 隙點缺陷之擴散機構所引起。其次，高劑量之硼需要最佳 之電特性。多利用lE14-3E15/cm2之植入硼劑量。以此高 劑量之硼，固有之擴散加上硼增加之擴散，限制了接面之 淺度。 對申請人而言，無習知技藝曾提供滿意之製造超淺接 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 486750 A7 B7 五、發明說明（）） (請先閱讀背面之注意事項再填寫本頁) 面之方法，特別是，所需之接面深度無法由降低離子能量 而獲得。準此，需要一改進之方法以製造半導體中之超淺 接面。 發明槪要 根據本發明之一個特性，提供一方法以形成一半導體 晶圓中之一淺接面。此方法包含以下步驟：植入硼進入半 導體晶圓中以形成一淺接面，以小於lOKeV之能量植入氮 於半導體晶圓中，由半導體晶圓之熱處理，以選擇之溫度 與選擇之時間，將硼活化。氮之能量加以選擇，俾植入氮 之深度約等於或小於植入硼之深度。 --線· 硼典型以小於或等於IKeV之能量植入，氮則以能量 5KeV或以下植入。氮植入劑量較佳爲大於2.5E14/cm2。在 第一例中，砸以IKeV能量植入，氮以2.6KeV能量植入。 在第二例中，硼以500eV植入，氮以1.3KeV植入。在第 三例中，硼以250eV植入，氮以0.6KeV或以下植入。硼 植入步驟包含植入B+離子或BF2+離子，氮植入步驟含植入 N2+離子。氮植入步驟可在硼植入前或後植入。 經濟部智慧財產局員工消費合作社印製 根據本發明之另一特性，係提供一形成一淺接面於半 導體晶圓中之方法。此方法包含以下步驟：將摻雜材料植 入半導體晶圓中，以形成一淺接面，以能量小於l〇KeV將 氮植入半導體晶圓中，及以選擇之溫度與選擇之時間，以 半導體晶圓熱處理以活化摻雜材料以形成一淺接面。氮之 能量加以選擇，俾氮植入深度約等於或小於摻雜雜材料植 入深度。 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 486750 五、發明說明（★) 熱處理期間，氮植入可延遲摻雜材料之擴散，因此可 使超淺接面形成。氮植入不會負面影響製造在半導體晶圓 上裝置之電特性。 圖式簡單說明 爲較佳瞭解本發明，參考倂入此間之伴隨圖式，其中： 圖1爲&gt;一簡化之半導體晶圓之部份剖面圖； 圖2A及2B爲流程圖，顯示本發明製造超淺接面於半 導體晶圓中之方法； 圖3爲在每一立方公分原子中之硼濃度圖，作爲不同 方法深度埃之函數，包括本發明之氮方法之實施例； 圖4爲在每一立方公分原子之硼濃度圖，作爲以 1.3KeV及15KeV氮植入深度埃之函數；及 圖5爲每立方公分原子中硼濃度圖，作爲不同氮植入 深度埃之函數。 元件符號說明 10.晶圓 12·離子束 14.植入區 ‘ 經濟部智慧財產局員工消費合作社印製 (請先閱讀背面之注意事看再填寫本頁) --緯· 16.植入光罩 20.雜質區 50·選擇氮能量及劑量 52.植入氮 54·植入摻雜材料 56.晶圓之熱處埋 6 本紙張尺度義巾關家鮮 486750486750 A7 B7 V. Description of the invention (/) Field of invention (please read the precautions on the back before filling this page) The present invention relates to a method for forming an ultra-shallow junction by ion implantation in a semiconductor wafer, especially A method for implanting nitrogen and a doped material into a semiconductor wafer using a low energy to form an ultra shallow junction. BACKGROUND OF THE INVENTION Ion implantation is a standard technique to direct doped materials with varying conductivity into semiconductor wafers. In a conventional ion implantation system, an ideal dopant material is ionized in an ion source, the ions are accelerated to form an ion beam of a prescribed energy, and the ion beam is directed to the surface of the wafer. The high-energy ions in the ion beam penetrate the body of the semiconductor material and are embedded in the crystal lattice of the semiconductor material. After the ion implantation, the semiconductor wafer is annealed to activate the doped material. Annealing involves warming a semiconductor wafer to a specified temperature in a timely manner. A well-known trend in the semiconductor industry is smaller, faster devices. In particular, lateral dimensions and characteristic depths in semiconductor devices are being reduced. Current technology semiconductor devices require a junction depth of less than 1000 Angstroms, and even require a junction depth of 200 Angstroms or less. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The implantation depth of the doped material is determined by the energy of the ions implanted into the semiconductor wafer. Shallow junctions can be obtained with low implantation energy. However, the annealing process used to start implanting the dopant material causes diffusion of the dopant material from the semiconductor wafer region. As a result of this diffusion, the depth of the junction is increased by annealing. In order to counteract this increase in the interface caused by annealing, the implantation energy can be reduced, and the ideal interface depth can be obtained after annealing. This method provides satisfactory results except for super shallow junctions. The diffusion of the doped material caused during the annealing can reduce the implantation energy to achieve the limit of the junction depth that can be achieved. 3 This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) 486750 A7 B7 V. Description of the invention (top) (Please read the notes on the back before filling this page) You can use rapid heat treatment to Minimize the diffusion caused during annealing. However, drastically changing the annealing process, such as lowering the annealing temperature, will reduce the amount of dopants that are activated and affect the operating characteristics of the semiconductor device. There have been many efforts to select heat treatment parameters that can achieve the activation of the dopant material and can limit the diffusion of the dopant material. 'Strategies to reduce planting energy and modify heat treatment parameters have created severe restrictions in the manufacturing industry. When the implantation energy of the ion implanter is reduced, the ion beam current is drastically reduced, thus limiting the wafer output of each machine. In addition, operating with a low-energy ion source and low efficiency can result in increased maintenance requirements and reduced machine availability. For most sub-250 nanometer channel length devices, the heat treatment is done with a rapid thermal anneal. For channel lengths of 130 nanometers and less, it is recommended to use a spike annealing process, where the rapid rise and fall rates and the final temperature of the wafer are almost zero. However, because it is difficult to control the temperature of the annealing process, the spike annealing process can cause the source doping uniformity and repeatability to deteriorate. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Two basic institutions limit the use of ion implantation and heat treatment methods to form super shallow junctions. First, during activation, diffusion of doped materials, such as boron, can occur by several agencies. Includes the inherent diffusion of boron and the transiently increased diffusion (TED) caused by the mechanism. This increased diffusion is caused by the diffusion mechanism of void point defects introduced during implantation or heat treatment. Second, high doses of boron require optimal electrical characteristics. Mostly use the boron implant dose of lE14-3E15 / cm2. With this high dose of boron, the inherent diffusion plus the increased diffusion of boron limits the shallowness of the interface. For applicants, the unskilled craftsmanship has provided satisfactory manufacturing of super shallow junctions. 4 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 486750 A7 B7. 5. Description of the invention ()) (please Please read the precautions on the back before filling this page). In particular, the required depth of the junction cannot be obtained by reducing the ion energy. In order to achieve this, there is a need for an improved method for manufacturing ultra-shallow junctions in semiconductors. Summary of the Invention According to one characteristic of the present invention, a method is provided for forming a shallow junction in a semiconductor wafer. The method includes the following steps: implanting boron into a semiconductor wafer to form a shallow junction, implanting nitrogen into the semiconductor wafer with an energy less than lOKeV, and heat-treating the semiconductor wafer to select a temperature and a selected time To activate boron. The energy of nitrogen is selected, and the depth of implanted nitrogen is approximately equal to or less than the depth of implanted boron. -Wire · Boron is typically implanted with an energy of less than or equal to I KeV, and nitrogen is implanted with an energy of 5 KeV or less. The nitrogen implantation dose is preferably greater than 2.5E14 / cm2. In the first case, IKeV was implanted and nitrogen was implanted at 2.6KeV. In the second example, boron was implanted at 500 eV and nitrogen was implanted at 1.3 KeV. In the third example, boron was implanted at 250 eV and nitrogen was implanted at 0.6 KeV or less. The boron implantation step includes implanting B + ions or BF2 + ions, and the nitrogen implantation step includes implanting N2 + ions. The nitrogen implantation step can be performed before or after the boron implantation. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs According to another feature of the present invention, a method for forming a shallow junction in a semiconductor wafer is provided. The method includes the steps of implanting a doped material into a semiconductor wafer to form a shallow junction, implanting nitrogen into the semiconductor wafer with an energy of less than 10 KeV, and selecting a temperature and a selected time to The semiconductor wafer is heat-treated to activate the doped material to form a shallow junction. The energy of nitrogen is selected, and the implantation depth of hafnium nitrogen is about equal to or less than the implantation depth of doped impurity materials. 5 This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 486750 V. Description of the invention (★) During heat treatment, nitrogen implantation can delay the diffusion of doped materials, so that super shallow junctions can be formed . Nitrogen implantation does not adversely affect the electrical characteristics of devices fabricated on semiconductor wafers. BRIEF DESCRIPTION OF THE DRAWINGS To better understand the present invention, refer to the accompanying drawings incorporated herein, where: Figure 1 is a partial cross-sectional view of a simplified semiconductor wafer; Figures 2A and 2B are flowcharts showing the present invention Method for manufacturing ultra shallow junctions in semiconductor wafers; Figure 3 is a graph of boron concentration in each cubic centimeter of atoms as a function of the depth of different methods, including an embodiment of the nitrogen method of the present invention; Figure 4 is in The boron concentration map of each cubic centimeter atom as a function of the depth of implantation with 1.3KeV and 15KeV nitrogen; and Figure 5 is the boron concentration map per cubic centimeter as a function of different nitrogen implantation depth. Description of component symbols 10. Wafer 12 · Ion beam 14. Implantation area 'Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page)-Weft 16. Implantation light Cover 20. Impurity area 50. Select nitrogen energy and dose 52. Implant nitrogen 54. Implant dopant material 56. Buried in the heat of the wafer 6 Paper-size prosthesis Guan Jiaxian 486750

五、發明說明（上） 詳細說明 圖1顯示一高度簡化半導體晶圓之部份剖面圖。一摻 雜材料之一離子束12導向晶圓1〇，產生一植入區14。植 入區14之邊界由植入光罩16限定。晶圓以快速熱處理器 加以退火，以活化摻雜材料。退火程序造成摻雜材料之擴 散至雜質區&gt; 20，其大於植入區14。雜質區20之特徵爲接 面深度Xj &quot;其爲雜質區20之深度，與晶圓表面1〇正交。 退火產生之接面深度增加，構成一可達成之接面深度Xj之 下限。 吾人發現，與習知技藝方法利用低能量氮植入’及以 摻雜材料植入及延遲退火期間之擴散相較，接面深度^可 以降低。在一例中，氮可在低能量硼植入之煎植入。或者 ，氮可在低能量硼植入後植入。氮能量及劑量須根據硼能 量及劑量加以選擇。典型爲，以N2+離子型式植入，植入 能量在少l〇KeV及大於2.5E14/cm2之劑量。（符號 2.5E14/cm2代表每立方公分原子2.5xl014之植入劑量）。氮 能量須加以選擇，俾氮植入深度約等於或小於硼植入深度 。氮及硼植入後，利用選擇使硼擴散最小之處理參數，以 半導體晶圓之熱處理將硼活化。氮植入方法可利用其他摻 雜材料，如砷及磷。 &lt; 圖2A爲一流程圖說明本發明氮處理之一例。步驟50 ，氮植入之劑量及能量，根據摻雜材料植入之劑量及能量 加以選擇。通常，氮能量之選擇俾使氮之植入深度等於或 小於摻雜材料之植入深度。典型利用小於lOKeV之氮能量 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) -¾ 訂---------線 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 486750 A7 _ _____B7_ 五、發明說明（t ) 。特殊舉例如下。氮劑量爲大於2.5E14/cm2。通常，氮劑 量隨摻雜材料之增加而增加。在步驟52，以選擇之能量及 劑量將氮植入半導體晶圓中。步驟54中，摻雜材料如硼植 入半導體晶圓中。可利用單一植入光罩供氮及摻雜材料之 植入。此方法可用於製造P-型及N-型MOS裝置之源極/汲 極製造中。步驟56中，摻雜材料由選擇之溫度與時間，以 半導體晶圓之熱處理加以活化以形成超淺接面。熱處理典 型包括以900度C-1050度C將半導體晶圓退火0.1至1〇 秒，但不限於此範圍。應了解，任何本發明範疇內適當之 熱處理參數均可利用。 圖2B爲一流程圖說明本發明氮處理之第二例。圖2B 之方法與圖2A相同，但氮植入步驟52及摻雜材料植入步 驟54在處理步驟中反轉。因此，氮植入在圖2B中之摻雜 材料植入之後。V. Description of the invention (above) Detailed description FIG. 1 shows a partial cross-sectional view of a highly simplified semiconductor wafer. An ion beam 12 of a dopant material is directed to the wafer 10, creating an implantation region 14. The border of the implantation area 14 is defined by the implantation mask 16. The wafer is annealed with a rapid thermal processor to activate the doped material. The annealing process causes diffusion of the doped material to the impurity region &gt; 20, which is larger than the implanted region 14. The impurity region 20 is characterized by the interface depth Xj &quot; which is the depth of the impurity region 20 and is orthogonal to the wafer surface 10. The junction depth generated by annealing increases, forming a lower limit of the achievable junction depth Xj. We have found that the junction depth ^ can be reduced compared with the conventional techniques using low energy nitrogen implantation 'and the diffusion during implantation with doped materials and delayed annealing. In one example, nitrogen can be implanted in a low-energy boron implant. Alternatively, nitrogen can be implanted after low-energy boron implantation. The nitrogen energy and dose must be selected based on the boron energy and dose. Typically, it is implanted in an N2 + ion type with an implantation energy of less than 10 KeV and a dose greater than 2.5E14 / cm2. (The symbol 2.5E14 / cm2 represents the implantation dose of 2.5xl014 per cubic centimeter atom). Nitrogen energy must be selected, and the nitrogen implantation depth is approximately equal to or less than the boron implantation depth. After the implantation of nitrogen and boron, the boron is activated by heat treatment of the semiconductor wafer by using processing parameters selected to minimize the diffusion of boron. Nitrogen implantation methods can utilize other doping materials such as arsenic and phosphorus. &lt; FIG. 2A is a flowchart illustrating an example of the nitrogen treatment of the present invention. In step 50, the dose and energy of the nitrogen implantation are selected according to the dose and energy of the doped material implantation. In general, the choice of nitrogen energy is such that the implantation depth of nitrogen is equal to or less than the implantation depth of the doped material. Typical use of nitrogen energy less than lOKeV 7 This paper size applies to Chinese National Standard (CNS) A4 specifications (210 X 297 mm) (Please read the precautions on the back before filling out this page) -¾ Order ------- -Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed 486750 A7 _ _____B7_ V. Description of the invention (t). Specific examples are as follows. The nitrogen dose was greater than 2.5E14 / cm2. Generally, the amount of nitrogen agent increases as the doping material increases. In step 52, nitrogen is implanted into the semiconductor wafer at the selected energy and dose. In step 54, a doped material such as boron is implanted into the semiconductor wafer. A single implant mask can be used for implantation of nitrogen and doped materials. This method can be used in manufacturing source / drain of P-type and N-type MOS devices. In step 56, the doped material is activated by a selected temperature and time by heat treatment of the semiconductor wafer to form an ultra shallow junction. Typical heat treatments include annealing semiconductor wafers at 900 ° C to 1050 ° C for 0.1 to 10 seconds, but are not limited to this range. It should be understood that any suitable heat treatment parameters within the scope of the present invention can be utilized. FIG. 2B is a flowchart illustrating a second example of the nitrogen treatment of the present invention. The method of Fig. 2B is the same as that of Fig. 2A, but the nitrogen implantation step 52 and the doped material implantation step 54 are reversed in the processing step. Therefore, nitrogen is implanted after implantation of the doped material in FIG. 2B.

本發明之氮處理之優點如圖3之硼摻雜輪廓所說明。 如圖3之摻雜輪廓，係由二次離子質譜儀(SIMS)獲得。圖 3中’每立方公分原子之硼濃度以自晶圓表面以埃爲深度 函數所繪。此時，矽晶圓係以硼在能量500KeV及劑量 1E15/Cm2植入。接面深度Xj此例中自晶圓表面限定，該 處之硼濃度降至低於4E18/cm2。圖3中，曲線70代表一* 晶體矽晶圓，其以硼植入有如上述，及以溫度1〇50度C 作尖峰退火10秒；曲線72代表晶矽晶圓，其以硼植入如 上述’在溫度1050度下作尖峰退火〇至1秒&lt;;曲線74代 表銦預非晶化矽晶圓，其以上述之硼植入並以105〇度C 8 不，A技又過用中國國家標準（CNS)A4規格（21〇 x 297公釐） (請先閱讀背面之注意事療再填寫本頁) 訂·· •線· 486750 A7 B7 五、發明說明（q ^ (請先閱讀背面之注意事辱再填寫本頁) 溫度尖峰退火0至1秒。氮未植入以曲線70,72及74代表 之晶圓中。曲線76代表晶矽晶圓，其中之氮在硼植入前植 入。特別是，N+氮離子以L3KeV能量，劑量lE15/cm2植 入。曲線76代表之晶圓在溫度1050度C下尖峰退火〇至 1秒，其中之退火時間係自快速熱處理系統之溫度輪廓所 建立。 &gt; 如圖3所示，氮植入由曲線76代表之晶圓，與其他方 法比較，有一降低之接面深度。利用上述之接面深度定義 ，以氮處理獲得之接面深度，如曲線76所代表爲246埃， 與無氮植入以相同退火條件比較，如曲線72所代表爲402 埃。 經濟部智慧財產局員工消費合作社印製 爲達成本發明氮植入方法之優點，氮植入之能量及質 量加以選擇其與硼或其他摻雜材料之能量與劑量有關。爲 達此目地，氮植入條件已供數種硼植入能量發展而出。氮 植入能量需加以選擇，俾氮及硼植入砂之深度相同。通常 ，N2+氮離子之植入能量爲約5KeV或更低。應瞭解N+氮離 子可以一半之植入能量被植入，並獲得相同之植入深度。 同理，BF2+離子可被增加之植入能量植入以獲得相同之硼 植入深度。 高於lOKeV之氮植入能量時，氮離子植入期間引進之 缺失，可造成硼之瞬間增加之擴散，及產生較深之接面。 在硼摻雜輪廓之效應如圖4說明。圖4中每立方公分原子 中砸濃度以自晶圓表面之深度埃爲函數繪出。此情況下， 石夕晶圓以硼在能量500eV及劑量lE15/cm2植入。此摻雜輪 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 486750 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明u ) 廓係由SIMS所獲得。曲線80代表以N2+氮離子在能量 1.3KeV植入之晶圓。曲線82代表以N2+氮離子在能量 15KeV之下植入之晶圓。此情況下，氮劑量爲lE15/cm2。 此等晶圓在溫度1050度C下，尖峰退火0-1秒。曲線82 代表較深之接面深度，及摻雜物之分隔’如摻雜物輪廓有 一個以上之&gt;尖峰所表示者。晶圓之傳輸電子顯微鏡(TEM) 分析顯示，在較高之氮植入能量時，發現形成數個延伸之 缺點。對比之下，在低氮植入能量時，晶圓則無延伸缺點 。出現延伸之缺點可產生在晶圓上構成之裝置，具有不良 之電效應。 ， 以氮植入能量有效形成淺接面之例已經建立。在以下 每一例中，B+硼離子及N2+氮離子被植入。在500eV硼植 入時，氮植入能量在1.3KeV或以下；在250eV硼植入時 ，氮植入能量爲〇.6KeV或以下；在1KeV硼植入時，氮植 入能量爲2.6KeV或以下。較高氮植入能量在需要較深接 面時可以使用。 除能量外’氮劑量必須選擇。氮劑量在硼植入輪廓之 影響如圖5說明。每立方公分原子硼濃度以自不同氮植入 劑量之晶圓表面’以埃爲深度之函數繪出。摻雜劑輪廓以 SIMS獲得。此例中，半導體晶圓以硼在能量5〇〇ev，劑量 lEB/cm2及N/氮離子以l 3KeV能量植入。曲線9〇代表 無氮植入之硼輪廓；曲線92代表砸輪廓與氮劑量 5E13/cm2(曲線90及92在圖5中重疊）；曲線94代表以氮 劑量2.5El4/cm2之硼輪廓；曲線96代表以氮劑量 10 本紙張尺度適用中國國家標準（CMS)A4 ~—-：---- (請先閱讀背面之注意事香再填寫本頁)The advantages of the nitrogen treatment of the present invention are illustrated by the boron doped profile of FIG. The doping profile shown in Figure 3 was obtained by a secondary ion mass spectrometer (SIMS). In Fig. 3, the boron concentration per cubic centimeter atom is plotted as a function of depth from the wafer surface in angstroms. At this time, the silicon wafer was implanted with boron at an energy of 500 KeV and a dose of 1E15 / Cm2. The junction depth Xj is limited from the wafer surface in this example, and the boron concentration at this point has dropped below 4E18 / cm2. In FIG. 3, curve 70 represents a * crystalline silicon wafer, which is implanted with boron as described above, and spiked at a temperature of 1050 ° C for 10 seconds; curve 72 represents a crystalline silicon wafer, which is implanted with boron such as The above 'spike annealing at a temperature of 1050 degrees 0 to 1 second &lt; curve 74 represents an indium pre-amorphous silicon wafer, which was implanted with boron as described above and at 1050 degrees C 8 No, A technology was used again China National Standard (CNS) A4 specification (21 × 297 mm) (Please read the precautions on the back before filling out this page) Order ·· • Line · 486750 A7 B7 V. Description of the invention (q ^ (Please read first Note on the back, please fill in this page again) Temperature spike annealing 0 to 1 second. Nitrogen is not implanted in the wafers represented by curves 70, 72 and 74. Curve 76 represents crystalline silicon wafers, where nitrogen is implanted in boron Front implantation. In particular, N + nitrogen ions are implanted with L3KeV energy and a dose of 1E15 / cm2. The wafer represented by curve 76 is annealed at a temperature of 1050 degrees C for 0 to 1 second. The annealing time is from the rapid heat treatment system. The temperature profile is established. &Gt; As shown in Fig. 3, the nitrogen implanted wafer represented by curve 76 has a decrease compared with other methods. Depth of junction. Using the above definition of junction depth, the junction depth obtained by nitrogen treatment, as represented by curve 76, is 246 angstroms, and compared with nitrogen-free implantation under the same annealing conditions, as represented by curve 72, 402 angstroms. The consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs has printed the advantages of inventing the nitrogen implantation method to achieve the cost. The energy and quality of nitrogen implantation is selected to be related to the energy and dose of boron or other doped materials. Nitrogen implantation conditions have been developed for several boron implantation energies. Nitrogen implantation energies need to be selected. The depth of nitrogen and boron implantation sand is the same. Generally, the implantation energies of N2 + nitrogen ions are about 5KeV or lower. It should be understood that N + nitrogen ions can be implanted with half of the implantation energy and obtain the same implantation depth. Similarly, BF2 + ions can be implanted with increased implantation energy to obtain the same boron implantation depth. Higher than lOKeV When nitrogen is implanted with energy, the loss introduced during nitrogen ion implantation can cause an instantaneous increase in the diffusion of boron and create a deeper interface. The effect of the boron doping profile is illustrated in Figure 4. Each cubic in Figure 4 Cm The particle concentration is plotted as a function of the depth Angstrom from the wafer surface. In this case, the Shi Xi wafer is implanted with boron at an energy of 500 eV and a dose of lE15 / cm2. This doping wheel 9 This paper size is applicable to Chinese national standards (CNS) A4 specification (210 X 297 mm) 486750 A7 B7 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention u) The profile was obtained by SIMS. Curve 80 represents a wafer implanted with N2 + nitrogen ions at an energy of 1.3 KeV. Curve 82 represents a wafer implanted with N2 + nitrogen ions at an energy of 15 KeV. In this case, the nitrogen dose was 1E15 / cm2. These wafers are annealed at a peak temperature of 1050 degrees C for 0-1 seconds. The curve 82 represents the deeper junction depth and the separation of the dopants, as indicated by the dopant profile having more than one &gt; spike. Transmission electron microscopy (TEM) analysis of the wafers revealed the disadvantage of forming several extensions at higher nitrogen implantation energies. In contrast, at low nitrogen implantation energies, the wafer has no extension disadvantages. The shortcomings of extension can result in devices constructed on wafers, which have poor electrical effects. An example of effective formation of shallow junctions with nitrogen implantation energy has been established. In each of the following examples, B + boron ions and N2 + nitrogen ions were implanted. At 500eV boron implantation, the nitrogen implantation energy is 1.3KeV or below; at 250eV boron implantation, the nitrogen implantation energy is 0.6KeV or below; at 1KeV boron implantation, the nitrogen implantation energy is 2.6KeV or the following. Higher nitrogen implant energies can be used when deeper interfaces are required. In addition to energy, the nitrogen dose must be selected. The effect of nitrogen dose on the profile of boron implantation is illustrated in Figure 5. The boron concentration per cubic centimeter atom is plotted as a function of the depth of Angstroms from the wafer surface at different nitrogen implantation doses. The dopant profile was obtained in SIMS. In this example, the semiconductor wafer was implanted with boron at an energy of 500 ev, a dose of 1 EB / cm 2 and N / nitrogen ions at an energy of 13 KeV. Curve 90 represents the boron profile of nitrogen-free implantation; curve 92 represents the scoring profile and nitrogen dose 5E13 / cm2 (curves 90 and 92 overlap in Figure 5); curve 94 represents the boron profile with nitrogen dose 2.5El4 / cm2; curve 96 stands for nitrogen dosage of 10 This paper size is applicable to Chinese National Standard (CMS) A4 ~ —-: ---- (Please read the notes on the back before filling this page)

486750 A7 B7____ 五、發明說明（？） lE15/cm2之硼輪廓。每—情況下，晶圓在溫度105〇度C 之下，尖峰退火〇至1秒。圖5中，接面深度之降低在氮 摻雜劑約2.5E14/cm2時所觀察到。因此’此位準或更大之 氮摻雜劑爲較佳。通常，降低氮植入劑量至能獲得理想接 面深度所需之位準，最爲理想，俾可輸出中降低氮植入劑 之負面影響爲最小。 以上已檢討氮植入劑方法之變化。此等變化包括（1)在 氮及硼植入劑之間引進一退火步驟，及(2)在硼植入之前及 以後，多次氮植入。 本發明之較佳實施例已說明及顯示如上，對熟悉此技 藝人士而言，不同改變及修改在不悖離本發明限定於申請 專利範圍之範疇時，均屬可行。 (請先閱讀背面之注意事項再填寫本頁) 訂· · --線· 經濟部智慧財產局員工消費合作社印製 11 297公釐） 本紙張尺度適用中國國家標準（CNS)A4規格（210486750 A7 B7____ 5. Description of the invention (?) Boron profile of lE15 / cm2. In each case, the wafer is annealed at a temperature of 1050 degrees C for 0 to 1 second. In Fig. 5, the decrease in junction depth is observed at a nitrogen dopant of about 2.5E14 / cm2. Therefore, a nitrogen dopant at this level or more is preferred. In general, reducing the nitrogen implantation dose to the level required to achieve the desired interface depth is the most ideal, and the negative impact of reducing nitrogen implantation in the output can be minimized. The changes in the nitrogen implant method have been reviewed above. These changes include (1) the introduction of an annealing step between the nitrogen and boron implants, and (2) multiple nitrogen implants before and after the boron implant. The preferred embodiments of the present invention have been described and shown above. For those skilled in the art, different changes and modifications are feasible without departing from the scope of the present invention which is limited to the scope of patent application. (Please read the precautions on the back before filling out this page) Order · ·-Line · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 11 297 mm) This paper size applies the Chinese National Standard (CNS) A4 specification (210

Claims (1)

486750 A8 B8 C8 D8 f、申請專利範圍 1·一種用以形成半導體晶圓中之一淺接面之方法，該 方法包含下列步驟： 植入硼於半導體晶圓中，以形成一淺接面； 以小於lOKeV之能量植入氮於半導體晶圓中，其中， 氮之能量係被選擇，俾氮之植入深度約等於或小於硼之植 入深度；及， 於選擇之溫度之下，以半導體晶圓之熱處理活化硼一 段選擇之時間，以形成該淺接面。 2·如申請專利範圍第1項之方法，其中植入硼步驟包 含以IKeV植入硼，其中植入氮之步驟包含以低於2.6KeV 植入氮。 3·如申請專利範圍第1項之方法，其中俥入硼之步驟 包含以5〇〇eV植入硼，其中植入氮之步驟包含以i.3KeV 植入氮。 4·如申請專利範圍第1項之方法，其中植入硼之步驟 包含也250eV植入硼，其中植入氮之步驟包含以或低於 0.6KeV植入氮。 5·如申請專利範圍第1項之方法，其中植入硼步驟包 含以或低於IKeV之能量植入硼，其中植入氮之步驟含以 等於或低於5KeV之能量植入氮。 6·如申請專利範圍第1項之方法，其中植入硼步驟包 含植入B +離子。 7·如申請專利範圍第1項之方法，其中植入硼步驟包 含植入BF2+離子。 1 (請先閱讀背面之注意事項再填寫本頁) -------訂—--------*^1 . 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 486750 A8 驾 D8 六、申請專利範圍 8. 如申請專利範圍第1項之方法，其中植入氮步驟包 含植入N2+離子。 (請先閲讀背面之注意事項再塡寫本頁) 9. 如申請專利範圍第1項之方法，其中植入氮步驟在 植入硼步驟之前實施。 10. 如申請專利範圍第1項之方法，其中植入氮之步驟 在植入硼步驟之後實施。 11. 如申請專利範圍第1項之方法，其中活化硼之步驟 包含，以約900度C至1050度C之溫度退火半導體晶圓 約0.1至10秒。 12. 如申請專利範圍第1項之方法，其中植入氮步驟包 含，以在或大於2.5E14/cm之劑量植入氮。 13. 如申請專利範圍第1項方法，其中植入硼之步驟包 含，爲形成用於MOS裝置之源極/汲極延伸。 14. 一種用以於半導體晶圓中形成淺接面之方法，包含 以下步驟： 植入一摻雜材料於半導體晶圓中，以形成一淺接面； 以小於l〇KeV之能量植入氮於半導體晶圓中，其中， 氮之能量係被選擇，俾氮之植入深度與摻雜材料之植入深 度大約相等或爲少；及 於選擇之溫度之下，以半導體晶圓之熱處理活化摻雜 材料一段選擇之時間，以形成該淺接面。 15. 如申請專利範圍第14項之方法，其中植入氮步驟 在植入摻雜材料步驟前實施。 16. 如申請專利範圍第14項之方法，其中植入氮步驟 在植入摻雜材料後實施。 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 經濟部智慧財產局員工消費合作社印製 486750 A8 cBs8 D8 _ 六、申請專利範圍 17. 如申請專利範圍第14項之方法，其中植入氮步驟 包含，以大於2.5E14/cm2之劑量植入氮。 18. 如申請專利範圍第14項之方法，其中植入氮步驟 包含，以等於或低於5KeV之能量植入氮。 19. 一種用以在半導體晶圓中形成一淺接面之方法，包 含下列步驟： 植入硼於半導體晶圓中，以形成一淺接面； 選擇小於lOKeV之氮能量，以產生半導體晶圓中一植 入深度，其約等於或小於硼之植入深度； , 以選擇之能量及大於約2.5E14/cm2之劑量植入氮於半 導體晶圓中；及 於選擇之溫度下，以半導體晶圓之熱處理活化硼一段 選擇之時間，以形成該淺接面。 20·如申請專利範圍第19項之方法，其中植入氮步驟 在植入硼步驟之前實施。 21. 如申請專利範圍第19項之方法，其中植入氮步驟 在植入硼步驟之後實施。 22. 如申請專利範圍第19項之方法，其中植入硼步驟 包含以或低於IKeV能量植入硼，其中植入氮步驟包含以 或低於5KeV能量植入氮。 23·如申請專利範圍第19項之方法，其中植入硼步驟 包含植入B+離子。 24·如申請專利範圍第19項之範圍，其中植入氮步驟 包括植入N2+離子。 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ' (請先閱讀背面之注意事項再填寫本頁) 赛 -------訂·--------I 486750 A8 B8 C8 D8 、申請專利範圍 25.如申請專利範圍第19項之方法，其中活化硼步驟 包括，以約900度C至1050度C溫度退火半導體晶圓約 0.1至10秒。 (請先閱讀背面之注意事項再填寫本頁) 0. 訂---------線！ 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）486750 A8 B8 C8 D8 f. Patent application scope 1. A method for forming a shallow junction in a semiconductor wafer, the method includes the following steps: implanting boron in the semiconductor wafer to form a shallow junction; Nitrogen is implanted into the semiconductor wafer with an energy of less than lOKeV, wherein the energy of nitrogen is selected, and the implantation depth of hafnium nitrogen is approximately equal to or less than the implantation depth of boron; and, at the selected temperature, semiconductors are used. The heat treatment of the wafer activates the boron for a selected period of time to form the shallow junction. 2. The method of claim 1 wherein the step of implanting boron includes implanting boron with IKeV, and the step of implanting nitrogen includes implanting nitrogen at a rate of less than 2.6 KeV. 3. The method of claim 1 in which the step of implanting boron includes implanting boron at 500 eV, and the step of implanting nitrogen includes implanting nitrogen at i.3KeV. 4. The method according to item 1 of the patent application range, wherein the step of implanting boron comprises 250 eV of implanting boron, and wherein the step of implanting nitrogen comprises implanting nitrogen at or below 0.6 KeV. 5. The method according to item 1 of the patent application range, wherein the step of implanting boron includes implanting boron with an energy of IKeV or lower, and wherein the step of implanting nitrogen includes implanting nitrogen with an energy equal to or lower than 5 KeV. 6. The method of claim 1 in which the boron implantation step includes implanting B + ions. 7. The method of claim 1 in which the boron implantation step includes implanting BF2 + ions. 1 (Please read the notes on the back before filling out this page) ------- Order --------- * ^ 1 National Standard (CNS) A4 Specification (210 X 297 mm) 486750 A8 Driving D8 VI. Patent Application Range 8. The method of applying for the first item of patent scope, wherein the step of implanting nitrogen includes implanting N2 + ions. (Please read the precautions on the reverse side before writing this page) 9. For the method in the first scope of the patent application, the nitrogen implantation step is performed before the boron implantation step. 10. The method of claim 1 in which the step of implanting nitrogen is performed after the step of implanting boron. 11. The method of claim 1, wherein the step of activating boron comprises annealing the semiconductor wafer at a temperature of about 900 ° C to 1050 ° C for about 0.1 to 10 seconds. 12. The method of claim 1 wherein the step of implanting nitrogen comprises implanting nitrogen at a dose of 2.5E14 / cm or more. 13. The method of claim 1, wherein the step of implanting boron includes forming a source / drain extension for a MOS device. 14. A method for forming a shallow junction in a semiconductor wafer, comprising the following steps: implanting a doped material into the semiconductor wafer to form a shallow junction; implanting nitrogen with an energy of less than 10 KeV In semiconductor wafers, the energy of nitrogen is selected, and the implantation depth of hafnium nitrogen is approximately equal to or less than the implantation depth of doped materials; and the semiconductor wafer is activated by heat treatment at a selected temperature Doping the material for a selected period of time to form the shallow junction. 15. The method of claim 14 wherein the step of implanting nitrogen is performed before the step of implanting the doping material. 16. The method of claim 14 wherein the step of implanting nitrogen is performed after implanting the doping material. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs 486750 A8 cBs8 D8 The step of implanting nitrogen includes implanting nitrogen at a dose greater than 2.5E14 / cm2. 18. The method of claim 14 wherein the step of implanting nitrogen comprises implanting nitrogen with an energy equal to or lower than 5 KeV. 19. A method for forming a shallow junction in a semiconductor wafer, comprising the following steps: implanting boron in the semiconductor wafer to form a shallow junction; selecting a nitrogen energy less than lOKeV to generate a semiconductor wafer S1 implant depth, which is approximately equal to or less than the implant depth of boron; implant nitrogen into the semiconductor wafer at a selected energy and a dose greater than approximately 2.5E14 / cm2; and at a selected temperature, use semiconductor crystals A round heat treatment activates the boron for a selected period of time to form the shallow junction. 20. The method of claim 19, wherein the step of implanting nitrogen is performed before the step of implanting boron. 21. The method of claim 19, wherein the step of implanting nitrogen is performed after the step of implanting boron. 22. The method of claim 19, wherein the step of implanting boron comprises implanting boron at or below IKeV energy, and wherein the step of implanting nitrogen comprises implanting nitrogen at or below 5 KeV. 23. The method of claim 19, wherein the step of implanting boron comprises implanting B + ions. 24. The scope of claim 19, wherein the step of implanting nitrogen includes implanting N2 + ions. 3 This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) '(Please read the precautions on the back before filling this page) --I 486750 A8 B8 C8 D8, patent application scope 25. The method of item 19 of the patent application scope, wherein the step of activating boron includes annealing the semiconductor wafer at a temperature of about 900 ° C to 1050 ° C for about 0.1 to 10 seconds. (Please read the notes on the back before filling this page) 0. Order --------- line! Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is sized to the Chinese National Standard (CNS) A4 (210 X 297 mm)
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