201240045 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種封裝載板及其製造方法，特別係 有關於一種具有非對稱增層結構之封裝戴板及其製造方 法。 【先前技術】 在積體電路(IC)封裝技術中，覆晶（flip chip, FC)載板 具有提供電子產品晶片與印刷電路板（PCB)間之電性連 接、實體支撐和散熱等功能。習知覆晶栽板製程係將基 板經機械鐵孔、灌孔、影像轉移及絕緣增層製程，重複 雙面增層步驟數次後以抗知綠漆塗佈’再經由錫膏印 刷、迴焊及切割製程’最終形成具有對稱增層結構之習 知覆晶（flip chip, FC)載板。 由於電子產品的球棚陣列間距（BGA pitch)要求日漸 精密，所以覆晶載板的佈線設計也朝向細線寬和細間距 (fine pitch)發展。然而’現今的印刷電路板(pcB)的表面 黏著技術（SMT)製程能力卻無法匹配覆晶載板之佈線設 計要求。故現發展轉接載板（interposer)，藉由重新佈線設 計將覆晶載板之較精密間距透過轉接載板（interposer)轉 換成標準印刷電路板（PCB)球距，以利後續表面黏著製 程。但是，轉接載板（interposer)的使用會產生製程成本上 升、封裝良率下降、封裝成品厚度增加等問題。 在此技術領域中，有需要一種封裝載板，以改善上述 缺點。 4 201240045 .【發明内容】 括一 一實施例係提供一種封裝載板，包 括核心板，其具有一第一表面和相對 =二表面。-第-線路增層結構，設置於上述 其中上述第-線路增層結構包括一絕緣層和一第1’ 線路層。-第二線路增層結構，設於 圖木化 述第二線路增層結構包括-絕緣層和—第:二面土：上 層。複數個第三線路增層結構，設置於 結構上，其中每一個第三線路增声=線路增層 第三圖案化線路層，並巾4 ^ 、纟巴緣層和一 w 共肀母一個上述止上第二 的上述第三圖案化線路層的最小咖增^構 =路:的最小間距，且其中上述第一 ：圖 苐二線路增層結構和每—個上述些第 =構、上述 述絕緣層為相同材質。 '’· s s結構的上 本發明另-實施例係提供 法，包括提供-核心板，其具有—第一封裝载，造方 一表面的一第二声而。八， 弟表面和相對上述第 面上形成-第—線路於上述第一表面和上述第二表 ψ ^ _ ，’曰層〜構和一第二線路増層社 中上μ弟—線路增層結構係包括 、。冓’，、 述絕緣層的—第二線路層。僅於上述第二:::覆蓋上 形成複數個第三線路增 ：線路增層結構上 結構的上述第二線路層。 田木 述第二線路增層 【實施方式】 201240045 做為詳細說明並伴隨著圖式說明之範例， 相同之部分皆使用相同之圖號。且月=田述^相似或 =厚度可擴大，並以簡化或方』:式:者貫 :件之部分將以分別描述說明之，值得注二圖= 繪示或描述之亓杜也α 忖立葱的疋’圖中未 知的形式，另外，特餘領域中具有通常知識者所 定方式，例僅為揭示本發明使用之特 义万式’其並非用以限定本發明。 寸 面円第土 =圖為本發明一實施例之封裝載板500之製程， 板，以㈣r中載板係整合積體電路載板和轉接 間距封裝载板不同側分別符合積體電路晶片細 p1CIi)和印刷電路板的球距a，响需求，使 積體電路晶片和印刷電路板直接接合，可節省製 二产並二少封裝植球的良率損失，且可降低封裝後 側的i述封I載板符合印刷電路板球距之一 面鮮制進行符合積體電路晶片細間距之—側的單 避‘：衣:,％為全面性覆蓋核心板而並未被圖案化，以 、仃早面增層製程時因應力不均造成板面攣 ° 二參:其具有+表* 射 一表面214。接者，可利用機械鑽孔或雷 黎·_ 4物理製程’分別從核心板2〇〇的第—表面或 =二表面2]4移除部分核心板材料，以於核心板· 肀形成貫穿核心板200的導通孔23〇。 6 201240045 接著，可利用塗佈（coating)、化學氣相沈積（CVD)、 例如藏鐘（sputtering)之物理氣相沈積（PVD)等方式，順應性 於核心板200上形成一晶種層（seed layer)(圖未顯示），並覆 蓋第一表面212、第二表面214以及導通孔230的内侧壁。 在本發明一實施例中，晶種層為一薄層，其材質可包括錄、 金、錫、鉛、銅、鋁、銀、鉻、鎢、矽或其組合或上述之 合金。上述晶種層便於藉以利用電鍍方式形成的金屬層在 其上成核與成長。然後，可利用電鍍方式，順應性於晶種 層上形成一電鐘金屬層，並覆蓋第一表面212、第二表面 214以及導通孔230的内側壁。在本發明一實施例中，第 一電鍍金屬層的材質可相同於上述晶種層。之後，形成填 滿導通孔230之灌孔樹脂203。 接著，可利用影像轉移製程，即經由覆蓋光阻、顯影 (developing)、#刻（etching)和去膜（striping)的步驟，移除 部分第一電鍍金屬層及部分晶種層，以於核心板200的第 一表面212和第二表面214上形成圖案化電鍍金屬層220a 和220b，又可視為内層線路層220a和220b。 接著，進行增層製程，分別於核心板200的第一表面 212和第二表面214上形成一第一線路增層結構240a和一 第二線路增層結構240b。在本發明一實施例中，核心板200 的第一表面212和第二表面214上係對稱地設置相同數量 的線路增層結構。第一線路增層結構240a可包括覆蓋内層 線路層220a的一絕緣層242a，形成於絕緣層242a上的圖 案化線路層244a和穿過於絕緣層242a且用以電性連接不 同層之圖案化線路層244a和内層線路層220a的導電盲孔 201240045 246a。而第二線路增層結構240b也可包括覆蓋内層線路層 220b的一絕緣層242b和穿過於絕緣層242b且用以電性連 接不同層之圖案化線路層244b和内層線路層220b的導電 盲孔246b。值得注意的是，於此步驟中，形成於絕緣層242b 上的線路層244b係全面性覆蓋絕緣層242b而並未被圖案 化。 在本發明一實施例中，第一線路增層結構240a和一第 二線路增層結構240b的形成方式可包括利用壓合製程，分 別於核心板200的第一表面212和第二表面214上貼附具 有相同材.質的絕緣層242a和絕緣層242b。之後，可利用 雷射鑽孔(laser drilling)製程，分別於絕緣層242a和絕緣層 242b中形成複數個盲孔，以預留後續形成導電盲孔246a 和246b的位置。接著，利用影像轉移製程，即經由覆蓋光 阻、曝光和顯影（developing)的步驟，於絕緣層242a的表面 上形成圖案化光阻層（圖未顯示），但在此步驟中在絕緣層 242b的表面上並沒有形成圖案化光阻層，再利用電鍍（晶種 層之形成為電鑛之習知技術，故圖未顯示）、化學沉積或無 電解電鍍等方式，分別於未被圖案化光阻層覆蓋的絕緣層 242a和絕緣層242b上同時形成導電盲孔246a和246b、圖 案化線路層244a和全面性覆蓋絕緣層242b表面的線路層 244b。在本發明一實施例中，導電盲孔246a和246b、圖 案化線路層244a和線路層244b的材質可包括鎳、金、錫、 錯、銅、铭、銀、鉻、鎢、^夕或其組合或上述之合金。 在本發明一實施例中，絕緣層242a和絕緣層242b為 相同的材質，例如為環氧樹脂（epoxy resin)、雙馬來亞醯胺 8 201240045 -二氮雜本树墙（bisma]eimide triacine, ΒΤ)、聚亞醯胺 (polyimide)、ABF 膜（ajinomoto buiid-up film) ' 聚苯醚(p〇iy phenylene oxide, i>pE)或聚四氟乙烯（p〇iyietra行u〇rethyiene, PTFE)。 然後’請參考第2圖，進行單面增層製程，僅於第一 線路增層結構24〇a結構上形成複數個第三線路增層結 構’例如第二線路增層結構25〇、26〇和27〇，並使位於最 外層（距核心板2〇〇的距離最遠）的第三線路增層結構270 的圖案化線路層的最小間距ρι #於—積體電路晶片的銲 墊最小間距。在本發明一實施例中，第三線路增層結構的 設置數量亚無限制，且依據客戶設計而定。在本發明一實 施例中’第二線路增層結構2.50、260和270的形成方式係 類似於第-線路增層結構2術和第二線路增層結構㈣匕 的开y成方式’而在進行形成第三線路增層結構25〇、26〇和 270的單面増層製程時，可使用例如聚合乾膜光阻的遮罩 眉^ 28f 面性覆蓋第二線路增層結構24〇b的線路層244b。 ，例^說’第二線路增層結構250的形成方式可包括利用 反5衣知於核心板200的第一線路增層結構240a上貼附 絕緣層252。之你 便’可利用雷射鑽孔(laser drilling)製程， 刀另ϋε緣層252中形成複數個盲孔，以預留後續形成導 電盲孔2 5 6的彳a» —、♦ 位I。接者’利用影像轉移製程，即經由覆 ⑽光阻曝光和顯影（developing)的步驟，於絕緣層252的 表面上$成圖案化光阻層（圖未顯示），再利用電鑛（晶種層 ，形成，電錢之習知技術’故圖未顯示)、化學沉積或無電 解電鑛等方式’於未被圖案化光阻層覆蓋的絕緣層252上 201240045 形成導電盲孔256和圖案化線路層254。之後，再重覆上 述製程，於第三線路增層結構250上依序形成第三線路增 層結構260和270，其中第三線路增層結構260包括覆蓋 第三線路增層結構250的一絕緣層262和穿過於絕緣層262 且用以電性連接不同層之圖案化線路層264和圖案化線路 層254的導電盲孔266，而其中第三線路增層結構270包 括覆蓋第三線路增層結構260的一絕緣層272和穿過於絕 緣層272且用以電性連接不同層之圖案化線路層274和圖 案化線路層264的導電盲孔276。在本發明一實施例中， 線路層244b的厚度T2可等於圖案化線路層254、264和 274的厚度T1。或者，在本發明另一實施例中，線路層244b 的厚度T2可大於圖案化線路層254、264和274的厚度T1， 以使第二線路增層結構240b具有更高的機械強度。值得注 意的是，由於線路層244b係全面性覆蓋絕緣層242b而並 未被圖案化，所以不論線路層244b的厚度T2等於或大於 圖案化線路層254、264和274的厚度T1，皆可避免後續 在進行單面增層製程形成第三線路增層結構250、260和 270時，因應力不均造成板面彎曲的問題。在本發明一實 施例中，第三線路增層結構250、260和270的導電盲孔 256、266和276、圖案化線路層254、264和274的材質可 包括鎳、金、錫、鉛、銅、鋁、銀、鉻、鎢、矽或其組合 或上述之合金，而第三線路增層結構250、260和270的絕 緣層252、262和272可與絕緣層242a和絕緣層242b具有 相同的材質。 值得注意的是，可設計使由内至外的第三線路增層結 201240045 構250、260和270中的圖案化線路層的最小間距和最小線 寬逐漸縮小，以使位於最外層（距核心板200的第一表面 212的距離最遠）的第三線路增層結構270的圖案化線路層 274的最小間距P1等於一積體電路晶片的銲墊最小間距。 另外，值得注意的是，在本發明一實施例中，由於第一線 路增層結構240a和第三線路增層結構250〜270的導電盲孔 和線路層並非藉由導通孔230做為電鍍導通路徑而形 成，所以第一線路增層結構240a和第三線路增層結構 250〜270中至少有一個導電盲孔，例如位於中間位置的導 電盲孔246a、256、266和276，不會與導通孔230電性連 接。 之後’請參考第3圖’在形成符合積體電·路晶片細間 距之一側的單面增層製程（包括第一線路增層結構240a和 第三線路增層結構250、260和270)之後，再形成符合印 刷電路板球距之第二圖案化線路層244c。如第3圖所示， 於第三線路增層結構250、260和270上，全面性形成例如 聚合乾膜光阻或光阻劑的遮罩層280。接著，進行曝光和 顯影（developing)步驟，圖案化如第2圖所示的遮罩層282, 以形成覆蓋部分如第2圖所示之線路層244b的遮罩圖案 282a。然後，進行一蝕刻製程，移除未被遮罩圖案282a覆 蓋的線路層244b。最後，可進行去膜（striping)步驟，去除 遮罩層280和遮罩圖案282a，以形成第4圖所示之圖案化 線路層244c。值得注意的是，核心板200的第二表面214 上方的圖案化線路層244c的最小間距P2係符合印刷電路 板球距，且小於第三線路增層結構270的圖案化線路層274 201240045 的最小間距pi。另外，值得注意的是，在本發明一實施例 中’由於第二線路增層結構240b的導電盲孔和線路層並 非藉由導通孔230做為電鍍導通路徑而形成，所以第二 線路增層結構240b中至少有一個導電盲孔，例如位於中 間位置的導電盲孔246b，不會與導通孔23()電性連接。 然後，請參考第5圖，可利用塗佈、印刷、貼覆、壓 合等方式，分別於第三線路増層結構27〇和第二線路增層 結構240b上形成抗焊絕緣層284a和284b，且可利用雷射 鑽孔（laser drilling)、電漿蝕刻或影像轉移等開環製程，分 別於抗焊絕.緣層284a和284b中選擇性形成複數個開口 286a和286b ’並暴露出部分圖案化線路層274和244c。在 本發明一實施例中，抗焊絕緣層284a和284b可包括例如 綠漆之防焊材料，或可為包括聚亞醯胺(polyimide)、ABF 膜（ajinomoto build-up film)或聚丙稀(polypropylene，PP)之 絕緣材料，其可保護其下的導電盲孔246b、276和圖案化 線路層244c、274不被氧化或彼此短路。另外，穿過抗焊 絕緣層284a和284b的開口 286a和286b可提供後續預銲 金屬凸塊的形成位置。接著，可利用化學沉積及電化學方 式’分別於從開口 286a和286b底面暴露出來的圖案化線 路層274和244c上形成金屬保護層288a和288b。在本發 明一實施例中’金屬保護層288a和288b的材質可包括鎳、 金、錫、鉛、鋁、銀、鉻、鎢、鈀或其組合或上述之合金， 其可增加後續形成之預銲金屬凸塊與圖案化線路層274和 244c的結合力。然後，可選擇性利用化學沉積、鋼板印刷、 微植球製程或電鍍金屬等方式，於符合積體電路晶片細間 12 201240045 距之一側的金屬保護層288a上形成預銲金屬凸塊290，以 提供積體電路晶片接合之用。在本發明一實施例中，預銲 金屬凸塊290的材質可包括鎳、金、錫、叙f、銅、紹、銀、 鉻、鶴、^夕或其組合或上述之合金。經過上述製程之後， 係形成本發明一實施例之封裝載板500。 第6圖為本發明一實施例之封裝載板500與積體電路 晶片300結合構成之封裝結構的示意圖。如第6圖所示， 可利用打線、導線架貼合或覆晶焊接等方式，將一積體電 路晶片300接合至封裝載板500之符合積體電路晶片細 間距之一側的預銲金屬凸塊290。在本發明一實施例中， 積體電路晶片300和抗焊絕緣層284a之間可設置有一底 膠292。接著，可選擇性於封裝載板500之符合印刷電路 板球距之一側的抗焊絕緣層284b上架設具有開環之印刷 模版，其中上述開環的位置大致對準開口 2 8 6b的位置。之 後，將錫膏刮入或擠入印刷模版之開環中，使位於印刷模 版開環内的金屬保護層288b表面和開口 286b均被錫膏覆 蓋。再利用迴銲方式，使金屬保護層288b表面上和開口 286b中的錫膏熔融為一球體，以於開口 286b中形成例如 錫球（solder ball)或銲墊（solder paste)的預銲金屬凸塊 302。在本發明一實施例中，預銲金屬凸塊302和預銲金屬 凸塊290可具有相同的材質。經過上述製程之後，係形成 本發明一實施例之封裝載板500與積體電路晶片300結合 構成之封裝結構。最後可再將上述封裝結構經由電性測 試確保良品，以提供作為直接與印刷電路板結合之封裝 結構。 13 201240045 本發明實施例係提供一種封裝載板及其製造方法。本 發明實施例的封裝載板為具有不對稱增層結構的封裝載 板，其利用單面增層技術’將習知技術的積體電路晶片 載板線路佈線於轉接載板（interP〇ser)上，以達到封裝載板 的一側適合結合積體電路晶片細間距（fine pitch)需求’而 封裝載板的另一侧提供適合結合印刷電路板(7CB)的球 距（ball pitch)需求。由於本發明實施例的封裝載板係將積 體電路晶片（1C)載板及轉接載板（interposer)設計成一主 合型載板，所以可節省封裝植球及良率損失成本。另外’ 本發明實施例的封裝载板，其表面可設計具有預銲金屬凸 塊或打線金手指。因此，其與積體電路晶片封裝後，可 WJ即 利用表面黏著技術（SMT)直接接合於㈣電路板上… 省疊成封裝（P0P)製程及相關材料，並可減少封f後成品 f度1再者，本發明實施例的封裝載板在進行單面增層製 層係全面性形成而並未被圖2板(PCB)的載板側的^ 增層製程時，因應力不均造=，所以可避免在 雖然本發明已以實施例^面彎曲的問題。 j揭路如上，然其並非用以限定 本發明，任何熟習此技藝者 範圍内，當可料許之更動/不脫離本發明之精神和 ^ 動與潤飾，因此本發明之保護 辄圍*視錢之巾請專利範為準。 14 201240045 【圖式簡單說明】 第1〜5圖為本發明一實施例之封裝載板之製程剖面 圖。 第6圖為本發明一實施例之封裝載板與積體電路晶片 結合構成之封裝結構示意圖。 【主要元件符號說明】 200〜核心板， 203〜灌孔樹脂； 212〜第一表面； 214〜第二表面； 220a、220b〜内層線路層； 230〜導通孔； 240a〜第一線路增層結構； 240b〜第二線路增層結構； 242a、242b、252、262、272〜絕緣層； 244a、244c、254、264、274〜圖案化線路層； 244b〜線路層； 246a、246b、256、266、276〜導電盲孔； 250、260、270〜第三線路增層結構； 284a、284b〜抗焊絕緣層； 286a、286b 〜開口， 288a、288b〜金屬保護層； 290、302〜預銲金屬凸塊； 292〜底膠； ]5 201240045 300〜積體電路晶片； 500〜封裝載板 PI、P2〜最小間距 ΊΠ、T2〜厚度。 16201240045 VI. Description of the Invention: [Technical Field] The present invention relates to a package carrier and a method of manufacturing the same, and more particularly to a package panel having an asymmetric buildup structure and a method of manufacturing the same. [Prior Art] In the integrated circuit (IC) packaging technology, a flip chip (FC) carrier has functions of providing electrical connection, physical support, and heat dissipation between an electronic product chip and a printed circuit board (PCB). The conventional flip-chip process system is to pass the mechanical iron hole, the filling hole, the image transfer and the insulation layer-adding process, repeat the double-layer layer-adding step several times and then apply the anti-sense green paint to 'print the paste through the solder paste. The soldering and dicing process 'finally forms a conventional flip chip (FC) carrier with a symmetric build-up structure. Since the ballbar array pitch (BGA pitch) requirements of electronic products are becoming increasingly precise, the layout design of the flip chip carrier is also progressing toward fine line width and fine pitch. However, today's printed circuit board (PCB) surface mount technology (SMT) process capability does not match the wiring design requirements of flip chip. Therefore, the interposer is now developed, and the finer pitch of the flip-chip carrier is converted into a standard printed circuit board (PCB) pitch by the rewiring design to facilitate subsequent surface adhesion. Process. However, the use of interposers can cause problems such as increased process costs, reduced package yield, and increased thickness of packaged finished products. In the art, there is a need for a package carrier to improve the above disadvantages. 4 201240045. SUMMARY OF THE INVENTION [0007] An embodiment provides a package carrier, including a core panel having a first surface and a second surface. - a first-line build-up structure, wherein said first-line build-up structure comprises an insulating layer and a first 'circuit layer. - a second line build-up structure, which is provided in the second line of the build-up structure comprising - an insulating layer and - a: two-faced soil: an upper layer. a plurality of third line build-up structures are disposed on the structure, wherein each of the third lines is increased in sound = the third patterned circuit layer of the line is added, and the towel 4 ^, the 纟 缘 层 layer and a w 肀 肀 一个a minimum spacing of the second third patterned circuit layer of the second layer, and wherein the first: the second circuit of the second circuit layer and the above-mentioned first structure, the above-mentioned insulation The layers are the same material. The invention of the present invention provides a method comprising providing a core panel having a first package carrying a second sound on a surface of the fabric. Eight, the surface of the brother and the first surface formed on the first surface - the first line and the second surface ψ ^ _ , '曰 layer ~ structure and a second line layer The structure includes, .冓', the second circuit layer of the insulating layer. Only a plurality of third line additions are formed on the second::: overlay described above: the second circuit layer of the structure on the line build-up structure. Tian Mu describes the second line layering [Embodiment] 201240045 As a detailed description and accompanying the example of the diagram, the same parts are used for the same parts. And month = Tian Shu ^ similar or = thickness can be expanded, and to simplify or square:: the style: the part of the piece will be described separately, it is worth noting the second picture = depict or describe the 亓 Du also α 忖The present invention is not limited to the scope of the invention. It is intended to be illustrative of the invention.英寸面円土=Fig. The process of the package carrier 500 according to an embodiment of the present invention, the board is matched with the integrated circuit chip on the different sides of the (4) r middle carrier integrated circuit circuit board and the inter-spaced package carrier Fine p1CIi) and the pitch of the printed circuit board a, the demand, the integrated circuit chip and the printed circuit board directly joined, can save the yield loss of the second production and the second package ball, and can reduce the back side of the package i describes that the I carrier board conforms to one side of the printed circuit board ball pitch and is made to meet the fine pitch of the integrated circuit chip - the side of the single avoidance ': clothing: % is a comprehensive cover of the core board and is not patterned, In the early surface layering process, the plate surface is caused by uneven stress. The second parameter: it has a + surface * a surface 214. The mechanical core drilling or the Rayleigh _ 4 physical process can be used to remove part of the core material from the first surface of the core plate 2 or the second surface 2] 4 to form a core plate. The via hole 23 of the core board 200 is turned on. 6 201240045 Next, a seed layer may be formed on the core plate 200 by means of coating, chemical vapor deposition (CVD), physical vapor deposition (PVD) such as sputtering, etc. A seed layer (not shown) covers the first surface 212, the second surface 214, and the inner sidewall of the via 230. In an embodiment of the invention, the seed layer is a thin layer of material which may include gold, tin, lead, copper, aluminum, silver, chromium, tungsten, niobium or combinations thereof or alloys thereof. The above seed layer facilitates nucleation and growth of the metal layer formed by electroplating. Then, an electric clock metal layer is formed on the seed layer by electroplating, and covers the first surface 212, the second surface 214, and the inner sidewall of the via 230. In an embodiment of the invention, the first plated metal layer may be made of the same material as the seed layer. Thereafter, a filling resin 203 filling the via holes 230 is formed. Then, the image transfer process can be utilized, that is, through the steps of covering photoresist, developing, etching, and stripping, part of the first plated metal layer and part of the seed layer are removed to the core. Patterned plated metal layers 220a and 220b are formed on first surface 212 and second surface 214 of plate 200, again as inner layer circuit layers 220a and 220b. Next, a build-up process is performed to form a first line build-up structure 240a and a second line build-up structure 240b on the first surface 212 and the second surface 214 of the core board 200, respectively. In an embodiment of the invention, the first surface 212 and the second surface 214 of the core board 200 are symmetrically disposed with the same number of line build-up structures. The first line build-up structure 240a may include an insulating layer 242a covering the inner layer circuit layer 220a, a patterned circuit layer 244a formed on the insulating layer 242a, and a patterned circuit passing through the insulating layer 242a for electrically connecting different layers. Conductive blind vias 201240045 246a of layer 244a and inner wiring layer 220a. The second line build-up structure 240b may also include an insulating layer 242b covering the inner layer circuit layer 220b and a conductive blind hole passing through the insulating layer 242b for electrically connecting the patterned layer layer 244b and the inner layer circuit layer 220b of different layers. 246b. It is to be noted that in this step, the wiring layer 244b formed on the insulating layer 242b is entirely covered with the insulating layer 242b without being patterned. In an embodiment of the invention, the first line build-up structure 240a and the second line build-up structure 240b may be formed by using a pressing process on the first surface 212 and the second surface 214 of the core board 200, respectively. An insulating layer 242a and an insulating layer 242b having the same material quality are attached. Thereafter, a plurality of blind vias may be formed in the insulating layer 242a and the insulating layer 242b by a laser drilling process to reserve a position where the conductive vias 246a and 246b are subsequently formed. Next, a patterned photoresist layer (not shown) is formed on the surface of the insulating layer 242a by an image transfer process, that is, via a step of covering photoresist, exposure, and developing, but in this step, the insulating layer 242b The patterned photoresist layer is not formed on the surface, and is not patterned by electroplating (the seed layer is formed into a conventional technique of electrowinning, so the figure is not shown), chemical deposition or electroless plating. Conductive blind holes 246a and 246b, a patterned wiring layer 244a, and a wiring layer 244b covering the surface of the insulating insulating layer 242b are simultaneously formed on the insulating layer 242a and the insulating layer 242b covered by the photoresist layer. In an embodiment of the invention, the conductive blind vias 246a and 246b, the patterned wiring layer 244a, and the wiring layer 244b may be made of nickel, gold, tin, copper, copper, quartz, chrome, tungsten, or Combination or alloy as described above. In an embodiment of the invention, the insulating layer 242a and the insulating layer 242b are made of the same material, for example, an epoxy resin, a bismaleimide 8 201240045 - a bismuth tree wall (bisma) eimide triacine , ΒΤ), polyimide, ABF film (ajinomoto buiid-up film) 'polyphenylene oxide (p>i phenylene oxide, i> pE) or polytetrafluoroethylene (p〇iyietra line u〇rethyiene, PTFE). Then, please refer to Figure 2 for a one-sided build-up process to form a plurality of third line build-up structures only on the first line build-up structure 24〇a structure. For example, the second line build-up structure 25〇, 26〇 And 27〇, and the minimum spacing of the patterned circuit layer of the third line build-up structure 270 at the outermost layer (the farthest distance from the core board 2〇〇) is the minimum pitch of the pads of the integrated circuit wafer . In an embodiment of the invention, the number of third line build-up structures is sub-restricted and is dependent on the customer's design. In an embodiment of the invention, the second line build-up structures 2.50, 260, and 270 are formed in a manner similar to the first-line build-up structure 2 and the second line build-up structure (four). When performing the one-sided germanium layer process for forming the third line build-up structures 25A, 26B, and 270, the mask line of the second line build-up structure 24〇b may be covered using a masking mask such as a polymerized dry film photoresist. Circuit layer 244b. For example, the formation of the second line build-up structure 250 may include attaching the insulating layer 252 to the first line build-up structure 240a of the core board 200. You can use the laser drilling process to form a plurality of blind holes in the ε ε layer 252 to reserve 彳a» —, ♦ bit I of the subsequent formation of the conductive blind hole 2 5 6 . The receiver uses the image transfer process, that is, through the step of overcoating (10) photoresist exposure and development, on the surface of the insulating layer 252, a patterned photoresist layer (not shown) is used, and then the electric ore is used. The layer, the formation, the conventional technology of the electric money is not shown, the chemical deposition or the electroless ore, etc. 'on the insulating layer 252 not covered by the patterned photoresist layer 201240045 to form the conductive blind hole 256 and the patterning Circuit layer 254. Thereafter, the process is repeated, and third line build-up structures 260 and 270 are sequentially formed on the third line build-up structure 250, wherein the third line build-up structure 260 includes an insulation covering the third line build-up structure 250. a layer 262 and a conductive via 266 passing through the insulating layer 262 and electrically connecting the patterned layer 264 of the different layers and the patterned wiring layer 254, wherein the third line build-up structure 270 includes a third line build-up layer An insulating layer 272 of the structure 260 and conductive vias 276 are formed through the insulating layer 272 for electrically connecting the patterned layers of the different layers and the patterned wiring layer 264. In an embodiment of the invention, the thickness T2 of the wiring layer 244b may be equal to the thickness T1 of the patterned wiring layers 254, 264, and 274. Alternatively, in another embodiment of the invention, the thickness T2 of the wiring layer 244b may be greater than the thickness T1 of the patterned wiring layers 254, 264, and 274 such that the second wiring buildup structure 240b has a higher mechanical strength. It is to be noted that since the wiring layer 244b is entirely covered by the insulating layer 242b and is not patterned, the thickness T2 of the wiring layer 244b is equal to or greater than the thickness T1 of the patterned wiring layers 254, 264 and 274, and can be avoided. Subsequent to the single-layer build-up process to form the third line build-up structures 250, 260, and 270, the problem of plate surface bending is caused by uneven stress. In an embodiment of the invention, the conductive vias 256, 266, and 276 of the third line build-up structures 250, 260, and 270, and the patterned circuit layers 254, 264, and 274 may comprise nickel, gold, tin, lead, Copper, aluminum, silver, chromium, tungsten, tantalum or combinations thereof or alloys thereof, and the insulating layers 252, 262 and 272 of the third line build-up structures 250, 260 and 270 may be the same as the insulating layer 242a and the insulating layer 242b Material. It is worth noting that the minimum pitch and minimum line width of the patterned circuit layer in the third line build-up layer 201240045 structures 250, 260 and 270 from the inside to the outside can be designed to be gradually reduced so as to be located at the outermost layer (from the core) The minimum pitch P1 of the patterned wiring layer 274 of the third line build-up structure 270 of the farthest distance of the first surface 212 of the board 200 is equal to the minimum pitch of the pads of an integrated circuit wafer. In addition, it is noted that, in an embodiment of the present invention, the conductive blind vias and circuit layers of the first line build-up structure 240a and the third line build-up structures 250-270 are not plated through the vias 230. The path is formed, so at least one of the first line build-up structure 240a and the third line build-up structure 250-270 has conductive bounces, such as conductive baffles 246a, 256, 266, and 276 at intermediate positions, which are not conductive. The holes 230 are electrically connected. Then, please refer to FIG. 3 for forming a one-sided build-up process (including the first line build-up structure 240a and the third line build-up structure 250, 260, and 270) on one side of the fine pitch of the integrated circuit. Thereafter, a second patterned wiring layer 244c conforming to the pitch of the printed circuit board is formed. As shown in Fig. 3, on the third line build-up structures 250, 260 and 270, a mask layer 280 such as a polymerized dry film photoresist or photoresist is formed in a comprehensive manner. Next, an exposure and development step is performed to pattern the mask layer 282 as shown in Fig. 2 to form a mask pattern 282a covering the wiring layer 244b as shown in Fig. 2. Then, an etching process is performed to remove the wiring layer 244b which is not covered by the mask pattern 282a. Finally, a stripping step can be performed to remove the mask layer 280 and the mask pattern 282a to form the patterned wiring layer 244c shown in FIG. It should be noted that the minimum pitch P2 of the patterned circuit layer 244c above the second surface 214 of the core board 200 conforms to the printed circuit board ball pitch and is smaller than the minimum of the patterned circuit layer 274 201240045 of the third line build-up structure 270. Spacing pi. In addition, it should be noted that, in an embodiment of the present invention, since the conductive blind vias and the wiring layers of the second wiring build-up structure 240b are not formed by the vias 230 as the plating conduction path, the second wiring layer is formed. At least one conductive blind via in the structure 240b, such as the conductive via 246b at the intermediate position, is not electrically connected to the via 23 (). Then, referring to FIG. 5, the solder resist insulating layers 284a and 284b may be formed on the third wiring layer structure 27 and the second wiring layer forming structure 240b by coating, printing, laminating, pressing, or the like, respectively. And an open-loop process such as laser drilling, plasma etching or image transfer may be used to selectively form a plurality of openings 286a and 286b' and expose portions in the solder resist edges 284a and 284b, respectively. The circuit layers 274 and 244c are patterned. In an embodiment of the invention, the solder resist layers 284a and 284b may comprise a solder resist material such as green lacquer, or may comprise a polyimide, an abinomoto build-up film or a polypropylene (a The insulating material of polypropylene, PP), which protects the conductive vias 246b, 276 and the patterned wiring layers 244c, 274 under them from being oxidized or shorted to each other. Additionally, openings 286a and 286b through the solder resist layers 284a and 284b can provide locations for subsequent pre-soldering metal bumps. Next, metal protective layers 288a and 288b can be formed on the patterned wiring layers 274 and 244c exposed from the bottom surfaces of the openings 286a and 286b, respectively, by chemical deposition and electrochemical methods. In an embodiment of the present invention, the material of the metal protective layers 288a and 288b may include nickel, gold, tin, lead, aluminum, silver, chromium, tungsten, palladium or a combination thereof or an alloy thereof, which may increase the subsequent formation. The bonding force of the solder bumps to the patterned wiring layers 274 and 244c. Then, a pre-soldering metal bump 290 may be formed on the metal protection layer 288a conforming to one side of the integrated circuit wafer thin compartment 12 201240045 by chemical deposition, steel plate printing, micro-balling process or electroplating metal. To provide integrated circuit die bonding. In an embodiment of the invention, the material of the pre-soldered metal bumps 290 may include nickel, gold, tin, tin, copper, sulphur, silver, chrome, crane, or combination thereof or alloys thereof. After the above process, the package carrier 500 of one embodiment of the present invention is formed. Fig. 6 is a view showing a package structure in which a package carrier 500 and an integrated circuit chip 300 are combined in accordance with an embodiment of the present invention. As shown in FIG. 6, an integrated circuit wafer 300 can be bonded to the pre-soldered metal of the package carrier 500 in accordance with one side of the fine pitch of the integrated circuit wafer by wire bonding, lead frame bonding, or flip chip bonding. Bump 290. In an embodiment of the invention, a primer 292 may be disposed between the integrated circuit wafer 300 and the solder resist layer 284a. Then, an open-loop printing stencil may be selectively disposed on the solder resist insulating layer 284b of the package carrier 500 on one side of the printed circuit board pitch, wherein the position of the open loop is substantially aligned with the position of the opening 286b . Thereafter, the solder paste is scraped or extruded into the open loop of the printing stencil so that the surface of the metal protective layer 288b and the opening 286b located in the open loop of the printing stencil are covered with solder paste. The solder paste on the surface of the metal protective layer 288b and the opening 286b is melted into a sphere by using a reflow method to form a pre-solder metal bump such as a solder ball or a solder paste in the opening 286b. Block 302. In an embodiment of the invention, the pre-solder metal bumps 302 and the pre-soldered metal bumps 290 may have the same material. After the above process, a package structure in which the package carrier 500 and the integrated circuit wafer 300 of one embodiment of the present invention are combined is formed. Finally, the package structure described above can be ensured by electrical testing to provide a package structure that is directly bonded to the printed circuit board. 13 201240045 Embodiments of the present invention provide a package carrier and a method of fabricating the same. The package carrier of the embodiment of the invention is a package carrier with an asymmetric build-up structure, which uses a single-sided build-up technology to route the integrated circuit wafer carrier circuit of the prior art to the transfer carrier (interP〇ser The other side of the package carrier is adapted to meet the ball pitch requirements of the printed circuit board (7CB) in order to achieve the fine pitch requirement of the integrated circuit chip. . Since the package carrier of the embodiment of the present invention designs the integrated circuit chip (1C) carrier and the interposer as a main carrier, the cost of package ball and yield loss can be saved. Further, the package carrier of the embodiment of the present invention may have a surface designed to have a pre-welded metal bump or a gold finger. Therefore, after being packaged with the integrated circuit chip, the WJ can be directly bonded to the (4) circuit board by surface adhesion technology (SMT)... The process is stacked into a package (P0P) process and related materials, and the finished product f degree can be reduced. In addition, the package carrier of the embodiment of the present invention is formed by the uniformity of the single-layer build-up layer and is not subjected to the build-up process of the carrier side of the board (PCB). =, so that the problem of bending the surface of the embodiment has been avoided. The above is not intended to limit the present invention, and it is intended to be modified or not to deviate from the spirit and the refinement of the present invention within the scope of the skilled artisan. The patent of the money is subject to the patent. 14 201240045 BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 to 5 are cross-sectional views showing a process of a package carrier according to an embodiment of the present invention. Figure 6 is a schematic view showing a package structure of a package carrier and an integrated circuit chip according to an embodiment of the present invention. [Main component symbol description] 200 to core plate, 203 to hole resin; 212 to first surface; 214 to second surface; 220a, 220b to inner layer circuit layer; 230 to via hole; 240a to first line buildup structure 240b~second line build-up structure; 242a, 242b, 252, 262, 272~ insulating layer; 244a, 244c, 254, 264, 274~ patterned circuit layer; 244b~ circuit layer; 246a, 246b, 256, 266 276~ conductive blind hole; 250, 260, 270~ third line build-up structure; 284a, 284b~ solder resistive layer; 286a, 286b~ opening, 288a, 288b~ metal protective layer; 290, 302~ pre-weld metal Bump; 292~ primer; ]5 201240045 300~ integrated circuit wafer; 500~ package carrier PI, P2~ minimum spacing ΊΠ, T2~ thickness. 16