TW200805611A - Manufacturing method of substrate without using exposure developing process and its inserted circuit structure - Google Patents

Abstract

In the invented manufacturing method of substrate without the application of exposure developing process and its embedded circuit structure, only one from the UV (ultra-violet) light, the excimer laser and the mold is used to form the minute via -hole trough and/or circuit trough in the build-up material on the core-layer substrate, in which minute via -hole and circuit are formed after forming the electroplated metal inside the via -hole trough and the circuit trough. Thus, as no exposure developing is used, it is capable of using the same machine to manufacture the minute via -hole and circuit such that it is easy to control the precision. As the circuit isembedded in the build-up material, the adhesion force is greatly increased and is not changed due to the condition control of the following process and the chemical liquid such that the line-width control is easy to reach high density. Therefore, the alignment precision is high; and it is easy to manufacture the ring-less via -hole for the minute via hole between the layers so as to increase the layout space.

Description

200805611 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method for fabricating a carrier plate and a shunting circuit structure thereof, and more particularly to the use of exposure and development (4) carrier plates for green and (10) wiring structures.

[Prior Art] Due to the trend of thin and light electronic products and the increasing functions, the number of I/Os in the chip is rapidly increasing, and the relative packaging technology is constantly updated. Nowadays, in the high-end products, most of the flip chip packages (Flip Chip) ), the packing density is also followed

Constantly developed from 90 coffee to 65nm, even to 45nm mass production technology. In order to improve the performance of the carrier, the low dielectric constant ([(10)k) wafer (Wafer) is also used, but the line width uniformity (secret (4) (7) control must be controlled by the current ^ 15% (25 coffee V- 5um) is upgraded to 1〇15um仏1〇% (1〇Curry's high specification' while the line width on the IC carrier board is thinner, that is, it must be quickly reduced to 30 qing or even 2 〇 (10). For the inter-layer shaving and guiding hole ring (8)), the size is also reduced from one side 25 to 15 sec or even no bonnet. However, due to the thinning of the line, the adhesion of the line and the substrate is greatly reduced, and the product is trusted. Sexual testing has produced great care. It is imperative to call the new touch structure reduction method to provide solutions. /' The well-known 1C structure is generally: layer to eight-layer laminate, the material used is Tao 5 200805611 Research or organic materials. In the manufacture of wealth, the process of the material-sensitive process is based on the material, and the process is controlled by the production conditions of Wei, and the manufacturing tolerances are simply Plate (2) layered; (3) laser drilled micro-via; (4) deposited metal; (5) posted _ light material, (6) exposure Into the line; (7) imaging; (8) electric money; (9) stripping of photosensitive material '·(10) fast money engraved deposition of conductive metal layer formation to line 0 between the above steps (3) ~ (6) and (4) due to different machinery manufacturing, in high precision When the accuracy of the alignment is difficult, and in the steps (8) to (10) ♦, due to the characteristics of the drug cartridge and the design of the device, Wei will make a miscellaneous (four) financial record to master, the manufacture of metal scales, especially in the line. Thinning, the material has a single-sided contact 'and the thin line is thinned and greatly reduced: over the reliability test. [Invention] The main purpose of the present invention is to provide a kind of not to use The production method and its inner lining structure, which excludes the inherent prejudice, eliminates the production of micro-via holes and circuits, must be exposed, developed, and other processes, with ultraviolet light _, excimer laser version recommended Laser and mold money - , in the core layer of the knife layer 200805611 material to form a small hole pattern to make tiny holes and / or line = line groove, and after the shape of the metal inside the same: the second = mining light development, Small guide holes can be made from the same machine After not because ㉟, embedded in the build-lion towel, domains force to enhance reading and sound. The control of the Lai phase condition is changed, the line width control (4) reaches the high density ==7##娜(四)尔_ and the closed type [implementation] ==:;=_production method and its _ road_ in the alignment, making fine飨 毋 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 GALAXY, but the part of the aligning and returning layer of the present invention does not use the exposure of Gu Dan, using 18h as shown in Figure 1G~II. First, the method of making the carrier board is to make the micro-j Line 18a (as shown in Figure π). The special clothes made a small through hole clear reference to the first Α Η , ,, # 1 Α 载 制作 制作 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 uf uf uf uf uf uf uf uf uf uf uf uf uf uf uf uf uf uf uf uf uf Shown here is a method for fabricating a 7 200805611 carrier board which does not employ an exposure and development process. In short, this is ....................

A conventional manufacturing method in which the core layer substrate 2 () is not produced is shown. As shown in Figure 1F, in the core calendar, its seven 9n uυ "π _

10 The original dielectric material will form the build-up material i3 for the layered portion, but there is no difference in the material, so there is no special difference between the different terms. After the completion of the formation of the build-up material 13, a micro-via hole is formed in the build-up material 13 by ultraviolet light (UV), excimer laser, and mold without using an exposure and development process. 14 and/or line slot 12, as shown in the ig diagram. Since it is known that ultraviolet light (UV) is used as a burnt wiring and a small pilot hole (contact), it is not accompanied by some problems, and since it is relatively easy to control, it is formed in a small amount. When the guide hole 14 and/or the line groove 12 are used, ablation using violet 200805611 external light (UV) is the best choice. The ultraviolet light (10) is fired, and each of the small via holes 14 and/or the path grooves 12 may be formed one by one, and the micro-channel holes 14 having different depths and shapes may be formed under the control of the burning time and speed. Line slot 12. If a special lens is used for the splitting, the ultraviolet light (―uv) can also be used to make several tiny via slots 14 and/or line slots at the same time. After the microvia 14 and/or the trench 12 are completed, a metal wire capable of transmitting a signal and a post-processing procedure are formed. An environment capable of conducting an electric ore current is formed on the augmented material 13 in the small via holes 14 and/or the line grooves 12 in the "conductive metal layer'. Then, as shown in FIG. 1H, a full-plate fill electric ore is used in the conductive gold to shovel the metal layer 16 and remove a portion of the second metal layer 16' by side and/or grinding until the exposed portion is exposed. Material 13, such as the π riding. In the case of =1, the line groove 12 filled with the second plating metal 16 is the circuit board, and the minute hole 12 of the true full-metal metal 16 is the minute conduction hole (10). In this way, because the exposure and development are not used, the micro-conductor can be made into the circuit board by the same machine, and the accuracy is easy to grasp. The line 18a is increased by the internal temperature, and the adhesion of the layered material 13 is greatly improved, and the condition of the German/female water (due to the need to use exposure development) is greatly improved. Control and (4) and drug density. _Make a small guide hole (10) and a small guide hole between the lines to make a non-porous Namail (10) guide hole Y 曰 In addition, as shown in the fourth (four), the production of the core layer substrate 20, ^ cloth, work room. A metal layer 3 having a thickness of 9 200805611 and a thickness of about 8 to 12/zm is formed on the substrate 1 as shown in Fig. 1A. The material of the substrate 1 is generally selected from Bismaleimide Triazine (BT) or other organic materials, and even ceramic materials. Next, a core substrate through hole 5 having a width of about 1 〇〇 to 25 〇 is formed through the metal layer 3 and the substrate by a mechanical iron hole ', as shown in Fig. 1B. Then, a first plating metal layer 7 having a thickness of about 丨(四)_ is formed on the metal layer 3 and the sidewall of the core substrate via 5 as shown in the first figure (as shown in the figure). The first key metal layer 7 and the metal layer 3 of the knives are removed until the substrate is exposed. Thus, in the first plating metal layer 7 and the metal layer 3, the inner layer wiring opening n, the first plating metal layer 7 and the metal which are not removed are formed. The layer 3 is an inner layer line. The dry film 9_ shown in Fig. 1F is formed by a circuit. The patterned dry film 9 is formed on the f-wei metal layer 7 as a removed portion. And a mask of the metal sound 3. Then, a build-up material 13 is formed to cover the first electric metal layer 7, the inner layer line opening n and the core substrate through hole 5, as shown in the third figure. The surface of which is covered by the build-up material 13 is a coated carrier. It is intended to more clearly describe the features and spirit of the present invention by the detailed description of the preferred embodiments above, and not The specific embodiment disclosed above (4) is intended to be against the present invention. Conversely, the purpose is to The arrangement of various changes and specificities is within the scope of the patent scope of the present invention. 200805611 [Simple Description of the Drawings] Figs. 1A to II are diagrams showing a method of manufacturing a carrier which does not employ an exposure and development process. [Description of main component symbols] 1 substrate 3 metal layer _ 5 core substrate via 7 first plated metal layer 9 dry film 11 inner layer line opening 13 build-up material 12 line groove 14 micro-via hole φ 16 second plated metal layer 18a Line 18b tiny guide hole 11

Claims (1)

200805611 X. Patent application scope: 1. A method for fabricating a carrier board without using an exposure and development process, the method for fabricating the carrier comprises: providing a core layer substrate; forming a build-up material on the core layer substrate; The exposure developing process forms a micro via groove and/or a line trench in the build-up material only by one of ultraviolet light (UV), excimer laser and mold. 2. The method for fabricating a carrier plate according to claim 1, wherein the method for fabricating the carrier further comprises: depositing in the microvia and/or the trench a conductive gold φ layer; forming a first plated metal layer on the conductive metal layer with a full-board fill-in electricity; and removing a portion of the second plated metal layer by etching and/or grinding until the portion of the layer is exposed Material; s where, the line, the line groove filling the second plating metal is a line and is filled with the micro-via 12 of the second electric clock metal. The 200805611 slot is the micro-via. 3. The method of fabricating a carrier layer that does not use an exposure and development process as described in claim 1, wherein the method of fabricating the core layer substrate further comprises: providing a substrate; forming a metal layer on the substrate; penetrating the metal a layer and the substrate, forming at least one core through hole; forming a first plated metal layer on the metal layer and the sidewall of the core substrate; removing a portion of the first plated metal layer and the Forming a metal layer until the substrate is exposed, and forming an inner layer wiring opening in the first plating metal layer and the metal layer, the first plating metal layer not removed and the metal layer being an inner layer line; a layer of material to cover the first plated metal layer, the inner layer line opening, and the core substrate via. 4. - In-board & line structure without exposure and development process, comprising: 13 200805611 - Core layer substrate having at least one build-up material on its surface; a line groove, only by ultraviolet light (uv) One of an excimer laser and a mold is formed in the build-up material; a line is formed in the line groove to form an electroplated metal belonging to the line, and the line is embedded in the increase The layer material φ is in the line trench; wherein a conductive metal layer is deposited in the line trench before forming the key metal. 14