SU563731A1 - Multi-channel device for transmission and reception of binary information - Google Patents

Description

one

The invention relates to communication technology and can be used in data transmission equipment.

A multichannel device for transmitting and receiving binary information is known, which contains shift registers, a manipulator, counters, a manipulated signal detector, triggers, and logic circuits. However, the provision of synchronization by the formation of a frequency-modulated signal leads to a breakdown of synchronization during fading of the signal in the communication channel.

The closest technical solution to the invention is a multichannel device for transmitting and receiving binary information, containing in each transmission channel the serially connected element I, the shift register, the frequency manipulator, the counter of the number of periods of oscillations of the carrier frequency, common for all the transmission channels To the inputs of which are connected the outputs of frequency manipulators, and in each reception channel - serially connected band-pass filter, amplitude limiter, frequency component Ktorov and shift register, and the count of the number of oscillations whose input is connected to the output of the amplitude limiter.

The purpose of the invention is to improve the synchronization accuracy of the transmitter and receiver.

This is achieved by the fact that in the proposed multi-channel device for transmitting and receiving binary information, a counter for the number of bit sendings and a control unit connected between the shift register and the frequency manipulator are entered into each transmission channel, while the output of the counter for the number of oscillations of the low frequency frequencies is connected to the first input the control unit and to the first input of the element I, and the outputs of the two last bits of the shift register are connected to the second and third inputs of the control unit, the output of the element I through the counter The fourth input of the control unit is connected to the fourth input of the control unit and the write input of the shift register is given a Start signal, the second output of the control unit is connected to the second input of the And element, and a trigger is inserted between each frequency channel the detector and shift register, the OR element and the counter of the number of bit sendings, the first and second outputs of the frequency detector are connected

to the setup inputs of the trigger, the outputs of which are connected to the information inputs of the shift register, and the first, second and third outputs of the frequency detector through the OR element are connected to the installation input

the counter of the number of periods of oscillations of the carrier frequency, one of the LOW-OUTS of which is connected to the reset input of the counter of the number of bit packages, and the second output of the number of periods of oscillations of the carrier frequency is connected to the shift register of the shift register and through the counter of the number of bit packages with the expansion input: binary information . Such a device provides an increase in the accuracy of synchronization of the transmitter and receiver while maintaining the information transfer rate and a predetermined duration of the bit messages, and the increase in the accuracy of the synchronization is performed by changing the sign of manipulation in each bit message. The drawing shows the structural electrical circuit of the proposed multi-channel device for transmitting and receiving binary information. A multichannel device for transmitting and receiving binary information contains, in each transmission channel, a serially connected element I 1, a shift register 2, a frequency manipulator 3, a counter 4 of the number of periods of oscillation of the non-skipping frequency, which is common for all transmission channels, frequency compaction unit 5 to which inputs are connected the outputs of frequency manipulators 3, in each channel of reception are series-connected band-pass filter 6, amplitude limiter 7, frequency detector 8 and shift register 9, as well as a counter 10 for the number of oscillations The input of which is connected to the output of the amplitude limiter 7, in each transmission channel - the number of bit packages entered by the counter 11 and the control unit 12 connected between the shift register 2 and the frequency manipulator 3, while the output of the counter 4 of the number of oscillations of the carrier frequency is connected to the first input of the control unit 12 and to the first input of the element I 1, and the outputs of the last two bits of the shift register 2 are connected to the second and third inputs of the control unit 12, the output of the element 1 1 through the counter 11 of the number of bits OK is connected to the fourth input of the control unit 12, while the fifth input of the control unit 12 and the write input of the shift register 2 is given a start signal, the second output of the control unit 12 is connected to the second input of the And 1 element. A trigger 13 is inserted into each receive channel, connected between the frequency detector 8 and the shift register 9, the element OR 14 and the counter 15 of the number of bit packages, the first and second outputs of the frequency detector 8 are connected to the setup inputs of the trigger 13, the outputs of which are connected to the information inputs of the shift register 9, and The first, second and third outputs of the frequency detector 8 are connected via OR 14 to the installation input of the counter 10 of the number of carrier frequency oscillations, one of whose outputs is connected to the input “Reset of the counter 15 bit packages and the second output of the counter 10 The number of periods of the carrier frequency oscillated with the shift input of the shift register 9 and through the counter 15 of the number of bit packages with the input of the issuance of binary information. A multichannel device for transmitting and receiving binary information operates as follows. At the beginning of the code word transmission cycle, register 2, counters 4 and I are in the zero state (after transmitting the next bit of information and after transmitting the entire code word, respectively). The transmission of the code word begins at the start. In this case, the binary information is recorded in the register 2 and the control unit 12 is started up, which, controlled by the manipulator 3, ensures that a block synchronization frequency signal with a duration equal to two information bits is generated at its output. To eliminate shifts in register 2 by the time of transmission of the block synchronization signal, block 12 closes element 1, prohibiting the passage of 4 clock pulses from the output of the counter. The first pulse, coming from the output of counter 4 and generated during the transmission of the block synchronization signal, enables the control unit 12 to operate in the register 2 state analysis mode. On the leading edge of the clock pulse, the analysis is performed, and on the falling edge, the analysis result is output of the manipulator 3 and the prohibition is removed, which is fed to the input of the element I 1, which further provides the passage of the shift pulses to the input of the register 2 and the counting of their number in the counter 11, the reset pulse of which translates b approx 12 to its original control state. In block 5 of frequency multiplexing, signals coming from other similar channels operating in different frequency bands are combined. On reception, the filter 6 extracts from the signal the frequency band of this channel, after which the received signal is fed through the amplitude limiter 7 to the inputs of the three-frequency detector 8 and the counter 10. The output signals of the detector 8 control the state of the trigger 13 and, regardless of the sign of the received signals, provide the OR 14 reset of the counter 10. Therefore, at the beginning of receiving the information bits due to the mandatory change of the manipulation feature, the OR element 14 resets the counter 10, which ensures that its operation is synchronized exactly for the time EMA each bit parcels. After resetting the counter 10, the number of oscillation periods of the received signal starts. If a long sending of block synchronization is received, then at the first output of counter 10 a pulse is released, which resets counter 15. In order to protect against short-term fading in the communication channel, in the time interval

the transmission of one bit burst in the counter 10 counts the number of received vibrations. If the number of received oscillations is not less than a predetermined number, then the pulse from the first output of counter 10 shifts the information in register 9, at which the trigger state 13 is assigned. At the same time, the specified pulse arrives at the input of counter 15, where it adds up to the number previously received bit packages. Since the recalculation module of the counter 15 is equal to the length of the transmitted code word, its output pulse allows the output of information from the shift register 9.

Claims (1)

Invention Formula A multichannel device for transmitting and receiving binary information, containing in each transmission channel a serially connected element I, a shift register, a frequency manipulator, a counter for the number of periods of carrier frequency oscillations, a frequency seal block common to all transmission channels, to the inputs of which frequency frequency outputs are connected. , and in each reception channel - series-connected band-pass filter, amplitude limiter, frequency detector and shift register, as well as a count of the number of oscillations, in d is connected to the output of the amplitude limiter, characterized in that, in order to increase the accuracy of the transmitter and receiver timing in each transmission channel a count of the number of bit Ilolocs and a control unit connected between the shift register and the frequency manipulator are introduced, and the output of the number of periods counter carrier frequency oscillations are connected to the first input of the control unit and to the first input of the I element, and the outputs of the last two bits of the shift register are connected to the second and third inputs of the control unit, the output of the element I is connected to the fourth input of the control unit through the counter of the number of bit sendings, the fifth input of the control unit and the write input of the shift register are given a Start signal, the second output of the control unit is connected to the second input of the And element, and a trigger is inputted to each receive channel, connected between the frequency detector and the shift register, the OR element and the counter of the number of bit parcels, the first and second outputs of the frequency detector are connected to the setup inputs of the trigger, the outputs of which are connected to the information and the inputs of the shift register, and the first, second and third outputs of the frequency detector through the OR element is connected to the installation input of the counter of the number of periods of oscillations of the actual frequency, one of the outputs of which is connected to the reset input of the counter of the number of bit sendings, and the second output The counter of the number of periods of oscillation of the carrier frequency is connected to the shift input of the shift register and through the counter of the number of bit packages to the input of the resolution of the output of binary information. Output g 8 channel Fifth Schnal transfer.