SU1238054A1 - Multichannel device for entering analog data and buffer storage - Google Patents

Abstract

The invention relates to measuring and computing technology and can be used in high-performance systems for collecting and processing analog data. The purpose of the invention is to increase the speed of a multi-channel device for inputting analog data and expanding the scope of application of the buffer memory. Introduction to a multi-channel buffer memory device with additional address inputs allows organizing parallel processing of information from simultaneously triggered data conversion channels. The buffer memory contains two RAMs of a number of control units and can operate in three modes; simultaneous recording of information from several failed channels into the first RAM, rewriting of information from the first RAM into the second, reading information from the second RAM. 2 sec. the item f-ly, sg 4 il. (/ IN :) oo 00 sd

Description

The invention relates to measuring and computing equipment, memory devices and can be used both together in the construction of high-performance systems for collecting and processing analog data using a multiplicated structure and computer, and separately in the construction of multi-channel systems and buffer drives.

The purpose of the invention is to increase the speed of a multi-channel device for inputting analog data by organizing the parallel recording of information in several memory cells.

FIG. 1 shows a block diagram of a multi-channel device for inputting analog data; in fig. 2 is a block diagram of a control unit of a multi-channel device; in fig. 3 - buffer memory; in fig. 4 — buffer storage control unit.

FIG. 1, module 1 contains, consisting of channels, control block 2, counter 3, digital-to-analog converter (D / A converter) 4, priority address generation unit (BFPA), buffer memory 6 (BDU), comparators 7, triggers 8, AND elements the first group 9, the elements And the second group 10; elements OR 11; bus 12 logical units, address inputs 13 and 14 BZU of the first and second groups, information inputs 15 BZU, output 16 of the control unit synchronization, input 17 of the end of the cycle of the control unit, control inputs 18 of the multichannel system, input 19 of the request of the control unit, reset output 20 a control unit request, control inputs 21 BZU; information 22 and control outputs 23 of the device.

FIG. 2 denotes: a generator of 24 square-shaped pulses, two triggers 25 and 26, two counters 27 and 28, two main amplifiers 29 and 30, three elements OR 31, 32, 33 and element 34.

FIG. 3 denotes: the first 35 and the second 36 groups of memory blocks 37 and 38, respectively, two counters 39, 40, the decryptor 41; multiplexer 42, control unit 43, OR 44, third counter 45, logical unit bus 46.

FIG. 4 marked: two trigger 47, 48; five elements And 49-53; two elements OR 54, 55 and counter 56.

A multichannel analog data input device operates as follows.

Module 1 (a group of t channels) provides a comparison of the levels of exemplary balancing voltage and voltage at each of the device t inputs, fixing the level matching independently For each channel and generating the "Query when the comparator triggers, at least in one of the t channels in the module . Module 1 can be implemented on commercially available integrated circuits (IC), for example, the K554 and K155 series. When using these series of microcircuits, the comparator 7 is a K544CASE chip.

Control unit 2 provides control and synchronization of the entire system, as well as reception of control commands from the outside, for example from a computer, and can be implemented on commercially available ICs, for example, K155, K561 series. When using scientific research institutes of microcircuits of these series, triggers 25 and 26, counters 27 and 28, main amplifiers, elements OR 31, 32, 33, and element 34 represent respectively К155ТМ2 К561IE9, К155ЛП9, К155ЛЛ1, К155ЛИ1. The pulse generator 24 is, for example, a K155LAZ microcircuit connected to time with master resistors and capacitors according to the multivibrator circuit. Counter 3 is, for example, a chip K155IE6.

0. DAC 4 is, for example, a series-connected current-DAC chip, the K594P1 and the K544UD2A operational amplifier, which converts current to voltage.

The BFPA 5 provides for the formation of codes of the numbers of the modules that have generated requests in accordance with the priority, with the position binary code being formed on the first group of outputs, the unitary binary code on the second group of outputs, and a request for asking for at least three from one module BFPA 5 is a serially connected priority encoder and decoder, the outputs of which are, respectively, the first and second groups of outputs of BFPA 5, and 1 input circuit OR, the output of which is the third output of the device, connected in parallel with the inputs of the encoder. The priority encoder, descrambler and -input circuit OR can be, respectively, chip 0 K155IV1, K155ID1, K155LL1.

BDU 6 provides for the matching of the rates of conversion of analog signals into codes and data entry speeds into a computer in order to maximize the speed of the data acquisition and processing subsystems. BZU 6 allows recording at an arbitrarily specified address into one

or several (up to t} memory cells, and the reading should be completed with a message complete and orderly, one cell at a time, starting at the cell with the starting address, and writing and reading can be done with the same and at different times. LPD 6 can be implemented on commercially available microcircuits, for example, the K 155 and K 531 series. When using microchips of this series, groups 35 and 36, for example, are K155RU2 microcircuits, counters 39, 40, 45, decoder 41, multiplexer 42, the element OR 44 are, respectively, chips K155IE1, K155ID1, K531KP11, K155LL1.

The unit 43 controls the operation of the LPD 6 in all modes, as well as the generation of service signals zl and 22, notifying external devices about the presence or absence of information in the RAM 7, and about allowing or prohibiting writing to it. Block 43 can be implemented on commercially available chips, for example, the K155 and K561 series. In this case, the triggers 47 and 48, the elements AND 49-53, OR 54 and 55 and the counter 56 are respectively the chips K155LI1, K155TM2, K155LL1, K561IE9.

The operation of the analog data input system in the computer and the buffer storage device for the data input system is controlled by the computer, which generates the Start, Reset, Flag Setting and Read Pulses commands to the control unit 18 of the control unit 2. In the initial state, when the power is turned on or the start of operation, counter 3, all triggers 8 of all modules 1, triggers 25 and. 26 of the control unit 2, the triggers 47 and 48 of the unit 43 are set to the initial (zero) state, and the outputs 23 of the service information generate signals and r2 0, which corresponds to the resolution of the recording and the prohibition of reading from the OVD 6 due to the lack of data in last one.

When the start signal arrives at control unit 2, sync pulses are generated at its output 16 and fed to counter 3, the outputs of which are connected to the inputs of the DAC 4, while the output of the DAC 4 is formed by a stepwise variable reference voltage. At the moment of coincidence of the level of reference voltage and voltage at one or several inputs of the device at the output corresponding to this input (inputs) of the comparator 7, a voltage drop (for example, from the state "O to" 1), according to which the corresponding trigger 8 (trigger 8) goes into one state. The logic level “1 from the output of the trigger 8, through the element OR 11, as a request goes to the input of the BFPA 5. The BFPA 5, according to one or several requests, forms at its outputs, respectively, the unitary and positional codes of the highest priority from the generated modules and the signal“ The request arriving at the input 19 of the control block 2.

In block 2 of control, generator 24 generates clock rectangular pulses that ensure the implementation of the principle of synchronous control of all devices of the system, are fed to both counters 27 and 28 and to the output of block 2 of control. The counters are used as frequency dividers and pulse distributors, the counter 27 is used to control the counter 3 of the DAC 4, the counter 28 to control the recording of data in the OVD 6.

As a rule, the time for setting the voltage at the output of the DAC 4 with a given error is significantly longer than writing to the RAM, and therefore the division ratio of the counter 27 is greater than the counter 28. The pulses from the output of the counter 27, through the OR 33 element, arrive at the C input of the trigger 26, and, if requested, translate the latter into a single state. In this state, trigger 26 prohibits the operation of counter 27 (the formation of the next pulse for counter 3), i.e., pauses the sweep for the duration of the recording in the RAM and enables the operation of counter 28. The pulse from the first two outputs of the counter 28 and RAM 7 is implemented recording data from the channel group that formed the request. The leading edge of the pulse from the third output of the counter 28 (output 20 of the control unit 2 through the And 10 element sets the trigger 8 of the serviced module 1 to the zero state, which leads to the removal of the request from this module. By the time the falling edge arrives from the third output of the counter 28 through the OR element 33, the C input of the trigger 26 at the D input will be set to logic level "1 if the requests were formed by several modules, the recording procedure is repeated, otherwise the logic level" O and trigger trigger will be formed on the) input of trigger 26 children in the null state, thus will be resumed formation of the stepwise-varying model voltage until a next request. Upon reaching a stepwise varying reference voltage of the range boundary, the counter 3 generates a pulse "Overflow", which through the OR element 31 of the control unit 2 enters the I-input of the flip-flops 25 and 26, setting them to the zero state. In this case, the formation of pulses for the counter 3 (element 34) is prohibited and the OU 6 is signaled about the end of the recording of information about analog signals (trigger output 25). After each conversion cycle of the analog signals (measurement cycle), the counter 3 and all the trigger 8 are automatically reset.

When the following command is received from the computer, the system starts up in a similar way, while simultaneously converting the analog signals, information can be read out from the RAM 6. The readout takes place when the computer reads read pulses.

In the initial state (when the power is turned on or by the commands "Setting the flag, Reset, all the counters 39, 40, 45, BZU 6 are set to the zero state, on all outputs of block 43, except for the fifth, to zero, to the outputs of the multiplexer 42 Inputs 13 are connected, and BZU 6 is ready to record data. Record in BZU 6 is possible at an arbitrary address and in the number of cells less or

equal to t at the same time. The entry address is divided into two parts A and AE of the address and subaddress and goes to the corresponding 14 and 13 inputs of the RAM 6. The address code determines the cell number in block 37 of group 35, enters the binary unitary code and is common to all blocks 37, code The subaddress identifies the blocks 37 to which the recording will be made and enters in binary positional form. The address code goes to the address inputs of the blocks 37 when a pulse 39 is sent to the Y input of the counter, which writes to the counter, and the sub address code goes from the output of multiplexer 42 to the control inputs Sample Blocks 37, allowing or disallowing to write to them. Thus, depending on the code at the outputs of the multiplexer 42, it can be carried out both sequentially and simultaneously writing to the RAM 6.

The recording end signal (negative differential), which arrives at the third input of block 43, translates trigger 47 into one state and through the AND 52 element at the first output of block 43 a logical level "1" (i.e., "Rip discarding signal") is set. Therefore, the signal resolves the operation of counter 56, and the decoder 41 and multiplexer 42 are switched to the state when all their outputs are set to "1, i.e., to the inputs" Sampling of all blocks 37 and 38, the signal "sampling resolution. The pulses from the output of counter 56 arriving at the C-inputs of counters 39 and 45 start to work synchronously, looping through all the addresses of the cells in blocks 37 and 38, and before each change of address information is read from all blocks 37 and written into all blocks 38. The overflow pulse of the counter 45, which arrives at the eighth input of the block 43, sets the trigger 47, 48 to the zero state, sets z 0; z2 0 - writing and reading of information from BZU 6 is allowed, - and removes the overwrite permission.

Upon receipt of read pulses to control inputs 21 of BZU 6, counters 40 and 45 and decoder 41 provide sequential reading of data from group 36, i.e., first the word will be read from the first cell of the first block 38, then from the first cell of the second block 38 and t . d. (in order of increasing the channel numbers of the multichannel system). When the counters reach the last address of the group 36, the element And 50 generates a "End of Read" signal that will translate the trigger 48 into one state (g 1), allowing the next rewriting cycle to be carried out. Depending on the ratio of the write and read times (in the case of use in conjunction with multi-channel analog data entry systems, the ratio of the measurement times and data entry into the computer) occurs or the transfer of the OVD 6 to the initial

state (write enable), or immediately back to the overwrite state if by the end of the readout r 0 22, i.e., writing to the first group 35 has already been completed.

The presence of the nth input of block 43 "Reset or" Setting the flag allows a computer command to allow rewriting of information even in cases when the reading from the second group 36 is not completed, for example, it makes no sense to complete it due to the lack of need for all data or for other reasons.

Thus, the buffer storage device allows one to record both simultaneously in / p-cells, and sequentially one by one, which additionally allows to reduce the time for writing and reading data both in complete units and in fragments.

20

Claims (2)

1. A multichannel analog data input device containing a control unit, a counter, a digital-to-analog converter, comparators, triggers, the first group of AND elements, an OR element, a priority address generation unit whose output is connected to the request input of the control unit whose control inputs are control inputs of the device, the synchronization output of the control unit is connected to the counter input, the overflow output of which is connected to the loop end input of the control unit, the counter outputs are connected to the inputs and a digital-analog converter, the output of which is connected to the second inputs of the comparators, the first inputs of which are information inputs of the device, the output of each comparator is connected to the C input of the corresponding trigger, the outputs of which are connected to the second inputs of the corresponding elements of the first group, the D inputs all the triggers are connected to the bus of a logical unit, characterized in that, in order to increase the speed of the device, due to the organization of parallel processing of information from simultaneously 5 The device contains the second group of elements And the buffer memory, the information and control outputs of which are respectively the information and control outputs of the multichannel system, to the control inputs 0 buffer memory, the control outputs of the control unit are connected, the counter inputs are connected to the information inputs of the buffer memory, the reset output of the request of the control unit is connected to the second inputs of the AND elements, the second group, the outputs 5 of which are connected to the / -inputs of the corresponding triggers, the inputs of the element OR are combined with the second inputs of the corresponding elements AND of the first group, the output each element OR is connected to the corresponding input of the priority address generation unit, the outputs of the positional code of which are connected to the first inputs of the corresponding elements AND of the second group, the outputs of the unitary code of the priority address generation unit are connected to the address inputs of the second group of the buffer memory, to the address inputs of the first group of which are connected the outputs of the corresponding elements And the first group, the first input of each element And the second group is combined with the first inputs of the corresponding elements And the first th group 2. Buffer memory containing memory blocks of the first and second groups, first and second counters, a decoder, a multiplexer, a control unit, to the seventh input of which the last output of the decryptor is connected, the enable inputs of the recording of memory blocks of the first group, the selection input the first counter, the counting input of the second counter and the second, third, fourth, fifth and sixth inputs of the control unit are the control inputs of the buffer memory; the setup inputs of the first counter are the address inputs of the second group of the buffer memory; the outputs of the first The detectors are connected to the address inputs of all the memory blocks of the first group, the corresponding information inputs of the memory blocks of the first group are combined and are information inputs of the buffer memory, the reset input of the first counter is combined with the third input of the control unit, the fifth and sixth outputs of which are device outputs, the fourth output of the control unit is connected to the reset input of the second counter, the information outputs of which connected to the information inputs of the decoder, the outputs of which are connected to the inputs of the selection of the corresponding memory blocks of the second group, the corresponding information outputs of which are combined and are information outputs of the buffer memory of the device, characterized in that in order to expand the scope by organizing parallel recording information in several memory cells, the buffer memory contains the OR element and the third counter, the outputs of which are connected to the address inputs of all the memory blocks of the second group , to the information inputs of which the information outputs of the corresponding memory blocks of the first group are connected, to the selection inputs of which the corresponding outputs of the multiplexer are connected, the information inputs of the first group of which are the address inputs of the first group of the buffer memory, 0 information inputs of the second group of the multiplexer and the first the input of the control unit is connected to the logical bus "I, the first output of the control unit is connected to the inputs of the multiplexer and the decoder selection, the second output of the control unit of the coupling is 5 dinen with the counting input of the first counter and the second input of the OR element, the output of which is connected to the counting input of the third counter, the last output of which is connected to the eighth input of the control unit, the reset input of the third counter is combined with the reset input of the second counter, the overflow output of which is connected to the first input of the element OR, the third output of the control unit is connected to the recording resolution inputs of all the memory blocks of the second group. (puS-1 fig