SU1171993A1 - Recursive digital filter - Google Patents

Abstract

A RECURSIVE ODFREAM FILTER, containing the first block of AND elements, the first input of which is the input of a recursive digital filter, the second block of AND elements, sequentially connected the third block of And elements, and the first adder, serially connected the first memory block, the second multiplier and the second adder, sequentially connected the second block of memory and the first multiplier, a tel, the fourth block of And elements and the third adder, as well as the fifth and sixth blocks, the ki elements of And, and a synchronization block, cat outputs connected to the second inputs of all blocks of the Ink elements to the control inputs of the first and second memory blocks, characterized in that, in order to increase the operation stability, the first shift register connected between the output of the first block of AND elements and the first input of the second block of elements is entered into it- And, the output of which is connected to the second input of the first adder, the second shift register, connected between the output of the first adder and the combined second input of the first multiplier and the first input of the fifth block of And elements, between the output which and the first input of the third block of elements And are connected in series the first inverter and the third shift register, the fourth shift register, the input of which is connected to the output of the second adder, and the output connected to the first input of the Fourth block of elements AND, is the output of the recursive digital filter, the fifth shift register connected between the output of the third adder and the combined second input of the second multiplier with the first input of the sixth block of elements And, between the output of which and the second input of the third The second mapper is connected in series with the second inverter, the sixth shift register and the seventh AND block, and the output of the first multiplier is connected to the second input from the second adder, the output of the sync block (ronization is paraphase and connected to the second inputs of the second, third and sixth oo And blocks of inputs and control inputs of the first and second blocks of memory, and another output with the second inputs of the first, fourth, fifth, and seventh blocks of elements I.

Description

This invention relates to radio engineering; Nickname and can be used in the subject of digital information processing. The purpose of the invention is to increase the stability of the filter operation. . Figure 1 shows the structural electrical circuit of the recursive filter} in figure 2 is its signal graph, in figure 3 the diagrams of the operation of the synchronization unit. The recursive digital filter contains the first, second, third, fourth, fifth, sixth and seventh blocks of elements And 1-7 ,. The first, second, third, fourth, fifth, and sixth shift registers 8–13, the first, second, and third adders 14–16, the first and second multipliers 17 and 18, the first and second blocks 19 and 20 of memory, the first and the second inverters 21 and 22 and the synchronization unit 23. The filter works as follows. The work of the proposed recursive digital filter is described by the system equations, xrK-11 + Csigii P) () UGK-1; XK l X K-1j-H (sign Р). (Sign P)), realizing the transfer function of the form (6ig.2) Before the start of the calculation of the output signal in the first, third, fifth and sixth registers B, 10, 12 and 13 the shift is recorded according to the values of the variables, iXrK-2.4YtK-0 and, where the + sign corresponds to the positive pole of the filter, and the sign - to the negative. The calculations in each cycle are carried out in two steps. At the first stage, on the command 1 produced by the synchronization unit 23 (Fig. 2), the enabling signals to the second, third and sixth blocks of the AND 2.3 and 6 elements and the control inputs of the first and second memory blocks 19 and 20 are supplied, in which coefficient values are stored. Next, the values of the variables and iXtK-23 are fed to the inputs of the first adder 14. The value of the sum. written to the shift register 9 and fed to the second input of the first multiplier 17, to the second input of which the output of the first memory block 19 is supplied; the value of the coefficient a. The product signal KL is fed to the first input of the second adder 15. Simultaneously, the second input from the output of the second multiplication unit 18 receives the output signal (sign P) (| P | -1), for which the multiplications of the output of the second unit 18 are received. Signals are given (sign P) (iPj-l) from the output of the second memory block 20 and the fifth shift register 12, respectively. The sum signal .1 a, + (sign P) (| Pl-1), which is the output signal of the recursive digital filter, is written to the fourth shift register 11 and goes to the output of the filter. Simultaneously, the signal from the output of the p of the 12 shift register - through the sixth block of elements And 6 and the second inverter 22 enters the sixth; shift register 13 In the second clock cycle (Fig. 2), the values of variables necessary for calculating the output of the filter in the next clock cycle are formed and written into the first, third and fifth registers 8, 10 and 12 of the shift. For this, p. O command 2 of synchronization unit 23 is supplied to enable the signal on the first, fourth, fifth and seventh blocks of the elements 1,4,5 and 7, at the same time the input signal. from the information input of the filter through the first block of elements AND 1 enters the first shift register 8, the signal from the second shift register 9 through the fifth block of AND blocks 5 and the first inverter 21 is fed to the third shift register 10, to the inputs of the third summer 16 simultaneously coming from the output of the recursive digital filter through the fourth block of elements And 4 signal and from the sixth register 13 shift through the seventh block of elements And 7 signal i, a. the sum signal is written into the fifth shift register 12. In the next (K + 1) -th calculation cycle, the operation of the recursive digital filter is described similarly. Thus, in each clock cycle of the computational process, the output of the filter generates the value of the output signal, the data necessary for the calculations in the next clock cycle are determined and recorded in the corresponding shift registers.

3 The first and second inverters 21 and 22 serve to invert the characters of the signals arriving at their inputs at the pole values of the recursive digital filter. No inverting is required and these inverters may be missing.

The round error error dispersion of the proposed recursive digital filter is

Gg 3 H-IPI

known -

 (g 12 1 + 1PI

Therefore, the error of the proposed recursive digital filter does not depend on the values of the coefficient a, the numerator of its transfer function 719934

and the error of the known filter grows with an increase in this coefficient. the accuracy of the proposed filter in the implementation of transfer functions, J having sufficiently large values of the coefficient, can be significantly higher than the accuracy of the known. As follows from the above expressions, the proposed filter has, compared with the known, lower dispersion value of the error when the inequality is satisfied

Sj (,, 2al. 8 1 12 1 + 1РГ 3 I + IPI

which is equivalent to the condition 1P1 3-2a |,

determines the ratio between a pair of 0 meters of the transfer function, in which the proposed filter has a smaller error than the known one.

1 /

fit

GM

ffpff)

rffz) r, (i)

 V yfzy

±

Zf

Fig.Z

Claims (1)

A recursive digital filter containing the first block of elements AND, the first input of which is the input of a recursive digital filter, the second block of elements And, the third block of elements And connected in series, the first adder, the first memory block connected in series, the second multiplier and the second adder, the second block connected in series memory and the first multiplier, connected in series with the fourth block of AND elements and the third adder, as well as the fifth and sixth blocks, ki elements AND, and a synchronization unit, the outputs of which are are connected to the second inputs of all blocks of AND elements and to the control inputs of the first and second memory blocks, characterized in that, in order to increase the stability of operation, the first shift register is inserted into it, included between the output of the first block of AND elements and the first input of the second block of elements - And, the output of which is connected to the second input of the first adder, the second shift register is connected between the output of the first adder and the combined second input of the first multiplier and the first input of the fifth block of AND elements, between the output of which and the first the input of the third block of AND elements includes the first inverter and the third shift register, the fourth shift register, the input of which is connected to the output of the second adder, and the output is connected to the first input of the fourth block of AND elements and is the output of a recursive digital filter, the fifth shift register is on between the output of the third adder and the combined second input of the second multiplier with the first input of the sixth block of AND elements, between the output of which and the second input of the third adder are connected Tel'nykh connected a second inverter, the sixth shift register and the seventh block of AND gates, the output of the first multiplier is connected to a second input ⁴ of the second adder, the output synchronization unit is paraphase and connected at one terminal to the second inputs of the second, third and sixth elements blocks D and the control inputs the first and second blocks of memory, and the other conclusion - with the second inputs of the first, fourth, fifth and seventh blocks of elements I. y [k] = _a) x X [K-1] = X Y [K-1T = y